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flash/nor/stm32f1x: remove write alignment code
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t hwords_count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 /* The flash write must be aligned to a halfword boundary */
155 bank->write_start_alignment = bank->write_end_alignment = 2;
156
157 return ERROR_OK;
158 }
159
160 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
161 {
162 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
163 return reg + stm32x_info->register_base;
164 }
165
166 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
167 {
168 struct target *target = bank->target;
169 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
170 }
171
172 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
173 {
174 struct target *target = bank->target;
175 uint32_t status;
176 int retval = ERROR_OK;
177
178 /* wait for busy to clear */
179 for (;;) {
180 retval = stm32x_get_flash_status(bank, &status);
181 if (retval != ERROR_OK)
182 return retval;
183 LOG_DEBUG("status: 0x%" PRIx32 "", status);
184 if ((status & FLASH_BSY) == 0)
185 break;
186 if (timeout-- <= 0) {
187 LOG_ERROR("timed out waiting for flash");
188 return ERROR_FAIL;
189 }
190 alive_sleep(1);
191 }
192
193 if (status & FLASH_WRPRTERR) {
194 LOG_ERROR("stm32x device protected");
195 retval = ERROR_FAIL;
196 }
197
198 if (status & FLASH_PGERR) {
199 LOG_ERROR("stm32x device programming failed");
200 retval = ERROR_FAIL;
201 }
202
203 /* Clear but report errors */
204 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
205 /* If this operation fails, we ignore it and report the original
206 * retval
207 */
208 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
209 FLASH_WRPRTERR | FLASH_PGERR);
210 }
211 return retval;
212 }
213
214 static int stm32x_check_operation_supported(struct flash_bank *bank)
215 {
216 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
217
218 /* if we have a dual flash bank device then
219 * we need to perform option byte stuff on bank0 only */
220 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
221 LOG_ERROR("Option byte operations must use bank 0");
222 return ERROR_FLASH_OPERATION_FAILED;
223 }
224
225 return ERROR_OK;
226 }
227
228 static int stm32x_read_options(struct flash_bank *bank)
229 {
230 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
231 struct target *target = bank->target;
232 uint32_t option_bytes;
233 int retval;
234
235 /* read user and read protection option bytes, user data option bytes */
236 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
237 if (retval != ERROR_OK)
238 return retval;
239
240 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
241 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
242 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
243
244 /* read write protection option bytes */
245 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
246 if (retval != ERROR_OK)
247 return retval;
248
249 return ERROR_OK;
250 }
251
252 static int stm32x_erase_options(struct flash_bank *bank)
253 {
254 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
255 struct target *target = bank->target;
256
257 /* read current options */
258 stm32x_read_options(bank);
259
260 /* unlock flash registers */
261 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
266 if (retval != ERROR_OK)
267 return retval;
268
269 /* unlock option flash registers */
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
271 if (retval != ERROR_OK)
272 return retval;
273 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
274 if (retval != ERROR_OK)
275 return retval;
276
277 /* erase option bytes */
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
282 if (retval != ERROR_OK)
283 return retval;
284
285 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
286 if (retval != ERROR_OK)
287 return retval;
288
289 /* clear read protection option byte
290 * this will also force a device unlock if set */
291 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
292
293 return ERROR_OK;
294 }
295
296 static int stm32x_write_options(struct flash_bank *bank)
297 {
298 struct stm32x_flash_bank *stm32x_info = NULL;
299 struct target *target = bank->target;
300
301 stm32x_info = bank->driver_priv;
302
303 /* unlock flash registers */
304 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
305 if (retval != ERROR_OK)
306 return retval;
307 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
308 if (retval != ERROR_OK)
309 return retval;
310
311 /* unlock option flash registers */
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
313 if (retval != ERROR_OK)
314 return retval;
315 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* program option bytes */
320 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
321 if (retval != ERROR_OK)
322 return retval;
323
324 uint8_t opt_bytes[16];
325
326 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
327 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
328 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
331 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
332 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
334
335 /* Block write is preferred in favour of operation with ancient ST-Link
336 * firmwares without 16-bit memory access. See
337 * 480: flash: stm32f1x: write option bytes using the loader
338 * https://review.openocd.org/c/openocd/+/480
339 */
340 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
341 if (retval != ERROR_OK)
342 return retval;
343
344 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
345 if (retval != ERROR_OK)
346 return retval;
347
348 return ERROR_OK;
349 }
350
351 static int stm32x_protect_check(struct flash_bank *bank)
352 {
353 struct target *target = bank->target;
354 uint32_t protection;
355
356 int retval = stm32x_check_operation_supported(bank);
357 if (retval != ERROR_OK)
358 return retval;
359
360 /* medium density - each bit refers to a 4 sector protection block
361 * high density - each bit refers to a 2 sector protection block
362 * bit 31 refers to all remaining sectors in a bank */
363 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
364 if (retval != ERROR_OK)
365 return retval;
366
367 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
368 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
369
370 return ERROR_OK;
371 }
372
373 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
374 unsigned int last)
375 {
376 struct target *target = bank->target;
377
378 if (bank->target->state != TARGET_HALTED) {
379 LOG_ERROR("Target not halted");
380 return ERROR_TARGET_NOT_HALTED;
381 }
382
383 if ((first == 0) && (last == (bank->num_sectors - 1)))
384 return stm32x_mass_erase(bank);
385
386 /* unlock flash registers */
387 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
388 if (retval != ERROR_OK)
389 return retval;
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
391 if (retval != ERROR_OK)
392 return retval;
393
394 for (unsigned int i = first; i <= last; i++) {
395 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
396 if (retval != ERROR_OK)
397 return retval;
398 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
399 bank->base + bank->sectors[i].offset);
400 if (retval != ERROR_OK)
401 return retval;
402 retval = target_write_u32(target,
403 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
404 if (retval != ERROR_OK)
405 return retval;
406
407 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
408 if (retval != ERROR_OK)
409 return retval;
410 }
411
412 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
413 if (retval != ERROR_OK)
414 return retval;
415
416 return ERROR_OK;
417 }
418
419 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
420 unsigned int last)
421 {
422 struct target *target = bank->target;
423 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
424
425 if (target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 int retval = stm32x_check_operation_supported(bank);
431 if (retval != ERROR_OK)
432 return retval;
433
434 retval = stm32x_erase_options(bank);
435 if (retval != ERROR_OK) {
436 LOG_ERROR("stm32x failed to erase options");
437 return retval;
438 }
439
440 for (unsigned int i = first; i <= last; i++) {
441 if (set)
442 stm32x_info->option_bytes.protection &= ~(1 << i);
443 else
444 stm32x_info->option_bytes.protection |= (1 << i);
445 }
446
447 return stm32x_write_options(bank);
448 }
449
450 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
451 uint32_t address, uint32_t hwords_count)
452 {
453 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
454 struct target *target = bank->target;
455 uint32_t buffer_size = 16384;
456 struct working_area *write_algorithm;
457 struct working_area *source;
458 struct reg_param reg_params[5];
459 struct armv7m_algorithm armv7m_info;
460 int retval = ERROR_OK;
461
462 static const uint8_t stm32x_flash_write_code[] = {
463 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
464 };
465
466 /* flash write code */
467 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
468 &write_algorithm) != ERROR_OK) {
469 LOG_WARNING("no working area available, can't do block memory writes");
470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
471 }
472
473 retval = target_write_buffer(target, write_algorithm->address,
474 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
475 if (retval != ERROR_OK) {
476 target_free_working_area(target, write_algorithm);
477 return retval;
478 }
479
480 /* memory buffer */
481 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
482 buffer_size /= 2;
483 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
484 if (buffer_size <= 256) {
485 /* we already allocated the writing code, but failed to get a
486 * buffer, free the algorithm */
487 target_free_working_area(target, write_algorithm);
488
489 LOG_WARNING("no large enough working area available, can't do block memory writes");
490 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
491 }
492 }
493
494 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
495 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
496 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
497 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
498 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
499
500 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
501 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
502 buf_set_u32(reg_params[2].value, 0, 32, source->address);
503 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
504 buf_set_u32(reg_params[4].value, 0, 32, address);
505
506 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
507 armv7m_info.core_mode = ARM_MODE_THREAD;
508
509 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
510 0, NULL,
511 5, reg_params,
512 source->address, source->size,
513 write_algorithm->address, 0,
514 &armv7m_info);
515
516 if (retval == ERROR_FLASH_OPERATION_FAILED) {
517 LOG_ERROR("flash write failed at address 0x%"PRIx32,
518 buf_get_u32(reg_params[4].value, 0, 32));
519
520 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
521 LOG_ERROR("flash memory not erased before writing");
522 /* Clear but report errors */
523 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
524 }
525
526 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
527 LOG_ERROR("flash memory write protected");
528 /* Clear but report errors */
529 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
530 }
531 }
532
533 target_free_working_area(target, source);
534 target_free_working_area(target, write_algorithm);
535
536 destroy_reg_param(&reg_params[0]);
537 destroy_reg_param(&reg_params[1]);
538 destroy_reg_param(&reg_params[2]);
539 destroy_reg_param(&reg_params[3]);
540 destroy_reg_param(&reg_params[4]);
541
542 return retval;
543 }
544
545 /** Writes a block to flash either using target algorithm
546 * or use fallback, host controlled halfword-by-halfword access.
547 * Flash controller must be unlocked before this call.
548 */
549 static int stm32x_write_block(struct flash_bank *bank,
550 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
551 {
552 struct target *target = bank->target;
553
554 /* The flash write must be aligned to a halfword boundary.
555 * The flash infrastructure ensures it, do just a security check
556 */
557 assert(address % 2 == 0);
558
559 /* try using a block write - on ARM architecture or... */
560 int retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
561
562 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
563 /* if block write failed (no sufficient working area),
564 * we use normal (slow) single halfword accesses */
565 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
566
567 while (hwords_count > 0) {
568 retval = target_write_memory(target, address, 2, 1, buffer);
569 if (retval != ERROR_OK)
570 return retval;
571
572 retval = stm32x_wait_status_busy(bank, 5);
573 if (retval != ERROR_OK)
574 return retval;
575
576 hwords_count--;
577 buffer += 2;
578 address += 2;
579 }
580 }
581 return retval;
582 }
583
584 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
585 uint32_t offset, uint32_t count)
586 {
587 struct target *target = bank->target;
588
589 if (bank->target->state != TARGET_HALTED) {
590 LOG_ERROR("Target not halted");
591 return ERROR_TARGET_NOT_HALTED;
592 }
593
594 /* The flash write must be aligned to a halfword boundary.
595 * The flash infrastructure ensures it, do just a security check
596 */
597 assert(offset % 2 == 0);
598 assert(count % 2 == 0);
599
600 int retval, retval2;
601
602 /* unlock flash registers */
603 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
604 if (retval != ERROR_OK)
605 return retval;
606 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
607 if (retval != ERROR_OK)
608 goto reset_pg_and_lock;
609
610 /* enable flash programming */
611 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
612 if (retval != ERROR_OK)
613 goto reset_pg_and_lock;
614
615 /* write to flash */
616 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
617
618 reset_pg_and_lock:
619 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
620 if (retval == ERROR_OK)
621 retval = retval2;
622
623 return retval;
624 }
625
626 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
627 {
628 struct target *target = bank->target;
629 uint32_t device_id_register = 0;
630
631 if (!target_was_examined(target)) {
632 LOG_ERROR("Target not examined yet");
633 return ERROR_TARGET_NOT_EXAMINED;
634 }
635
636 switch (cortex_m_get_partno_safe(target)) {
637 case CORTEX_M0_PARTNO: /* STM32F0x devices */
638 device_id_register = 0x40015800;
639 break;
640 case CORTEX_M3_PARTNO: /* STM32F1x devices */
641 device_id_register = 0xE0042000;
642 break;
643 case CORTEX_M4_PARTNO: /* STM32F3x devices */
644 device_id_register = 0xE0042000;
645 break;
646 case CORTEX_M23_PARTNO: /* GD32E23x devices */
647 device_id_register = 0x40015800;
648 break;
649 default:
650 LOG_ERROR("Cannot identify target as a stm32x");
651 return ERROR_FAIL;
652 }
653
654 /* read stm32 device id register */
655 int retval = target_read_u32(target, device_id_register, device_id);
656 if (retval != ERROR_OK)
657 return retval;
658
659 return retval;
660 }
661
662 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
663 {
664 struct target *target = bank->target;
665 uint32_t flash_size_reg;
666
667 if (!target_was_examined(target)) {
668 LOG_ERROR("Target not examined yet");
669 return ERROR_TARGET_NOT_EXAMINED;
670 }
671
672 switch (cortex_m_get_partno_safe(target)) {
673 case CORTEX_M0_PARTNO: /* STM32F0x devices */
674 flash_size_reg = 0x1FFFF7CC;
675 break;
676 case CORTEX_M3_PARTNO: /* STM32F1x devices */
677 flash_size_reg = 0x1FFFF7E0;
678 break;
679 case CORTEX_M4_PARTNO: /* STM32F3x devices */
680 flash_size_reg = 0x1FFFF7CC;
681 break;
682 case CORTEX_M23_PARTNO: /* GD32E23x devices */
683 flash_size_reg = 0x1FFFF7E0;
684 break;
685 default:
686 LOG_ERROR("Cannot identify target as a stm32x");
687 return ERROR_FAIL;
688 }
689
690 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
691 if (retval != ERROR_OK)
692 return retval;
693
694 return retval;
695 }
696
697 static int stm32x_probe(struct flash_bank *bank)
698 {
699 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
700 uint16_t flash_size_in_kb;
701 uint16_t max_flash_size_in_kb;
702 uint32_t dbgmcu_idcode;
703 int page_size;
704 uint32_t base_address = 0x08000000;
705
706 stm32x_info->probed = false;
707 stm32x_info->register_base = FLASH_REG_BASE_B0;
708 stm32x_info->user_data_offset = 10;
709 stm32x_info->option_offset = 0;
710
711 /* default factory read protection level 0 */
712 stm32x_info->default_rdp = 0xA5;
713
714 /* read stm32 device id register */
715 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
716 if (retval != ERROR_OK)
717 return retval;
718
719 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
720
721 uint16_t device_id = dbgmcu_idcode & 0xfff;
722 uint16_t rev_id = dbgmcu_idcode >> 16;
723
724 /* set page size, protection granularity and max flash size depending on family */
725 switch (device_id) {
726 case 0x440: /* stm32f05x */
727 page_size = 1024;
728 stm32x_info->ppage_size = 4;
729 max_flash_size_in_kb = 64;
730 stm32x_info->user_data_offset = 16;
731 stm32x_info->option_offset = 6;
732 stm32x_info->default_rdp = 0xAA;
733 stm32x_info->can_load_options = true;
734 break;
735 case 0x444: /* stm32f03x */
736 case 0x445: /* stm32f04x */
737 page_size = 1024;
738 stm32x_info->ppage_size = 4;
739 max_flash_size_in_kb = 32;
740 stm32x_info->user_data_offset = 16;
741 stm32x_info->option_offset = 6;
742 stm32x_info->default_rdp = 0xAA;
743 stm32x_info->can_load_options = true;
744 break;
745 case 0x448: /* stm32f07x */
746 page_size = 2048;
747 stm32x_info->ppage_size = 4;
748 max_flash_size_in_kb = 128;
749 stm32x_info->user_data_offset = 16;
750 stm32x_info->option_offset = 6;
751 stm32x_info->default_rdp = 0xAA;
752 stm32x_info->can_load_options = true;
753 break;
754 case 0x442: /* stm32f09x */
755 page_size = 2048;
756 stm32x_info->ppage_size = 4;
757 max_flash_size_in_kb = 256;
758 stm32x_info->user_data_offset = 16;
759 stm32x_info->option_offset = 6;
760 stm32x_info->default_rdp = 0xAA;
761 stm32x_info->can_load_options = true;
762 break;
763 case 0x410: /* stm32f1x medium-density */
764 page_size = 1024;
765 stm32x_info->ppage_size = 4;
766 max_flash_size_in_kb = 128;
767 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
768 share DEV_ID with STM32F101/2/3 medium-density line,
769 however they use a REV_ID different from any STM32 device.
770 The main difference is another offset of user option bits
771 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
772 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
773 This caused problems e.g. during flash block programming
774 because of unexpected active hardware watchog. */
775 switch (rev_id) {
776 case 0x1303: /* gd32f1x0 */
777 stm32x_info->user_data_offset = 16;
778 stm32x_info->option_offset = 6;
779 max_flash_size_in_kb = 64;
780 break;
781 case 0x1704: /* gd32f3x0 */
782 stm32x_info->user_data_offset = 16;
783 stm32x_info->option_offset = 6;
784 break;
785 case 0x1909: /* gd32e23x */
786 stm32x_info->user_data_offset = 16;
787 stm32x_info->option_offset = 6;
788 max_flash_size_in_kb = 64;
789 break;
790 }
791 break;
792 case 0x412: /* stm32f1x low-density */
793 page_size = 1024;
794 stm32x_info->ppage_size = 4;
795 max_flash_size_in_kb = 32;
796 break;
797 case 0x414: /* stm32f1x high-density */
798 page_size = 2048;
799 stm32x_info->ppage_size = 2;
800 max_flash_size_in_kb = 512;
801 break;
802 case 0x418: /* stm32f1x connectivity */
803 page_size = 2048;
804 stm32x_info->ppage_size = 2;
805 max_flash_size_in_kb = 256;
806 break;
807 case 0x430: /* stm32f1 XL-density (dual flash banks) */
808 page_size = 2048;
809 stm32x_info->ppage_size = 2;
810 max_flash_size_in_kb = 1024;
811 stm32x_info->has_dual_banks = true;
812 break;
813 case 0x420: /* stm32f100xx low- and medium-density value line */
814 page_size = 1024;
815 stm32x_info->ppage_size = 4;
816 max_flash_size_in_kb = 128;
817 break;
818 case 0x428: /* stm32f100xx high-density value line */
819 page_size = 2048;
820 stm32x_info->ppage_size = 4;
821 max_flash_size_in_kb = 512;
822 break;
823 case 0x422: /* stm32f302/3xb/c */
824 page_size = 2048;
825 stm32x_info->ppage_size = 2;
826 max_flash_size_in_kb = 256;
827 stm32x_info->user_data_offset = 16;
828 stm32x_info->option_offset = 6;
829 stm32x_info->default_rdp = 0xAA;
830 stm32x_info->can_load_options = true;
831 break;
832 case 0x446: /* stm32f303xD/E */
833 page_size = 2048;
834 stm32x_info->ppage_size = 2;
835 max_flash_size_in_kb = 512;
836 stm32x_info->user_data_offset = 16;
837 stm32x_info->option_offset = 6;
838 stm32x_info->default_rdp = 0xAA;
839 stm32x_info->can_load_options = true;
840 break;
841 case 0x432: /* stm32f37x */
842 page_size = 2048;
843 stm32x_info->ppage_size = 2;
844 max_flash_size_in_kb = 256;
845 stm32x_info->user_data_offset = 16;
846 stm32x_info->option_offset = 6;
847 stm32x_info->default_rdp = 0xAA;
848 stm32x_info->can_load_options = true;
849 break;
850 case 0x438: /* stm32f33x */
851 case 0x439: /* stm32f302x6/8 */
852 page_size = 2048;
853 stm32x_info->ppage_size = 2;
854 max_flash_size_in_kb = 64;
855 stm32x_info->user_data_offset = 16;
856 stm32x_info->option_offset = 6;
857 stm32x_info->default_rdp = 0xAA;
858 stm32x_info->can_load_options = true;
859 break;
860 default:
861 LOG_WARNING("Cannot identify target as a STM32 family.");
862 return ERROR_FAIL;
863 }
864
865 /* get flash size from target. */
866 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
867
868 /* failed reading flash size or flash size invalid (early silicon),
869 * default to max target family */
870 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
871 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
872 max_flash_size_in_kb);
873 flash_size_in_kb = max_flash_size_in_kb;
874 }
875
876 if (stm32x_info->has_dual_banks) {
877 /* split reported size into matching bank */
878 if (bank->base != 0x08080000) {
879 /* bank 0 will be fixed 512k */
880 flash_size_in_kb = 512;
881 } else {
882 flash_size_in_kb -= 512;
883 /* bank1 also uses a register offset */
884 stm32x_info->register_base = FLASH_REG_BASE_B1;
885 base_address = 0x08080000;
886 }
887 }
888
889 /* if the user sets the size manually then ignore the probed value
890 * this allows us to work around devices that have a invalid flash size register value */
891 if (stm32x_info->user_bank_size) {
892 LOG_INFO("ignoring flash probed value, using configured bank size");
893 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
894 }
895
896 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
897
898 /* did we assign flash size? */
899 assert(flash_size_in_kb != 0xffff);
900
901 /* calculate numbers of pages */
902 int num_pages = flash_size_in_kb * 1024 / page_size;
903
904 /* check that calculation result makes sense */
905 assert(num_pages > 0);
906
907 free(bank->sectors);
908 bank->sectors = NULL;
909
910 free(bank->prot_blocks);
911 bank->prot_blocks = NULL;
912
913 bank->base = base_address;
914 bank->size = (num_pages * page_size);
915
916 bank->num_sectors = num_pages;
917 bank->sectors = alloc_block_array(0, page_size, num_pages);
918 if (!bank->sectors)
919 return ERROR_FAIL;
920
921 /* calculate number of write protection blocks */
922 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
923 if (num_prot_blocks > 32)
924 num_prot_blocks = 32;
925
926 bank->num_prot_blocks = num_prot_blocks;
927 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
928 if (!bank->prot_blocks)
929 return ERROR_FAIL;
930
931 if (num_prot_blocks == 32)
932 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
933
934 stm32x_info->probed = true;
935
936 return ERROR_OK;
937 }
938
939 static int stm32x_auto_probe(struct flash_bank *bank)
940 {
941 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
942 if (stm32x_info->probed)
943 return ERROR_OK;
944 return stm32x_probe(bank);
945 }
946
947 #if 0
948 COMMAND_HANDLER(stm32x_handle_part_id_command)
949 {
950 return ERROR_OK;
951 }
952 #endif
953
954 static const char *get_stm32f0_revision(uint16_t rev_id)
955 {
956 const char *rev_str = NULL;
957
958 switch (rev_id) {
959 case 0x1000:
960 rev_str = "1.0";
961 break;
962 case 0x2000:
963 rev_str = "2.0";
964 break;
965 }
966 return rev_str;
967 }
968
969 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
970 {
971 uint32_t dbgmcu_idcode;
972
973 /* read stm32 device id register */
974 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
975 if (retval != ERROR_OK)
976 return retval;
977
978 uint16_t device_id = dbgmcu_idcode & 0xfff;
979 uint16_t rev_id = dbgmcu_idcode >> 16;
980 const char *device_str;
981 const char *rev_str = NULL;
982
983 switch (device_id) {
984 case 0x410:
985 device_str = "STM32F10x (Medium Density)";
986
987 switch (rev_id) {
988 case 0x0000:
989 rev_str = "A";
990 break;
991
992 case 0x1303: /* gd32f1x0 */
993 device_str = "GD32F1x0";
994 break;
995
996 case 0x1704: /* gd32f3x0 */
997 device_str = "GD32F3x0";
998 break;
999
1000 case 0x1909: /* gd32e23x */
1001 device_str = "GD32E23x";
1002 break;
1003
1004 case 0x2000:
1005 rev_str = "B";
1006 break;
1007
1008 case 0x2001:
1009 rev_str = "Z";
1010 break;
1011
1012 case 0x2003:
1013 rev_str = "Y";
1014 break;
1015 }
1016 break;
1017
1018 case 0x412:
1019 device_str = "STM32F10x (Low Density)";
1020
1021 switch (rev_id) {
1022 case 0x1000:
1023 rev_str = "A";
1024 break;
1025 }
1026 break;
1027
1028 case 0x414:
1029 device_str = "STM32F10x (High Density)";
1030
1031 switch (rev_id) {
1032 case 0x1000:
1033 rev_str = "A";
1034 break;
1035
1036 case 0x1001:
1037 rev_str = "Z";
1038 break;
1039
1040 case 0x1003:
1041 rev_str = "Y";
1042 break;
1043 }
1044 break;
1045
1046 case 0x418:
1047 device_str = "STM32F10x (Connectivity)";
1048
1049 switch (rev_id) {
1050 case 0x1000:
1051 rev_str = "A";
1052 break;
1053
1054 case 0x1001:
1055 rev_str = "Z";
1056 break;
1057 }
1058 break;
1059
1060 case 0x420:
1061 device_str = "STM32F100 (Low/Medium Density)";
1062
1063 switch (rev_id) {
1064 case 0x1000:
1065 rev_str = "A";
1066 break;
1067
1068 case 0x1001:
1069 rev_str = "Z";
1070 break;
1071 }
1072 break;
1073
1074 case 0x422:
1075 device_str = "STM32F302xB/C";
1076
1077 switch (rev_id) {
1078 case 0x1000:
1079 rev_str = "A";
1080 break;
1081
1082 case 0x1001:
1083 rev_str = "Z";
1084 break;
1085
1086 case 0x1003:
1087 rev_str = "Y";
1088 break;
1089
1090 case 0x2000:
1091 rev_str = "B";
1092 break;
1093 }
1094 break;
1095
1096 case 0x428:
1097 device_str = "STM32F100 (High Density)";
1098
1099 switch (rev_id) {
1100 case 0x1000:
1101 rev_str = "A";
1102 break;
1103
1104 case 0x1001:
1105 rev_str = "Z";
1106 break;
1107 }
1108 break;
1109
1110 case 0x430:
1111 device_str = "STM32F10x (XL Density)";
1112
1113 switch (rev_id) {
1114 case 0x1000:
1115 rev_str = "A";
1116 break;
1117 }
1118 break;
1119
1120 case 0x432:
1121 device_str = "STM32F37x";
1122
1123 switch (rev_id) {
1124 case 0x1000:
1125 rev_str = "A";
1126 break;
1127
1128 case 0x2000:
1129 rev_str = "B";
1130 break;
1131 }
1132 break;
1133
1134 case 0x438:
1135 device_str = "STM32F33x";
1136
1137 switch (rev_id) {
1138 case 0x1000:
1139 rev_str = "A";
1140 break;
1141 }
1142 break;
1143
1144 case 0x439:
1145 device_str = "STM32F302x6/8";
1146
1147 switch (rev_id) {
1148 case 0x1000:
1149 rev_str = "A";
1150 break;
1151
1152 case 0x1001:
1153 rev_str = "Z";
1154 break;
1155 }
1156 break;
1157
1158 case 0x444:
1159 device_str = "STM32F03x";
1160 rev_str = get_stm32f0_revision(rev_id);
1161 break;
1162
1163 case 0x440:
1164 device_str = "STM32F05x";
1165 rev_str = get_stm32f0_revision(rev_id);
1166 break;
1167
1168 case 0x445:
1169 device_str = "STM32F04x";
1170 rev_str = get_stm32f0_revision(rev_id);
1171 break;
1172
1173 case 0x446:
1174 device_str = "STM32F303xD/E";
1175 switch (rev_id) {
1176 case 0x1000:
1177 rev_str = "A";
1178 break;
1179 }
1180 break;
1181
1182 case 0x448:
1183 device_str = "STM32F07x";
1184 rev_str = get_stm32f0_revision(rev_id);
1185 break;
1186
1187 case 0x442:
1188 device_str = "STM32F09x";
1189 rev_str = get_stm32f0_revision(rev_id);
1190 break;
1191
1192 default:
1193 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1194 return ERROR_FAIL;
1195 }
1196
1197 if (rev_str)
1198 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1199 else
1200 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1201
1202 return ERROR_OK;
1203 }
1204
1205 COMMAND_HANDLER(stm32x_handle_lock_command)
1206 {
1207 struct target *target = NULL;
1208 struct stm32x_flash_bank *stm32x_info = NULL;
1209
1210 if (CMD_ARGC < 1)
1211 return ERROR_COMMAND_SYNTAX_ERROR;
1212
1213 struct flash_bank *bank;
1214 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1215 if (retval != ERROR_OK)
1216 return retval;
1217
1218 stm32x_info = bank->driver_priv;
1219
1220 target = bank->target;
1221
1222 if (target->state != TARGET_HALTED) {
1223 LOG_ERROR("Target not halted");
1224 return ERROR_TARGET_NOT_HALTED;
1225 }
1226
1227 retval = stm32x_check_operation_supported(bank);
1228 if (retval != ERROR_OK)
1229 return retval;
1230
1231 if (stm32x_erase_options(bank) != ERROR_OK) {
1232 command_print(CMD, "stm32x failed to erase options");
1233 return ERROR_OK;
1234 }
1235
1236 /* set readout protection */
1237 stm32x_info->option_bytes.rdp = 0;
1238
1239 if (stm32x_write_options(bank) != ERROR_OK) {
1240 command_print(CMD, "stm32x failed to lock device");
1241 return ERROR_OK;
1242 }
1243
1244 command_print(CMD, "stm32x locked");
1245
1246 return ERROR_OK;
1247 }
1248
1249 COMMAND_HANDLER(stm32x_handle_unlock_command)
1250 {
1251 struct target *target = NULL;
1252
1253 if (CMD_ARGC < 1)
1254 return ERROR_COMMAND_SYNTAX_ERROR;
1255
1256 struct flash_bank *bank;
1257 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1258 if (retval != ERROR_OK)
1259 return retval;
1260
1261 target = bank->target;
1262
1263 if (target->state != TARGET_HALTED) {
1264 LOG_ERROR("Target not halted");
1265 return ERROR_TARGET_NOT_HALTED;
1266 }
1267
1268 retval = stm32x_check_operation_supported(bank);
1269 if (retval != ERROR_OK)
1270 return retval;
1271
1272 if (stm32x_erase_options(bank) != ERROR_OK) {
1273 command_print(CMD, "stm32x failed to erase options");
1274 return ERROR_OK;
1275 }
1276
1277 if (stm32x_write_options(bank) != ERROR_OK) {
1278 command_print(CMD, "stm32x failed to unlock device");
1279 return ERROR_OK;
1280 }
1281
1282 command_print(CMD, "stm32x unlocked.\n"
1283 "INFO: a reset or power cycle is required "
1284 "for the new settings to take effect.");
1285
1286 return ERROR_OK;
1287 }
1288
1289 COMMAND_HANDLER(stm32x_handle_options_read_command)
1290 {
1291 uint32_t optionbyte, protection;
1292 struct target *target = NULL;
1293 struct stm32x_flash_bank *stm32x_info = NULL;
1294
1295 if (CMD_ARGC < 1)
1296 return ERROR_COMMAND_SYNTAX_ERROR;
1297
1298 struct flash_bank *bank;
1299 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1300 if (retval != ERROR_OK)
1301 return retval;
1302
1303 stm32x_info = bank->driver_priv;
1304
1305 target = bank->target;
1306
1307 if (target->state != TARGET_HALTED) {
1308 LOG_ERROR("Target not halted");
1309 return ERROR_TARGET_NOT_HALTED;
1310 }
1311
1312 retval = stm32x_check_operation_supported(bank);
1313 if (retval != ERROR_OK)
1314 return retval;
1315
1316 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1317 if (retval != ERROR_OK)
1318 return retval;
1319
1320 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1321
1322 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1323 if (retval != ERROR_OK)
1324 return retval;
1325
1326 if (optionbyte & (1 << OPT_ERROR))
1327 command_print(CMD, "option byte complement error");
1328
1329 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1330 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1331
1332 command_print(CMD, "read protection: %s",
1333 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1334
1335 /* user option bytes are offset depending on variant */
1336 optionbyte >>= stm32x_info->option_offset;
1337
1338 command_print(CMD, "watchdog: %sware",
1339 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1340
1341 command_print(CMD, "stop mode: %sreset generated upon entry",
1342 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1343
1344 command_print(CMD, "standby mode: %sreset generated upon entry",
1345 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1346
1347 if (stm32x_info->has_dual_banks)
1348 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1349
1350 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1351
1352 return ERROR_OK;
1353 }
1354
1355 COMMAND_HANDLER(stm32x_handle_options_write_command)
1356 {
1357 struct target *target = NULL;
1358 struct stm32x_flash_bank *stm32x_info = NULL;
1359 uint8_t optionbyte;
1360 uint16_t useropt;
1361
1362 if (CMD_ARGC < 2)
1363 return ERROR_COMMAND_SYNTAX_ERROR;
1364
1365 struct flash_bank *bank;
1366 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1367 if (retval != ERROR_OK)
1368 return retval;
1369
1370 stm32x_info = bank->driver_priv;
1371
1372 target = bank->target;
1373
1374 if (target->state != TARGET_HALTED) {
1375 LOG_ERROR("Target not halted");
1376 return ERROR_TARGET_NOT_HALTED;
1377 }
1378
1379 retval = stm32x_check_operation_supported(bank);
1380 if (retval != ERROR_OK)
1381 return retval;
1382
1383 retval = stm32x_read_options(bank);
1384 if (retval != ERROR_OK)
1385 return retval;
1386
1387 /* start with current options */
1388 optionbyte = stm32x_info->option_bytes.user;
1389 useropt = stm32x_info->option_bytes.data;
1390
1391 /* skip over flash bank */
1392 CMD_ARGC--;
1393 CMD_ARGV++;
1394
1395 while (CMD_ARGC) {
1396 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1397 optionbyte |= (1 << 0);
1398 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1399 optionbyte &= ~(1 << 0);
1400 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1401 optionbyte |= (1 << 1);
1402 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1403 optionbyte &= ~(1 << 1);
1404 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1405 optionbyte |= (1 << 2);
1406 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1407 optionbyte &= ~(1 << 2);
1408 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1409 if (CMD_ARGC < 2)
1410 return ERROR_COMMAND_SYNTAX_ERROR;
1411 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1412 CMD_ARGC--;
1413 CMD_ARGV++;
1414 } else if (stm32x_info->has_dual_banks) {
1415 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1416 optionbyte |= (1 << 3);
1417 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1418 optionbyte &= ~(1 << 3);
1419 else
1420 return ERROR_COMMAND_SYNTAX_ERROR;
1421 } else
1422 return ERROR_COMMAND_SYNTAX_ERROR;
1423 CMD_ARGC--;
1424 CMD_ARGV++;
1425 }
1426
1427 if (stm32x_erase_options(bank) != ERROR_OK) {
1428 command_print(CMD, "stm32x failed to erase options");
1429 return ERROR_OK;
1430 }
1431
1432 stm32x_info->option_bytes.user = optionbyte;
1433 stm32x_info->option_bytes.data = useropt;
1434
1435 if (stm32x_write_options(bank) != ERROR_OK) {
1436 command_print(CMD, "stm32x failed to write options");
1437 return ERROR_OK;
1438 }
1439
1440 command_print(CMD, "stm32x write options complete.\n"
1441 "INFO: %spower cycle is required "
1442 "for the new settings to take effect.",
1443 stm32x_info->can_load_options
1444 ? "'stm32f1x options_load' command or " : "");
1445
1446 return ERROR_OK;
1447 }
1448
1449 COMMAND_HANDLER(stm32x_handle_options_load_command)
1450 {
1451 if (CMD_ARGC < 1)
1452 return ERROR_COMMAND_SYNTAX_ERROR;
1453
1454 struct flash_bank *bank;
1455 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1456 if (retval != ERROR_OK)
1457 return retval;
1458
1459 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1460
1461 if (!stm32x_info->can_load_options) {
1462 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1463 "required instead.");
1464 return ERROR_FAIL;
1465 }
1466
1467 struct target *target = bank->target;
1468
1469 if (target->state != TARGET_HALTED) {
1470 LOG_ERROR("Target not halted");
1471 return ERROR_TARGET_NOT_HALTED;
1472 }
1473
1474 retval = stm32x_check_operation_supported(bank);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 /* unlock option flash registers */
1479 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1480 if (retval != ERROR_OK)
1481 return retval;
1482 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1483 if (retval != ERROR_OK)
1484 return retval;
1485
1486 /* force re-load of option bytes - generates software reset */
1487 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1488 if (retval != ERROR_OK)
1489 return retval;
1490
1491 return ERROR_OK;
1492 }
1493
1494 static int stm32x_mass_erase(struct flash_bank *bank)
1495 {
1496 struct target *target = bank->target;
1497
1498 if (target->state != TARGET_HALTED) {
1499 LOG_ERROR("Target not halted");
1500 return ERROR_TARGET_NOT_HALTED;
1501 }
1502
1503 /* unlock option flash registers */
1504 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1505 if (retval != ERROR_OK)
1506 return retval;
1507 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1508 if (retval != ERROR_OK)
1509 return retval;
1510
1511 /* mass erase flash memory */
1512 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1513 if (retval != ERROR_OK)
1514 return retval;
1515 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1516 FLASH_MER | FLASH_STRT);
1517 if (retval != ERROR_OK)
1518 return retval;
1519
1520 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1521 if (retval != ERROR_OK)
1522 return retval;
1523
1524 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1525 if (retval != ERROR_OK)
1526 return retval;
1527
1528 return ERROR_OK;
1529 }
1530
1531 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1532 {
1533 if (CMD_ARGC < 1)
1534 return ERROR_COMMAND_SYNTAX_ERROR;
1535
1536 struct flash_bank *bank;
1537 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1538 if (retval != ERROR_OK)
1539 return retval;
1540
1541 retval = stm32x_mass_erase(bank);
1542 if (retval == ERROR_OK)
1543 command_print(CMD, "stm32x mass erase complete");
1544 else
1545 command_print(CMD, "stm32x mass erase failed");
1546
1547 return retval;
1548 }
1549
1550 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1551 {
1552 .name = "lock",
1553 .handler = stm32x_handle_lock_command,
1554 .mode = COMMAND_EXEC,
1555 .usage = "bank_id",
1556 .help = "Lock entire flash device.",
1557 },
1558 {
1559 .name = "unlock",
1560 .handler = stm32x_handle_unlock_command,
1561 .mode = COMMAND_EXEC,
1562 .usage = "bank_id",
1563 .help = "Unlock entire protected flash device.",
1564 },
1565 {
1566 .name = "mass_erase",
1567 .handler = stm32x_handle_mass_erase_command,
1568 .mode = COMMAND_EXEC,
1569 .usage = "bank_id",
1570 .help = "Erase entire flash device.",
1571 },
1572 {
1573 .name = "options_read",
1574 .handler = stm32x_handle_options_read_command,
1575 .mode = COMMAND_EXEC,
1576 .usage = "bank_id",
1577 .help = "Read and display device option bytes.",
1578 },
1579 {
1580 .name = "options_write",
1581 .handler = stm32x_handle_options_write_command,
1582 .mode = COMMAND_EXEC,
1583 .usage = "bank_id ('SWWDG'|'HWWDG') "
1584 "('RSTSTNDBY'|'NORSTSTNDBY') "
1585 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1586 .help = "Replace bits in device option bytes.",
1587 },
1588 {
1589 .name = "options_load",
1590 .handler = stm32x_handle_options_load_command,
1591 .mode = COMMAND_EXEC,
1592 .usage = "bank_id",
1593 .help = "Force re-load of device option bytes.",
1594 },
1595 COMMAND_REGISTRATION_DONE
1596 };
1597
1598 static const struct command_registration stm32f1x_command_handlers[] = {
1599 {
1600 .name = "stm32f1x",
1601 .mode = COMMAND_ANY,
1602 .help = "stm32f1x flash command group",
1603 .usage = "",
1604 .chain = stm32f1x_exec_command_handlers,
1605 },
1606 COMMAND_REGISTRATION_DONE
1607 };
1608
1609 const struct flash_driver stm32f1x_flash = {
1610 .name = "stm32f1x",
1611 .commands = stm32f1x_command_handlers,
1612 .flash_bank_command = stm32x_flash_bank_command,
1613 .erase = stm32x_erase,
1614 .protect = stm32x_protect,
1615 .write = stm32x_write,
1616 .read = default_flash_read,
1617 .probe = stm32x_probe,
1618 .auto_probe = stm32x_auto_probe,
1619 .erase_check = default_flash_blank_check,
1620 .protect_check = stm32x_protect_check,
1621 .info = get_stm32x_info,
1622 .free_driver_priv = default_flash_free_driver_priv,
1623 };
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