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flash/nor/stm32f1x: tidy up async algo supporting code
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t hwords_count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 /* The flash write must be aligned to a halfword boundary */
155 bank->write_start_alignment = bank->write_end_alignment = 2;
156
157 return ERROR_OK;
158 }
159
160 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
161 {
162 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
163 return reg + stm32x_info->register_base;
164 }
165
166 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
167 {
168 struct target *target = bank->target;
169 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
170 }
171
172 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
173 {
174 struct target *target = bank->target;
175 uint32_t status;
176 int retval = ERROR_OK;
177
178 /* wait for busy to clear */
179 for (;;) {
180 retval = stm32x_get_flash_status(bank, &status);
181 if (retval != ERROR_OK)
182 return retval;
183 LOG_DEBUG("status: 0x%" PRIx32 "", status);
184 if ((status & FLASH_BSY) == 0)
185 break;
186 if (timeout-- <= 0) {
187 LOG_ERROR("timed out waiting for flash");
188 return ERROR_FAIL;
189 }
190 alive_sleep(1);
191 }
192
193 if (status & FLASH_WRPRTERR) {
194 LOG_ERROR("stm32x device protected");
195 retval = ERROR_FAIL;
196 }
197
198 if (status & FLASH_PGERR) {
199 LOG_ERROR("stm32x device programming failed");
200 retval = ERROR_FAIL;
201 }
202
203 /* Clear but report errors */
204 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
205 /* If this operation fails, we ignore it and report the original
206 * retval
207 */
208 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
209 FLASH_WRPRTERR | FLASH_PGERR);
210 }
211 return retval;
212 }
213
214 static int stm32x_check_operation_supported(struct flash_bank *bank)
215 {
216 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
217
218 /* if we have a dual flash bank device then
219 * we need to perform option byte stuff on bank0 only */
220 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
221 LOG_ERROR("Option byte operations must use bank 0");
222 return ERROR_FLASH_OPERATION_FAILED;
223 }
224
225 return ERROR_OK;
226 }
227
228 static int stm32x_read_options(struct flash_bank *bank)
229 {
230 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
231 struct target *target = bank->target;
232 uint32_t option_bytes;
233 int retval;
234
235 /* read user and read protection option bytes, user data option bytes */
236 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
237 if (retval != ERROR_OK)
238 return retval;
239
240 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
241 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
242 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
243
244 /* read write protection option bytes */
245 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
246 if (retval != ERROR_OK)
247 return retval;
248
249 return ERROR_OK;
250 }
251
252 static int stm32x_erase_options(struct flash_bank *bank)
253 {
254 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
255 struct target *target = bank->target;
256
257 /* read current options */
258 stm32x_read_options(bank);
259
260 /* unlock flash registers */
261 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
266 if (retval != ERROR_OK)
267 return retval;
268
269 /* unlock option flash registers */
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
271 if (retval != ERROR_OK)
272 return retval;
273 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
274 if (retval != ERROR_OK)
275 return retval;
276
277 /* erase option bytes */
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
282 if (retval != ERROR_OK)
283 return retval;
284
285 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
286 if (retval != ERROR_OK)
287 return retval;
288
289 /* clear read protection option byte
290 * this will also force a device unlock if set */
291 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
292
293 return ERROR_OK;
294 }
295
296 static int stm32x_write_options(struct flash_bank *bank)
297 {
298 struct stm32x_flash_bank *stm32x_info = NULL;
299 struct target *target = bank->target;
300
301 stm32x_info = bank->driver_priv;
302
303 /* unlock flash registers */
304 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
305 if (retval != ERROR_OK)
306 return retval;
307 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
308 if (retval != ERROR_OK)
309 return retval;
310
311 /* unlock option flash registers */
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
313 if (retval != ERROR_OK)
314 return retval;
315 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* program option bytes */
320 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
321 if (retval != ERROR_OK)
322 return retval;
323
324 uint8_t opt_bytes[16];
325
326 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
327 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
328 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
331 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
332 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
334
335 /* Block write is preferred in favour of operation with ancient ST-Link
336 * firmwares without 16-bit memory access. See
337 * 480: flash: stm32f1x: write option bytes using the loader
338 * https://review.openocd.org/c/openocd/+/480
339 */
340 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
341 if (retval != ERROR_OK)
342 return retval;
343
344 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
345 if (retval != ERROR_OK)
346 return retval;
347
348 return ERROR_OK;
349 }
350
351 static int stm32x_protect_check(struct flash_bank *bank)
352 {
353 struct target *target = bank->target;
354 uint32_t protection;
355
356 int retval = stm32x_check_operation_supported(bank);
357 if (retval != ERROR_OK)
358 return retval;
359
360 /* medium density - each bit refers to a 4 sector protection block
361 * high density - each bit refers to a 2 sector protection block
362 * bit 31 refers to all remaining sectors in a bank */
363 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
364 if (retval != ERROR_OK)
365 return retval;
366
367 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
368 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
369
370 return ERROR_OK;
371 }
372
373 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
374 unsigned int last)
375 {
376 struct target *target = bank->target;
377
378 if (bank->target->state != TARGET_HALTED) {
379 LOG_ERROR("Target not halted");
380 return ERROR_TARGET_NOT_HALTED;
381 }
382
383 if ((first == 0) && (last == (bank->num_sectors - 1)))
384 return stm32x_mass_erase(bank);
385
386 /* unlock flash registers */
387 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
388 if (retval != ERROR_OK)
389 return retval;
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
391 if (retval != ERROR_OK)
392 return retval;
393
394 for (unsigned int i = first; i <= last; i++) {
395 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
396 if (retval != ERROR_OK)
397 return retval;
398 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
399 bank->base + bank->sectors[i].offset);
400 if (retval != ERROR_OK)
401 return retval;
402 retval = target_write_u32(target,
403 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
404 if (retval != ERROR_OK)
405 return retval;
406
407 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
408 if (retval != ERROR_OK)
409 return retval;
410 }
411
412 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
413 if (retval != ERROR_OK)
414 return retval;
415
416 return ERROR_OK;
417 }
418
419 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
420 unsigned int last)
421 {
422 struct target *target = bank->target;
423 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
424
425 if (target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 int retval = stm32x_check_operation_supported(bank);
431 if (retval != ERROR_OK)
432 return retval;
433
434 retval = stm32x_erase_options(bank);
435 if (retval != ERROR_OK) {
436 LOG_ERROR("stm32x failed to erase options");
437 return retval;
438 }
439
440 for (unsigned int i = first; i <= last; i++) {
441 if (set)
442 stm32x_info->option_bytes.protection &= ~(1 << i);
443 else
444 stm32x_info->option_bytes.protection |= (1 << i);
445 }
446
447 return stm32x_write_options(bank);
448 }
449
450 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
451 uint32_t address, uint32_t hwords_count)
452 {
453 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
454 struct target *target = bank->target;
455 uint32_t buffer_size;
456 struct working_area *write_algorithm;
457 struct working_area *source;
458 struct armv7m_algorithm armv7m_info;
459 int retval;
460
461 static const uint8_t stm32x_flash_write_code[] = {
462 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
463 };
464
465 /* flash write code */
466 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
467 &write_algorithm) != ERROR_OK) {
468 LOG_WARNING("no working area available, can't do block memory writes");
469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
470 }
471
472 retval = target_write_buffer(target, write_algorithm->address,
473 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
474 if (retval != ERROR_OK) {
475 target_free_working_area(target, write_algorithm);
476 return retval;
477 }
478
479 /* memory buffer */
480 buffer_size = target_get_working_area_avail(target);
481 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
482 /* Normally we allocate all available working area.
483 * MIN shrinks buffer_size if the size of the written block is smaller.
484 * MAX prevents using async algo if the available working area is smaller
485 * than 256, the following allocation fails with
486 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
487 */
488
489 retval = target_alloc_working_area(target, buffer_size, &source);
490 /* Allocated size is always 32-bit word aligned */
491 if (retval != ERROR_OK) {
492 target_free_working_area(target, write_algorithm);
493 LOG_WARNING("no large enough working area available, can't do block memory writes");
494 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
495 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
496 */
497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
498 }
499
500 struct reg_param reg_params[5];
501
502 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
503 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
504 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
505 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
506 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
507
508 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
509 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
510 buf_set_u32(reg_params[2].value, 0, 32, source->address);
511 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
512 buf_set_u32(reg_params[4].value, 0, 32, address);
513
514 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
515 armv7m_info.core_mode = ARM_MODE_THREAD;
516
517 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
518 0, NULL,
519 ARRAY_SIZE(reg_params), reg_params,
520 source->address, source->size,
521 write_algorithm->address, 0,
522 &armv7m_info);
523
524 if (retval == ERROR_FLASH_OPERATION_FAILED) {
525 LOG_ERROR("flash write failed at address 0x%"PRIx32,
526 buf_get_u32(reg_params[4].value, 0, 32));
527
528 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
529 LOG_ERROR("flash memory not erased before writing");
530 /* Clear but report errors */
531 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
532 }
533
534 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
535 LOG_ERROR("flash memory write protected");
536 /* Clear but report errors */
537 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
538 }
539 }
540
541 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
542 destroy_reg_param(&reg_params[i]);
543
544 target_free_working_area(target, source);
545 target_free_working_area(target, write_algorithm);
546
547 return retval;
548 }
549
550 /** Writes a block to flash either using target algorithm
551 * or use fallback, host controlled halfword-by-halfword access.
552 * Flash controller must be unlocked before this call.
553 */
554 static int stm32x_write_block(struct flash_bank *bank,
555 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
556 {
557 struct target *target = bank->target;
558
559 /* The flash write must be aligned to a halfword boundary.
560 * The flash infrastructure ensures it, do just a security check
561 */
562 assert(address % 2 == 0);
563
564 /* try using a block write - on ARM architecture or... */
565 int retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
566
567 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
568 /* if block write failed (no sufficient working area),
569 * we use normal (slow) single halfword accesses */
570 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
571
572 while (hwords_count > 0) {
573 retval = target_write_memory(target, address, 2, 1, buffer);
574 if (retval != ERROR_OK)
575 return retval;
576
577 retval = stm32x_wait_status_busy(bank, 5);
578 if (retval != ERROR_OK)
579 return retval;
580
581 hwords_count--;
582 buffer += 2;
583 address += 2;
584 }
585 }
586 return retval;
587 }
588
589 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
590 uint32_t offset, uint32_t count)
591 {
592 struct target *target = bank->target;
593
594 if (bank->target->state != TARGET_HALTED) {
595 LOG_ERROR("Target not halted");
596 return ERROR_TARGET_NOT_HALTED;
597 }
598
599 /* The flash write must be aligned to a halfword boundary.
600 * The flash infrastructure ensures it, do just a security check
601 */
602 assert(offset % 2 == 0);
603 assert(count % 2 == 0);
604
605 int retval, retval2;
606
607 /* unlock flash registers */
608 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
609 if (retval != ERROR_OK)
610 return retval;
611 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
612 if (retval != ERROR_OK)
613 goto reset_pg_and_lock;
614
615 /* enable flash programming */
616 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
617 if (retval != ERROR_OK)
618 goto reset_pg_and_lock;
619
620 /* write to flash */
621 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
622
623 reset_pg_and_lock:
624 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
625 if (retval == ERROR_OK)
626 retval = retval2;
627
628 return retval;
629 }
630
631 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
632 {
633 struct target *target = bank->target;
634 uint32_t device_id_register = 0;
635
636 if (!target_was_examined(target)) {
637 LOG_ERROR("Target not examined yet");
638 return ERROR_TARGET_NOT_EXAMINED;
639 }
640
641 switch (cortex_m_get_partno_safe(target)) {
642 case CORTEX_M0_PARTNO: /* STM32F0x devices */
643 device_id_register = 0x40015800;
644 break;
645 case CORTEX_M3_PARTNO: /* STM32F1x devices */
646 device_id_register = 0xE0042000;
647 break;
648 case CORTEX_M4_PARTNO: /* STM32F3x devices */
649 device_id_register = 0xE0042000;
650 break;
651 case CORTEX_M23_PARTNO: /* GD32E23x devices */
652 device_id_register = 0x40015800;
653 break;
654 default:
655 LOG_ERROR("Cannot identify target as a stm32x");
656 return ERROR_FAIL;
657 }
658
659 /* read stm32 device id register */
660 int retval = target_read_u32(target, device_id_register, device_id);
661 if (retval != ERROR_OK)
662 return retval;
663
664 return retval;
665 }
666
667 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
668 {
669 struct target *target = bank->target;
670 uint32_t flash_size_reg;
671
672 if (!target_was_examined(target)) {
673 LOG_ERROR("Target not examined yet");
674 return ERROR_TARGET_NOT_EXAMINED;
675 }
676
677 switch (cortex_m_get_partno_safe(target)) {
678 case CORTEX_M0_PARTNO: /* STM32F0x devices */
679 flash_size_reg = 0x1FFFF7CC;
680 break;
681 case CORTEX_M3_PARTNO: /* STM32F1x devices */
682 flash_size_reg = 0x1FFFF7E0;
683 break;
684 case CORTEX_M4_PARTNO: /* STM32F3x devices */
685 flash_size_reg = 0x1FFFF7CC;
686 break;
687 case CORTEX_M23_PARTNO: /* GD32E23x devices */
688 flash_size_reg = 0x1FFFF7E0;
689 break;
690 default:
691 LOG_ERROR("Cannot identify target as a stm32x");
692 return ERROR_FAIL;
693 }
694
695 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
696 if (retval != ERROR_OK)
697 return retval;
698
699 return retval;
700 }
701
702 static int stm32x_probe(struct flash_bank *bank)
703 {
704 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
705 uint16_t flash_size_in_kb;
706 uint16_t max_flash_size_in_kb;
707 uint32_t dbgmcu_idcode;
708 int page_size;
709 uint32_t base_address = 0x08000000;
710
711 stm32x_info->probed = false;
712 stm32x_info->register_base = FLASH_REG_BASE_B0;
713 stm32x_info->user_data_offset = 10;
714 stm32x_info->option_offset = 0;
715
716 /* default factory read protection level 0 */
717 stm32x_info->default_rdp = 0xA5;
718
719 /* read stm32 device id register */
720 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
721 if (retval != ERROR_OK)
722 return retval;
723
724 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
725
726 uint16_t device_id = dbgmcu_idcode & 0xfff;
727 uint16_t rev_id = dbgmcu_idcode >> 16;
728
729 /* set page size, protection granularity and max flash size depending on family */
730 switch (device_id) {
731 case 0x440: /* stm32f05x */
732 page_size = 1024;
733 stm32x_info->ppage_size = 4;
734 max_flash_size_in_kb = 64;
735 stm32x_info->user_data_offset = 16;
736 stm32x_info->option_offset = 6;
737 stm32x_info->default_rdp = 0xAA;
738 stm32x_info->can_load_options = true;
739 break;
740 case 0x444: /* stm32f03x */
741 case 0x445: /* stm32f04x */
742 page_size = 1024;
743 stm32x_info->ppage_size = 4;
744 max_flash_size_in_kb = 32;
745 stm32x_info->user_data_offset = 16;
746 stm32x_info->option_offset = 6;
747 stm32x_info->default_rdp = 0xAA;
748 stm32x_info->can_load_options = true;
749 break;
750 case 0x448: /* stm32f07x */
751 page_size = 2048;
752 stm32x_info->ppage_size = 4;
753 max_flash_size_in_kb = 128;
754 stm32x_info->user_data_offset = 16;
755 stm32x_info->option_offset = 6;
756 stm32x_info->default_rdp = 0xAA;
757 stm32x_info->can_load_options = true;
758 break;
759 case 0x442: /* stm32f09x */
760 page_size = 2048;
761 stm32x_info->ppage_size = 4;
762 max_flash_size_in_kb = 256;
763 stm32x_info->user_data_offset = 16;
764 stm32x_info->option_offset = 6;
765 stm32x_info->default_rdp = 0xAA;
766 stm32x_info->can_load_options = true;
767 break;
768 case 0x410: /* stm32f1x medium-density */
769 page_size = 1024;
770 stm32x_info->ppage_size = 4;
771 max_flash_size_in_kb = 128;
772 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
773 share DEV_ID with STM32F101/2/3 medium-density line,
774 however they use a REV_ID different from any STM32 device.
775 The main difference is another offset of user option bits
776 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
777 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
778 This caused problems e.g. during flash block programming
779 because of unexpected active hardware watchog. */
780 switch (rev_id) {
781 case 0x1303: /* gd32f1x0 */
782 stm32x_info->user_data_offset = 16;
783 stm32x_info->option_offset = 6;
784 max_flash_size_in_kb = 64;
785 break;
786 case 0x1704: /* gd32f3x0 */
787 stm32x_info->user_data_offset = 16;
788 stm32x_info->option_offset = 6;
789 break;
790 case 0x1909: /* gd32e23x */
791 stm32x_info->user_data_offset = 16;
792 stm32x_info->option_offset = 6;
793 max_flash_size_in_kb = 64;
794 break;
795 }
796 break;
797 case 0x412: /* stm32f1x low-density */
798 page_size = 1024;
799 stm32x_info->ppage_size = 4;
800 max_flash_size_in_kb = 32;
801 break;
802 case 0x414: /* stm32f1x high-density */
803 page_size = 2048;
804 stm32x_info->ppage_size = 2;
805 max_flash_size_in_kb = 512;
806 break;
807 case 0x418: /* stm32f1x connectivity */
808 page_size = 2048;
809 stm32x_info->ppage_size = 2;
810 max_flash_size_in_kb = 256;
811 break;
812 case 0x430: /* stm32f1 XL-density (dual flash banks) */
813 page_size = 2048;
814 stm32x_info->ppage_size = 2;
815 max_flash_size_in_kb = 1024;
816 stm32x_info->has_dual_banks = true;
817 break;
818 case 0x420: /* stm32f100xx low- and medium-density value line */
819 page_size = 1024;
820 stm32x_info->ppage_size = 4;
821 max_flash_size_in_kb = 128;
822 break;
823 case 0x428: /* stm32f100xx high-density value line */
824 page_size = 2048;
825 stm32x_info->ppage_size = 4;
826 max_flash_size_in_kb = 512;
827 break;
828 case 0x422: /* stm32f302/3xb/c */
829 page_size = 2048;
830 stm32x_info->ppage_size = 2;
831 max_flash_size_in_kb = 256;
832 stm32x_info->user_data_offset = 16;
833 stm32x_info->option_offset = 6;
834 stm32x_info->default_rdp = 0xAA;
835 stm32x_info->can_load_options = true;
836 break;
837 case 0x446: /* stm32f303xD/E */
838 page_size = 2048;
839 stm32x_info->ppage_size = 2;
840 max_flash_size_in_kb = 512;
841 stm32x_info->user_data_offset = 16;
842 stm32x_info->option_offset = 6;
843 stm32x_info->default_rdp = 0xAA;
844 stm32x_info->can_load_options = true;
845 break;
846 case 0x432: /* stm32f37x */
847 page_size = 2048;
848 stm32x_info->ppage_size = 2;
849 max_flash_size_in_kb = 256;
850 stm32x_info->user_data_offset = 16;
851 stm32x_info->option_offset = 6;
852 stm32x_info->default_rdp = 0xAA;
853 stm32x_info->can_load_options = true;
854 break;
855 case 0x438: /* stm32f33x */
856 case 0x439: /* stm32f302x6/8 */
857 page_size = 2048;
858 stm32x_info->ppage_size = 2;
859 max_flash_size_in_kb = 64;
860 stm32x_info->user_data_offset = 16;
861 stm32x_info->option_offset = 6;
862 stm32x_info->default_rdp = 0xAA;
863 stm32x_info->can_load_options = true;
864 break;
865 default:
866 LOG_WARNING("Cannot identify target as a STM32 family.");
867 return ERROR_FAIL;
868 }
869
870 /* get flash size from target. */
871 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
872
873 /* failed reading flash size or flash size invalid (early silicon),
874 * default to max target family */
875 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
876 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
877 max_flash_size_in_kb);
878 flash_size_in_kb = max_flash_size_in_kb;
879 }
880
881 if (stm32x_info->has_dual_banks) {
882 /* split reported size into matching bank */
883 if (bank->base != 0x08080000) {
884 /* bank 0 will be fixed 512k */
885 flash_size_in_kb = 512;
886 } else {
887 flash_size_in_kb -= 512;
888 /* bank1 also uses a register offset */
889 stm32x_info->register_base = FLASH_REG_BASE_B1;
890 base_address = 0x08080000;
891 }
892 }
893
894 /* if the user sets the size manually then ignore the probed value
895 * this allows us to work around devices that have a invalid flash size register value */
896 if (stm32x_info->user_bank_size) {
897 LOG_INFO("ignoring flash probed value, using configured bank size");
898 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
899 }
900
901 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
902
903 /* did we assign flash size? */
904 assert(flash_size_in_kb != 0xffff);
905
906 /* calculate numbers of pages */
907 int num_pages = flash_size_in_kb * 1024 / page_size;
908
909 /* check that calculation result makes sense */
910 assert(num_pages > 0);
911
912 free(bank->sectors);
913 bank->sectors = NULL;
914
915 free(bank->prot_blocks);
916 bank->prot_blocks = NULL;
917
918 bank->base = base_address;
919 bank->size = (num_pages * page_size);
920
921 bank->num_sectors = num_pages;
922 bank->sectors = alloc_block_array(0, page_size, num_pages);
923 if (!bank->sectors)
924 return ERROR_FAIL;
925
926 /* calculate number of write protection blocks */
927 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
928 if (num_prot_blocks > 32)
929 num_prot_blocks = 32;
930
931 bank->num_prot_blocks = num_prot_blocks;
932 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
933 if (!bank->prot_blocks)
934 return ERROR_FAIL;
935
936 if (num_prot_blocks == 32)
937 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
938
939 stm32x_info->probed = true;
940
941 return ERROR_OK;
942 }
943
944 static int stm32x_auto_probe(struct flash_bank *bank)
945 {
946 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
947 if (stm32x_info->probed)
948 return ERROR_OK;
949 return stm32x_probe(bank);
950 }
951
952 #if 0
953 COMMAND_HANDLER(stm32x_handle_part_id_command)
954 {
955 return ERROR_OK;
956 }
957 #endif
958
959 static const char *get_stm32f0_revision(uint16_t rev_id)
960 {
961 const char *rev_str = NULL;
962
963 switch (rev_id) {
964 case 0x1000:
965 rev_str = "1.0";
966 break;
967 case 0x2000:
968 rev_str = "2.0";
969 break;
970 }
971 return rev_str;
972 }
973
974 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
975 {
976 uint32_t dbgmcu_idcode;
977
978 /* read stm32 device id register */
979 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
980 if (retval != ERROR_OK)
981 return retval;
982
983 uint16_t device_id = dbgmcu_idcode & 0xfff;
984 uint16_t rev_id = dbgmcu_idcode >> 16;
985 const char *device_str;
986 const char *rev_str = NULL;
987
988 switch (device_id) {
989 case 0x410:
990 device_str = "STM32F10x (Medium Density)";
991
992 switch (rev_id) {
993 case 0x0000:
994 rev_str = "A";
995 break;
996
997 case 0x1303: /* gd32f1x0 */
998 device_str = "GD32F1x0";
999 break;
1000
1001 case 0x1704: /* gd32f3x0 */
1002 device_str = "GD32F3x0";
1003 break;
1004
1005 case 0x1909: /* gd32e23x */
1006 device_str = "GD32E23x";
1007 break;
1008
1009 case 0x2000:
1010 rev_str = "B";
1011 break;
1012
1013 case 0x2001:
1014 rev_str = "Z";
1015 break;
1016
1017 case 0x2003:
1018 rev_str = "Y";
1019 break;
1020 }
1021 break;
1022
1023 case 0x412:
1024 device_str = "STM32F10x (Low Density)";
1025
1026 switch (rev_id) {
1027 case 0x1000:
1028 rev_str = "A";
1029 break;
1030 }
1031 break;
1032
1033 case 0x414:
1034 device_str = "STM32F10x (High Density)";
1035
1036 switch (rev_id) {
1037 case 0x1000:
1038 rev_str = "A";
1039 break;
1040
1041 case 0x1001:
1042 rev_str = "Z";
1043 break;
1044
1045 case 0x1003:
1046 rev_str = "Y";
1047 break;
1048 }
1049 break;
1050
1051 case 0x418:
1052 device_str = "STM32F10x (Connectivity)";
1053
1054 switch (rev_id) {
1055 case 0x1000:
1056 rev_str = "A";
1057 break;
1058
1059 case 0x1001:
1060 rev_str = "Z";
1061 break;
1062 }
1063 break;
1064
1065 case 0x420:
1066 device_str = "STM32F100 (Low/Medium Density)";
1067
1068 switch (rev_id) {
1069 case 0x1000:
1070 rev_str = "A";
1071 break;
1072
1073 case 0x1001:
1074 rev_str = "Z";
1075 break;
1076 }
1077 break;
1078
1079 case 0x422:
1080 device_str = "STM32F302xB/C";
1081
1082 switch (rev_id) {
1083 case 0x1000:
1084 rev_str = "A";
1085 break;
1086
1087 case 0x1001:
1088 rev_str = "Z";
1089 break;
1090
1091 case 0x1003:
1092 rev_str = "Y";
1093 break;
1094
1095 case 0x2000:
1096 rev_str = "B";
1097 break;
1098 }
1099 break;
1100
1101 case 0x428:
1102 device_str = "STM32F100 (High Density)";
1103
1104 switch (rev_id) {
1105 case 0x1000:
1106 rev_str = "A";
1107 break;
1108
1109 case 0x1001:
1110 rev_str = "Z";
1111 break;
1112 }
1113 break;
1114
1115 case 0x430:
1116 device_str = "STM32F10x (XL Density)";
1117
1118 switch (rev_id) {
1119 case 0x1000:
1120 rev_str = "A";
1121 break;
1122 }
1123 break;
1124
1125 case 0x432:
1126 device_str = "STM32F37x";
1127
1128 switch (rev_id) {
1129 case 0x1000:
1130 rev_str = "A";
1131 break;
1132
1133 case 0x2000:
1134 rev_str = "B";
1135 break;
1136 }
1137 break;
1138
1139 case 0x438:
1140 device_str = "STM32F33x";
1141
1142 switch (rev_id) {
1143 case 0x1000:
1144 rev_str = "A";
1145 break;
1146 }
1147 break;
1148
1149 case 0x439:
1150 device_str = "STM32F302x6/8";
1151
1152 switch (rev_id) {
1153 case 0x1000:
1154 rev_str = "A";
1155 break;
1156
1157 case 0x1001:
1158 rev_str = "Z";
1159 break;
1160 }
1161 break;
1162
1163 case 0x444:
1164 device_str = "STM32F03x";
1165 rev_str = get_stm32f0_revision(rev_id);
1166 break;
1167
1168 case 0x440:
1169 device_str = "STM32F05x";
1170 rev_str = get_stm32f0_revision(rev_id);
1171 break;
1172
1173 case 0x445:
1174 device_str = "STM32F04x";
1175 rev_str = get_stm32f0_revision(rev_id);
1176 break;
1177
1178 case 0x446:
1179 device_str = "STM32F303xD/E";
1180 switch (rev_id) {
1181 case 0x1000:
1182 rev_str = "A";
1183 break;
1184 }
1185 break;
1186
1187 case 0x448:
1188 device_str = "STM32F07x";
1189 rev_str = get_stm32f0_revision(rev_id);
1190 break;
1191
1192 case 0x442:
1193 device_str = "STM32F09x";
1194 rev_str = get_stm32f0_revision(rev_id);
1195 break;
1196
1197 default:
1198 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1199 return ERROR_FAIL;
1200 }
1201
1202 if (rev_str)
1203 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1204 else
1205 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1206
1207 return ERROR_OK;
1208 }
1209
1210 COMMAND_HANDLER(stm32x_handle_lock_command)
1211 {
1212 struct target *target = NULL;
1213 struct stm32x_flash_bank *stm32x_info = NULL;
1214
1215 if (CMD_ARGC < 1)
1216 return ERROR_COMMAND_SYNTAX_ERROR;
1217
1218 struct flash_bank *bank;
1219 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1220 if (retval != ERROR_OK)
1221 return retval;
1222
1223 stm32x_info = bank->driver_priv;
1224
1225 target = bank->target;
1226
1227 if (target->state != TARGET_HALTED) {
1228 LOG_ERROR("Target not halted");
1229 return ERROR_TARGET_NOT_HALTED;
1230 }
1231
1232 retval = stm32x_check_operation_supported(bank);
1233 if (retval != ERROR_OK)
1234 return retval;
1235
1236 if (stm32x_erase_options(bank) != ERROR_OK) {
1237 command_print(CMD, "stm32x failed to erase options");
1238 return ERROR_OK;
1239 }
1240
1241 /* set readout protection */
1242 stm32x_info->option_bytes.rdp = 0;
1243
1244 if (stm32x_write_options(bank) != ERROR_OK) {
1245 command_print(CMD, "stm32x failed to lock device");
1246 return ERROR_OK;
1247 }
1248
1249 command_print(CMD, "stm32x locked");
1250
1251 return ERROR_OK;
1252 }
1253
1254 COMMAND_HANDLER(stm32x_handle_unlock_command)
1255 {
1256 struct target *target = NULL;
1257
1258 if (CMD_ARGC < 1)
1259 return ERROR_COMMAND_SYNTAX_ERROR;
1260
1261 struct flash_bank *bank;
1262 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1263 if (retval != ERROR_OK)
1264 return retval;
1265
1266 target = bank->target;
1267
1268 if (target->state != TARGET_HALTED) {
1269 LOG_ERROR("Target not halted");
1270 return ERROR_TARGET_NOT_HALTED;
1271 }
1272
1273 retval = stm32x_check_operation_supported(bank);
1274 if (retval != ERROR_OK)
1275 return retval;
1276
1277 if (stm32x_erase_options(bank) != ERROR_OK) {
1278 command_print(CMD, "stm32x failed to erase options");
1279 return ERROR_OK;
1280 }
1281
1282 if (stm32x_write_options(bank) != ERROR_OK) {
1283 command_print(CMD, "stm32x failed to unlock device");
1284 return ERROR_OK;
1285 }
1286
1287 command_print(CMD, "stm32x unlocked.\n"
1288 "INFO: a reset or power cycle is required "
1289 "for the new settings to take effect.");
1290
1291 return ERROR_OK;
1292 }
1293
1294 COMMAND_HANDLER(stm32x_handle_options_read_command)
1295 {
1296 uint32_t optionbyte, protection;
1297 struct target *target = NULL;
1298 struct stm32x_flash_bank *stm32x_info = NULL;
1299
1300 if (CMD_ARGC < 1)
1301 return ERROR_COMMAND_SYNTAX_ERROR;
1302
1303 struct flash_bank *bank;
1304 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1305 if (retval != ERROR_OK)
1306 return retval;
1307
1308 stm32x_info = bank->driver_priv;
1309
1310 target = bank->target;
1311
1312 if (target->state != TARGET_HALTED) {
1313 LOG_ERROR("Target not halted");
1314 return ERROR_TARGET_NOT_HALTED;
1315 }
1316
1317 retval = stm32x_check_operation_supported(bank);
1318 if (retval != ERROR_OK)
1319 return retval;
1320
1321 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1322 if (retval != ERROR_OK)
1323 return retval;
1324
1325 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1326
1327 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1328 if (retval != ERROR_OK)
1329 return retval;
1330
1331 if (optionbyte & (1 << OPT_ERROR))
1332 command_print(CMD, "option byte complement error");
1333
1334 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1335 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1336
1337 command_print(CMD, "read protection: %s",
1338 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1339
1340 /* user option bytes are offset depending on variant */
1341 optionbyte >>= stm32x_info->option_offset;
1342
1343 command_print(CMD, "watchdog: %sware",
1344 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1345
1346 command_print(CMD, "stop mode: %sreset generated upon entry",
1347 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1348
1349 command_print(CMD, "standby mode: %sreset generated upon entry",
1350 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1351
1352 if (stm32x_info->has_dual_banks)
1353 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1354
1355 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1356
1357 return ERROR_OK;
1358 }
1359
1360 COMMAND_HANDLER(stm32x_handle_options_write_command)
1361 {
1362 struct target *target = NULL;
1363 struct stm32x_flash_bank *stm32x_info = NULL;
1364 uint8_t optionbyte;
1365 uint16_t useropt;
1366
1367 if (CMD_ARGC < 2)
1368 return ERROR_COMMAND_SYNTAX_ERROR;
1369
1370 struct flash_bank *bank;
1371 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1372 if (retval != ERROR_OK)
1373 return retval;
1374
1375 stm32x_info = bank->driver_priv;
1376
1377 target = bank->target;
1378
1379 if (target->state != TARGET_HALTED) {
1380 LOG_ERROR("Target not halted");
1381 return ERROR_TARGET_NOT_HALTED;
1382 }
1383
1384 retval = stm32x_check_operation_supported(bank);
1385 if (retval != ERROR_OK)
1386 return retval;
1387
1388 retval = stm32x_read_options(bank);
1389 if (retval != ERROR_OK)
1390 return retval;
1391
1392 /* start with current options */
1393 optionbyte = stm32x_info->option_bytes.user;
1394 useropt = stm32x_info->option_bytes.data;
1395
1396 /* skip over flash bank */
1397 CMD_ARGC--;
1398 CMD_ARGV++;
1399
1400 while (CMD_ARGC) {
1401 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1402 optionbyte |= (1 << 0);
1403 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1404 optionbyte &= ~(1 << 0);
1405 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1406 optionbyte |= (1 << 1);
1407 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1408 optionbyte &= ~(1 << 1);
1409 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1410 optionbyte |= (1 << 2);
1411 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1412 optionbyte &= ~(1 << 2);
1413 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1414 if (CMD_ARGC < 2)
1415 return ERROR_COMMAND_SYNTAX_ERROR;
1416 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1417 CMD_ARGC--;
1418 CMD_ARGV++;
1419 } else if (stm32x_info->has_dual_banks) {
1420 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1421 optionbyte |= (1 << 3);
1422 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1423 optionbyte &= ~(1 << 3);
1424 else
1425 return ERROR_COMMAND_SYNTAX_ERROR;
1426 } else
1427 return ERROR_COMMAND_SYNTAX_ERROR;
1428 CMD_ARGC--;
1429 CMD_ARGV++;
1430 }
1431
1432 if (stm32x_erase_options(bank) != ERROR_OK) {
1433 command_print(CMD, "stm32x failed to erase options");
1434 return ERROR_OK;
1435 }
1436
1437 stm32x_info->option_bytes.user = optionbyte;
1438 stm32x_info->option_bytes.data = useropt;
1439
1440 if (stm32x_write_options(bank) != ERROR_OK) {
1441 command_print(CMD, "stm32x failed to write options");
1442 return ERROR_OK;
1443 }
1444
1445 command_print(CMD, "stm32x write options complete.\n"
1446 "INFO: %spower cycle is required "
1447 "for the new settings to take effect.",
1448 stm32x_info->can_load_options
1449 ? "'stm32f1x options_load' command or " : "");
1450
1451 return ERROR_OK;
1452 }
1453
1454 COMMAND_HANDLER(stm32x_handle_options_load_command)
1455 {
1456 if (CMD_ARGC < 1)
1457 return ERROR_COMMAND_SYNTAX_ERROR;
1458
1459 struct flash_bank *bank;
1460 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1461 if (retval != ERROR_OK)
1462 return retval;
1463
1464 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1465
1466 if (!stm32x_info->can_load_options) {
1467 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1468 "required instead.");
1469 return ERROR_FAIL;
1470 }
1471
1472 struct target *target = bank->target;
1473
1474 if (target->state != TARGET_HALTED) {
1475 LOG_ERROR("Target not halted");
1476 return ERROR_TARGET_NOT_HALTED;
1477 }
1478
1479 retval = stm32x_check_operation_supported(bank);
1480 if (retval != ERROR_OK)
1481 return retval;
1482
1483 /* unlock option flash registers */
1484 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1485 if (retval != ERROR_OK)
1486 return retval;
1487 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1488 if (retval != ERROR_OK)
1489 return retval;
1490
1491 /* force re-load of option bytes - generates software reset */
1492 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1493 if (retval != ERROR_OK)
1494 return retval;
1495
1496 return ERROR_OK;
1497 }
1498
1499 static int stm32x_mass_erase(struct flash_bank *bank)
1500 {
1501 struct target *target = bank->target;
1502
1503 if (target->state != TARGET_HALTED) {
1504 LOG_ERROR("Target not halted");
1505 return ERROR_TARGET_NOT_HALTED;
1506 }
1507
1508 /* unlock option flash registers */
1509 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1510 if (retval != ERROR_OK)
1511 return retval;
1512 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1513 if (retval != ERROR_OK)
1514 return retval;
1515
1516 /* mass erase flash memory */
1517 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1518 if (retval != ERROR_OK)
1519 return retval;
1520 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1521 FLASH_MER | FLASH_STRT);
1522 if (retval != ERROR_OK)
1523 return retval;
1524
1525 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1526 if (retval != ERROR_OK)
1527 return retval;
1528
1529 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1530 if (retval != ERROR_OK)
1531 return retval;
1532
1533 return ERROR_OK;
1534 }
1535
1536 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1537 {
1538 if (CMD_ARGC < 1)
1539 return ERROR_COMMAND_SYNTAX_ERROR;
1540
1541 struct flash_bank *bank;
1542 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1543 if (retval != ERROR_OK)
1544 return retval;
1545
1546 retval = stm32x_mass_erase(bank);
1547 if (retval == ERROR_OK)
1548 command_print(CMD, "stm32x mass erase complete");
1549 else
1550 command_print(CMD, "stm32x mass erase failed");
1551
1552 return retval;
1553 }
1554
1555 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1556 {
1557 .name = "lock",
1558 .handler = stm32x_handle_lock_command,
1559 .mode = COMMAND_EXEC,
1560 .usage = "bank_id",
1561 .help = "Lock entire flash device.",
1562 },
1563 {
1564 .name = "unlock",
1565 .handler = stm32x_handle_unlock_command,
1566 .mode = COMMAND_EXEC,
1567 .usage = "bank_id",
1568 .help = "Unlock entire protected flash device.",
1569 },
1570 {
1571 .name = "mass_erase",
1572 .handler = stm32x_handle_mass_erase_command,
1573 .mode = COMMAND_EXEC,
1574 .usage = "bank_id",
1575 .help = "Erase entire flash device.",
1576 },
1577 {
1578 .name = "options_read",
1579 .handler = stm32x_handle_options_read_command,
1580 .mode = COMMAND_EXEC,
1581 .usage = "bank_id",
1582 .help = "Read and display device option bytes.",
1583 },
1584 {
1585 .name = "options_write",
1586 .handler = stm32x_handle_options_write_command,
1587 .mode = COMMAND_EXEC,
1588 .usage = "bank_id ('SWWDG'|'HWWDG') "
1589 "('RSTSTNDBY'|'NORSTSTNDBY') "
1590 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1591 .help = "Replace bits in device option bytes.",
1592 },
1593 {
1594 .name = "options_load",
1595 .handler = stm32x_handle_options_load_command,
1596 .mode = COMMAND_EXEC,
1597 .usage = "bank_id",
1598 .help = "Force re-load of device option bytes.",
1599 },
1600 COMMAND_REGISTRATION_DONE
1601 };
1602
1603 static const struct command_registration stm32f1x_command_handlers[] = {
1604 {
1605 .name = "stm32f1x",
1606 .mode = COMMAND_ANY,
1607 .help = "stm32f1x flash command group",
1608 .usage = "",
1609 .chain = stm32f1x_exec_command_handlers,
1610 },
1611 COMMAND_REGISTRATION_DONE
1612 };
1613
1614 const struct flash_driver stm32f1x_flash = {
1615 .name = "stm32f1x",
1616 .commands = stm32f1x_command_handlers,
1617 .flash_bank_command = stm32x_flash_bank_command,
1618 .erase = stm32x_erase,
1619 .protect = stm32x_protect,
1620 .write = stm32x_write,
1621 .read = default_flash_read,
1622 .probe = stm32x_probe,
1623 .auto_probe = stm32x_auto_probe,
1624 .erase_check = default_flash_blank_check,
1625 .protect_check = stm32x_protect_check,
1626 .info = get_stm32x_info,
1627 .free_driver_priv = default_flash_free_driver_priv,
1628 };
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