1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
33 /* STM32L4xxx series for reference.
35 * RM0351 (STM32L4x5/STM32L4x6)
36 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
38 * RM0394 (STM32L43x/44x/45x/46x)
39 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
41 * RM0432 (STM32L4R/4Sxx)
42 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
44 * STM32L476RG Datasheet (for erase timing)
45 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
47 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
48 * an option byte is available to map all sectors to the first bank.
49 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
52 * RM0394 devices have a single bank only.
54 * RM0432 devices have single and dual bank operating modes.
55 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
56 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
57 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
59 * Bank mode is controlled by two different bits in option bytes register.
61 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
62 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
64 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
65 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
69 /* STM32WBxxx series for reference.
72 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
75 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
78 /* STM32WLxxx series for reference.
81 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
85 * STM32G0xxx series for reference.
88 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
91 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
95 * STM32G4xxx series for reference.
97 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
98 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
100 * Cat. 2 devices have single bank only, page size is 2kByte.
102 * Cat. 3 devices have single and dual bank operating modes,
103 * Page size is 2kByte (dual mode) or 4kByte (single mode).
105 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
106 * Both banks are treated as a single OpenOCD bank.
108 * Cat. 4 devices have single bank only, page size is 2kByte.
111 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
113 #define FLASH_ERASE_TIMEOUT 250
120 struct stm32l4_part_info
{
122 const char *device_str
;
123 const struct stm32l4_rev
*revs
;
124 const size_t num_revs
;
125 const uint16_t max_flash_size_kb
;
126 const bool has_dual_bank
;
127 const uint32_t flash_regs_base
;
128 const uint32_t fsize_addr
;
131 struct stm32l4_flash_bank
{
134 unsigned int bank1_sectors
;
137 uint32_t user_bank_size
;
138 uint32_t wrpxxr_mask
;
139 const struct stm32l4_part_info
*part_info
;
142 /* human readable list of families this drivers supports */
143 static const char *device_families
= "STM32L4/L4+/WB/WL/G4/G0";
145 static const struct stm32l4_rev stm32_415_revs
[] = {
146 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
149 static const struct stm32l4_rev stm32_435_revs
[] = {
150 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
153 static const struct stm32l4_rev stm32_460_revs
[] = {
154 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
157 static const struct stm32l4_rev stm32_461_revs
[] = {
158 { 0x1000, "A" }, { 0x2000, "B" },
161 static const struct stm32l4_rev stm32_462_revs
[] = {
162 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
165 static const struct stm32l4_rev stm32_464_revs
[] = {
166 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
169 static const struct stm32l4_rev stm32_466_revs
[] = {
170 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
173 static const struct stm32l4_rev stm32_468_revs
[] = {
174 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
177 static const struct stm32l4_rev stm32_469_revs
[] = {
178 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
181 static const struct stm32l4_rev stm32_470_revs
[] = {
182 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
185 static const struct stm32l4_rev stm32_471_revs
[] = {
189 static const struct stm32l4_rev stm32_479_revs
[] = {
193 static const struct stm32l4_rev stm32_495_revs
[] = {
197 static const struct stm32l4_rev stm32_496_revs
[] = {
201 static const struct stm32l4_rev stm32_497_revs
[] = {
205 static const struct stm32l4_part_info stm32l4_parts
[] = {
208 .revs
= stm32_415_revs
,
209 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
210 .device_str
= "STM32L47/L48xx",
211 .max_flash_size_kb
= 1024,
212 .has_dual_bank
= true,
213 .flash_regs_base
= 0x40022000,
214 .fsize_addr
= 0x1FFF75E0,
218 .revs
= stm32_435_revs
,
219 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
220 .device_str
= "STM32L43/L44xx",
221 .max_flash_size_kb
= 256,
222 .has_dual_bank
= false,
223 .flash_regs_base
= 0x40022000,
224 .fsize_addr
= 0x1FFF75E0,
228 .revs
= stm32_460_revs
,
229 .num_revs
= ARRAY_SIZE(stm32_460_revs
),
230 .device_str
= "STM32G07/G08xx",
231 .max_flash_size_kb
= 128,
232 .has_dual_bank
= false,
233 .flash_regs_base
= 0x40022000,
234 .fsize_addr
= 0x1FFF75E0,
238 .revs
= stm32_461_revs
,
239 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
240 .device_str
= "STM32L49/L4Axx",
241 .max_flash_size_kb
= 1024,
242 .has_dual_bank
= true,
243 .flash_regs_base
= 0x40022000,
244 .fsize_addr
= 0x1FFF75E0,
248 .revs
= stm32_462_revs
,
249 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
250 .device_str
= "STM32L45/L46xx",
251 .max_flash_size_kb
= 512,
252 .has_dual_bank
= false,
253 .flash_regs_base
= 0x40022000,
254 .fsize_addr
= 0x1FFF75E0,
258 .revs
= stm32_464_revs
,
259 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
260 .device_str
= "STM32L41/L42xx",
261 .max_flash_size_kb
= 128,
262 .has_dual_bank
= false,
263 .flash_regs_base
= 0x40022000,
264 .fsize_addr
= 0x1FFF75E0,
268 .revs
= stm32_466_revs
,
269 .num_revs
= ARRAY_SIZE(stm32_466_revs
),
270 .device_str
= "STM32G03/G04xx",
271 .max_flash_size_kb
= 64,
272 .has_dual_bank
= false,
273 .flash_regs_base
= 0x40022000,
274 .fsize_addr
= 0x1FFF75E0,
278 .revs
= stm32_468_revs
,
279 .num_revs
= ARRAY_SIZE(stm32_468_revs
),
280 .device_str
= "STM32G43/G44xx",
281 .max_flash_size_kb
= 128,
282 .has_dual_bank
= false,
283 .flash_regs_base
= 0x40022000,
284 .fsize_addr
= 0x1FFF75E0,
288 .revs
= stm32_469_revs
,
289 .num_revs
= ARRAY_SIZE(stm32_469_revs
),
290 .device_str
= "STM32G47/G48xx",
291 .max_flash_size_kb
= 512,
292 .has_dual_bank
= true,
293 .flash_regs_base
= 0x40022000,
294 .fsize_addr
= 0x1FFF75E0,
298 .revs
= stm32_470_revs
,
299 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
300 .device_str
= "STM32L4R/L4Sxx",
301 .max_flash_size_kb
= 2048,
302 .has_dual_bank
= true,
303 .flash_regs_base
= 0x40022000,
304 .fsize_addr
= 0x1FFF75E0,
308 .revs
= stm32_471_revs
,
309 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
310 .device_str
= "STM32L4P5/L4Q5x",
311 .max_flash_size_kb
= 1024,
312 .has_dual_bank
= true,
313 .flash_regs_base
= 0x40022000,
314 .fsize_addr
= 0x1FFF75E0,
318 .revs
= stm32_479_revs
,
319 .num_revs
= ARRAY_SIZE(stm32_479_revs
),
320 .device_str
= "STM32G49/G4Axx",
321 .max_flash_size_kb
= 512,
322 .has_dual_bank
= false,
323 .flash_regs_base
= 0x40022000,
324 .fsize_addr
= 0x1FFF75E0,
328 .revs
= stm32_495_revs
,
329 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
330 .device_str
= "STM32WB5x",
331 .max_flash_size_kb
= 1024,
332 .has_dual_bank
= false,
333 .flash_regs_base
= 0x58004000,
334 .fsize_addr
= 0x1FFF75E0,
338 .revs
= stm32_496_revs
,
339 .num_revs
= ARRAY_SIZE(stm32_496_revs
),
340 .device_str
= "STM32WB3x",
341 .max_flash_size_kb
= 512,
342 .has_dual_bank
= false,
343 .flash_regs_base
= 0x58004000,
344 .fsize_addr
= 0x1FFF75E0,
348 .revs
= stm32_497_revs
,
349 .num_revs
= ARRAY_SIZE(stm32_497_revs
),
350 .device_str
= "STM32WLEx",
351 .max_flash_size_kb
= 256,
352 .has_dual_bank
= false,
353 .flash_regs_base
= 0x58004000,
354 .fsize_addr
= 0x1FFF75E0,
358 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
359 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
361 struct stm32l4_flash_bank
*stm32l4_info
;
364 return ERROR_COMMAND_SYNTAX_ERROR
;
366 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
368 return ERROR_FAIL
; /* Checkme: What better error to use?*/
369 bank
->driver_priv
= stm32l4_info
;
371 /* The flash write must be aligned to a double word (8-bytes) boundary.
372 * Ask the flash infrastructure to ensure required alignment */
373 bank
->write_start_alignment
= bank
->write_end_alignment
= 8;
375 stm32l4_info
->probed
= false;
376 stm32l4_info
->user_bank_size
= bank
->size
;
381 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
383 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
384 return stm32l4_info
->part_info
->flash_regs_base
+ reg_offset
;
387 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
389 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
392 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
394 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
397 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
400 int retval
= ERROR_OK
;
402 /* wait for busy to clear */
404 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_SR
, &status
);
405 if (retval
!= ERROR_OK
)
407 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
408 if ((status
& FLASH_BSY
) == 0)
410 if (timeout
-- <= 0) {
411 LOG_ERROR("timed out waiting for flash");
418 if (status
& FLASH_WRPERR
) {
419 LOG_ERROR("stm32x device protected");
423 /* Clear but report errors */
424 if (status
& FLASH_ERROR
) {
425 if (retval
== ERROR_OK
)
427 /* If this operation fails, we ignore it and report the original
430 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, status
& FLASH_ERROR
);
436 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
440 /* first check if not already unlocked
441 * otherwise writing on STM32_FLASH_KEYR will fail
443 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
444 if (retval
!= ERROR_OK
)
447 if ((ctrl
& FLASH_LOCK
) == 0)
450 /* unlock flash registers */
451 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY1
);
452 if (retval
!= ERROR_OK
)
455 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY2
);
456 if (retval
!= ERROR_OK
)
459 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
460 if (retval
!= ERROR_OK
)
463 if (ctrl
& FLASH_LOCK
) {
464 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
465 return ERROR_TARGET_FAILURE
;
471 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
475 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
476 if (retval
!= ERROR_OK
)
479 if ((ctrl
& FLASH_OPTLOCK
) == 0)
482 /* unlock option registers */
483 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
484 if (retval
!= ERROR_OK
)
487 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
488 if (retval
!= ERROR_OK
)
491 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
492 if (retval
!= ERROR_OK
)
495 if (ctrl
& FLASH_OPTLOCK
) {
496 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
497 return ERROR_TARGET_FAILURE
;
503 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
504 uint32_t value
, uint32_t mask
)
509 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
510 if (retval
!= ERROR_OK
)
513 retval
= stm32l4_unlock_reg(bank
);
514 if (retval
!= ERROR_OK
)
517 retval
= stm32l4_unlock_option_reg(bank
);
518 if (retval
!= ERROR_OK
)
521 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
523 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
524 if (retval
!= ERROR_OK
)
527 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OPTSTRT
);
528 if (retval
!= ERROR_OK
)
531 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
534 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
| FLASH_OPTLOCK
);
536 if (retval
!= ERROR_OK
)
542 static int stm32l4_protect_check(struct flash_bank
*bank
)
544 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
546 uint32_t wrp1ar
, wrp1br
, wrp2ar
, wrp2br
;
547 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1AR
, &wrp1ar
);
548 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1BR
, &wrp1br
);
549 if (stm32l4_info
->part_info
->has_dual_bank
) {
550 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2AR
, &wrp2ar
);
551 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2BR
, &wrp2br
);
553 /* prevent uninitialized errors */
558 const uint8_t wrp1a_start
= wrp1ar
& stm32l4_info
->wrpxxr_mask
;
559 const uint8_t wrp1a_end
= (wrp1ar
>> 16) & stm32l4_info
->wrpxxr_mask
;
560 const uint8_t wrp1b_start
= wrp1br
& stm32l4_info
->wrpxxr_mask
;
561 const uint8_t wrp1b_end
= (wrp1br
>> 16) & stm32l4_info
->wrpxxr_mask
;
562 const uint8_t wrp2a_start
= wrp2ar
& stm32l4_info
->wrpxxr_mask
;
563 const uint8_t wrp2a_end
= (wrp2ar
>> 16) & stm32l4_info
->wrpxxr_mask
;
564 const uint8_t wrp2b_start
= wrp2br
& stm32l4_info
->wrpxxr_mask
;
565 const uint8_t wrp2b_end
= (wrp2br
>> 16) & stm32l4_info
->wrpxxr_mask
;
567 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
568 if (i
< stm32l4_info
->bank1_sectors
) {
569 if (((i
>= wrp1a_start
) &&
571 ((i
>= wrp1b_start
) &&
573 bank
->sectors
[i
].is_protected
= 1;
575 bank
->sectors
[i
].is_protected
= 0;
577 assert(stm32l4_info
->part_info
->has_dual_bank
== true);
579 snb
= i
- stm32l4_info
->bank1_sectors
;
580 if (((snb
>= wrp2a_start
) &&
581 (snb
<= wrp2a_end
)) ||
582 ((snb
>= wrp2b_start
) &&
584 bank
->sectors
[i
].is_protected
= 1;
586 bank
->sectors
[i
].is_protected
= 0;
592 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
595 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
598 assert((first
<= last
) && (last
< bank
->num_sectors
));
600 if (bank
->target
->state
!= TARGET_HALTED
) {
601 LOG_ERROR("Target not halted");
602 return ERROR_TARGET_NOT_HALTED
;
605 retval
= stm32l4_unlock_reg(bank
);
606 if (retval
!= ERROR_OK
)
611 To erase a sector, follow the procedure below:
612 1. Check that no Flash memory operation is ongoing by
613 checking the BSY bit in the FLASH_SR register
614 2. Set the PER bit and select the page and bank
615 you wish to erase in the FLASH_CR register
616 3. Set the STRT bit in the FLASH_CR register
617 4. Wait for the BSY bit to be cleared
620 for (unsigned int i
= first
; i
<= last
; i
++) {
621 uint32_t erase_flags
;
622 erase_flags
= FLASH_PER
| FLASH_STRT
;
624 if (i
>= stm32l4_info
->bank1_sectors
) {
626 snb
= i
- stm32l4_info
->bank1_sectors
;
627 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
629 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
630 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, erase_flags
);
631 if (retval
!= ERROR_OK
)
634 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
635 if (retval
!= ERROR_OK
)
638 bank
->sectors
[i
].is_erased
= 1;
642 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
644 if (retval
!= ERROR_OK
)
650 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
653 struct target
*target
= bank
->target
;
654 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
656 if (target
->state
!= TARGET_HALTED
) {
657 LOG_ERROR("Target not halted");
658 return ERROR_TARGET_NOT_HALTED
;
663 uint32_t reg_value
= 0xFF; /* Default to bank un-protected */
664 if (last
>= stm32l4_info
->bank1_sectors
) {
666 uint8_t begin
= first
> stm32l4_info
->bank1_sectors
? first
: 0x00;
667 reg_value
= ((last
& 0xFF) << 16) | begin
;
670 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP2AR
, reg_value
, 0xffffffff);
673 reg_value
= 0xFF; /* Default to bank un-protected */
674 if (first
< stm32l4_info
->bank1_sectors
) {
676 uint8_t end
= last
>= stm32l4_info
->bank1_sectors
? 0xFF : last
;
677 reg_value
= (end
<< 16) | (first
& 0xFF);
680 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP1AR
, reg_value
, 0xffffffff);
686 /* Count is in double-words */
687 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
688 uint32_t offset
, uint32_t count
)
690 struct target
*target
= bank
->target
;
691 uint32_t buffer_size
;
692 struct working_area
*write_algorithm
;
693 struct working_area
*source
;
694 uint32_t address
= bank
->base
+ offset
;
695 struct reg_param reg_params
[6];
696 struct armv7m_algorithm armv7m_info
;
697 int retval
= ERROR_OK
;
699 static const uint8_t stm32l4_flash_write_code
[] = {
700 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
703 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
704 &write_algorithm
) != ERROR_OK
) {
705 LOG_WARNING("no working area available, can't do block memory writes");
706 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
709 retval
= target_write_buffer(target
, write_algorithm
->address
,
710 sizeof(stm32l4_flash_write_code
),
711 stm32l4_flash_write_code
);
712 if (retval
!= ERROR_OK
) {
713 target_free_working_area(target
, write_algorithm
);
717 /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
718 buffer_size
= target_get_working_area_avail(target
) & ~(2 * sizeof(uint32_t) - 1);
719 if (buffer_size
< 256) {
720 LOG_WARNING("large enough working area not available, can't do block memory writes");
721 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
722 } else if (buffer_size
> 16384) {
723 /* probably won't benefit from more than 16k ... */
727 if (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
728 LOG_ERROR("allocating working area failed");
729 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
732 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
733 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
735 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
736 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
737 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
738 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
739 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash status register */
740 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
); /* flash control register */
742 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
743 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
744 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
745 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
746 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
));
747 buf_set_u32(reg_params
[5].value
, 0, 32, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
));
749 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 8,
751 ARRAY_SIZE(reg_params
), reg_params
,
752 source
->address
, source
->size
,
753 write_algorithm
->address
, 0,
756 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
757 LOG_ERROR("error executing stm32l4 flash write algorithm");
759 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
761 if (error
& FLASH_WRPERR
)
762 LOG_ERROR("flash memory write protected");
765 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
766 /* Clear but report errors */
767 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, error
);
772 target_free_working_area(target
, source
);
773 target_free_working_area(target
, write_algorithm
);
775 destroy_reg_param(®_params
[0]);
776 destroy_reg_param(®_params
[1]);
777 destroy_reg_param(®_params
[2]);
778 destroy_reg_param(®_params
[3]);
779 destroy_reg_param(®_params
[4]);
780 destroy_reg_param(®_params
[5]);
785 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
786 uint32_t offset
, uint32_t count
)
788 int retval
= ERROR_OK
, retval2
;
790 if (bank
->target
->state
!= TARGET_HALTED
) {
791 LOG_ERROR("Target not halted");
792 return ERROR_TARGET_NOT_HALTED
;
795 /* The flash write must be aligned to a double word (8-bytes) boundary.
796 * The flash infrastructure ensures it, do just a security check */
797 assert(offset
% 8 == 0);
798 assert(count
% 8 == 0);
800 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
801 * data to be written does not go into a gap:
802 * suppose buffer is fully contained in bank from sector 0 to sector
803 * num->sectors - 1 and sectors are ordered according to offset
805 struct flash_sector
*head
= &bank
->sectors
[0];
806 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
808 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
809 /* buffer does not intersect head nor gap behind head */
813 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
814 /* buffer does not intersect tail nor gap before tail */
818 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
819 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
821 /* Now check that there is no gap from head to tail, this should work
822 * even for multiple or non-symmetric gaps
824 while (head
< tail
) {
825 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
826 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
827 bank
->base
+ head
->offset
+ head
->size
,
828 bank
->base
+ (head
+ 1)->offset
- 1);
829 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
834 if (retval
!= ERROR_OK
)
837 retval
= stm32l4_unlock_reg(bank
);
838 if (retval
!= ERROR_OK
)
841 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 8);
844 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
846 if (retval
!= ERROR_OK
) {
847 LOG_ERROR("block write failed");
853 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
857 /* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
858 retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE_L4_G4
, id
);
859 if ((retval
!= ERROR_OK
) || ((*id
& 0xfff) == 0) || ((*id
& 0xfff) == 0xfff)) {
860 retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE_G0
, id
);
861 if ((retval
!= ERROR_OK
) || ((*id
& 0xfff) == 0) || ((*id
& 0xfff) == 0xfff)) {
862 LOG_ERROR("can't get device id");
863 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
870 static int stm32l4_probe(struct flash_bank
*bank
)
872 struct target
*target
= bank
->target
;
873 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
874 const struct stm32l4_part_info
*part_info
;
875 uint16_t flash_size_kb
= 0xffff;
879 stm32l4_info
->probed
= false;
881 /* read stm32 device id registers */
882 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
883 if (retval
!= ERROR_OK
)
886 device_id
= stm32l4_info
->idcode
& 0xFFF;
888 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
889 if (device_id
== stm32l4_parts
[n
].id
)
890 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
893 if (!stm32l4_info
->part_info
) {
894 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
898 part_info
= stm32l4_info
->part_info
;
900 char device_info
[1024];
901 retval
= bank
->driver
->info(bank
, device_info
, sizeof(device_info
));
902 if (retval
!= ERROR_OK
)
905 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s)", stm32l4_info
->idcode
, device_info
);
907 /* get flash size from target. */
908 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
910 /* failed reading flash size or flash size invalid (early silicon),
911 * default to max target family */
912 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
913 || flash_size_kb
> part_info
->max_flash_size_kb
) {
914 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
915 part_info
->max_flash_size_kb
);
916 flash_size_kb
= part_info
->max_flash_size_kb
;
919 /* if the user sets the size manually then ignore the probed value
920 * this allows us to work around devices that have a invalid flash size register value */
921 if (stm32l4_info
->user_bank_size
) {
922 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
923 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
926 LOG_INFO("flash size = %dkbytes", flash_size_kb
);
928 /* did we assign a flash size? */
929 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
931 /* read flash option register */
932 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_OPTR
, &options
);
933 if (retval
!= ERROR_OK
)
936 stm32l4_info
->bank1_sectors
= 0;
937 stm32l4_info
->hole_sectors
= 0;
940 int page_size_kb
= 0;
942 stm32l4_info
->dual_bank_mode
= false;
945 case 0x415: /* STM32L47/L48xx */
946 case 0x461: /* STM32L49/L4Axx */
947 /* if flash size is max (1M) the device is always dual bank
948 * 0x415: has variants with 512K
949 * 0x461: has variants with 512 and 256
950 * for these variants:
951 * if DUAL_BANK = 0 -> single bank
952 * else -> dual bank without gap
953 * note: the page size is invariant
956 num_pages
= flash_size_kb
/ page_size_kb
;
957 stm32l4_info
->bank1_sectors
= num_pages
;
959 /* check DUAL_BANK bit[21] if the flash is less than 1M */
960 if (flash_size_kb
== 1024 || (options
& BIT(21))) {
961 stm32l4_info
->dual_bank_mode
= true;
962 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
965 case 0x435: /* STM32L43/L44xx */
966 case 0x460: /* STM32G07/G08xx */
967 case 0x462: /* STM32L45/L46xx */
968 case 0x464: /* STM32L41/L42xx */
969 case 0x466: /* STM32G03/G04xx */
970 case 0x468: /* STM32G43/G44xx */
971 case 0x479: /* STM32G49/G4Axx */
972 case 0x497: /* STM32WLEx */
973 /* single bank flash */
975 num_pages
= flash_size_kb
/ page_size_kb
;
976 stm32l4_info
->bank1_sectors
= num_pages
;
978 case 0x469: /* STM32G47/G48xx */
979 /* STM32G47/8 can be single/dual bank:
980 * if DUAL_BANK = 0 -> single bank
981 * else -> dual bank WITH gap
984 num_pages
= flash_size_kb
/ page_size_kb
;
985 stm32l4_info
->bank1_sectors
= num_pages
;
986 if (options
& BIT(22)) {
987 stm32l4_info
->dual_bank_mode
= true;
989 num_pages
= flash_size_kb
/ page_size_kb
;
990 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
992 /* for devices with trimmed flash, there is a gap between both banks */
993 stm32l4_info
->hole_sectors
=
994 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
997 case 0x470: /* STM32L4R/L4Sxx */
998 case 0x471: /* STM32L4P5/L4Q5x */
999 /* STM32L4R/S can be single/dual bank:
1000 * if size = 2M check DBANK bit(22)
1001 * if size = 1M check DB1M bit(21)
1002 * STM32L4P/Q can be single/dual bank
1003 * if size = 1M check DBANK bit(22)
1004 * if size = 512K check DB512K bit(21)
1007 num_pages
= flash_size_kb
/ page_size_kb
;
1008 stm32l4_info
->bank1_sectors
= num_pages
;
1009 const bool use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1010 if ((use_dbank_bit
&& (options
& BIT(22))) ||
1011 (!use_dbank_bit
&& (options
& BIT(21)))) {
1012 stm32l4_info
->dual_bank_mode
= true;
1014 num_pages
= flash_size_kb
/ page_size_kb
;
1015 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1018 case 0x495: /* STM32WB5x */
1019 case 0x496: /* STM32WB3x */
1020 /* single bank flash */
1022 num_pages
= flash_size_kb
/ page_size_kb
;
1023 stm32l4_info
->bank1_sectors
= num_pages
;
1026 LOG_ERROR("unsupported device");
1030 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
1032 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
1034 if (gap_size_kb
!= 0) {
1035 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1036 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
1037 * page_size_kb
* 1024,
1038 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
1039 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
1042 /* number of significant bits in WRPxxR differs per device,
1043 * always right adjusted, on some devices non-implemented
1044 * bits read as '0', on others as '1' ...
1045 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1048 /* use *max_flash_size* instead of actual size as the trimmed versions
1049 * certainly use the same number of bits
1050 * max_flash_size is always power of two, so max_pages too
1052 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
1053 assert((max_pages
& (max_pages
- 1)) == 0);
1055 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1056 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
1057 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
1058 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
1060 free(bank
->sectors
);
1062 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
1063 bank
->base
= STM32_FLASH_BANK_BASE
;
1064 bank
->num_sectors
= num_pages
;
1065 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
1066 if (bank
->sectors
== NULL
) {
1067 LOG_ERROR("failed to allocate bank sectors");
1071 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1072 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
1073 /* in dual bank configuration, if there is a gap between banks
1074 * we fix up the sector offset to consider this gap */
1075 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
1076 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
1077 bank
->sectors
[i
].size
= page_size_kb
* 1024;
1078 bank
->sectors
[i
].is_erased
= -1;
1079 bank
->sectors
[i
].is_protected
= 1;
1082 stm32l4_info
->probed
= true;
1086 static int stm32l4_auto_probe(struct flash_bank
*bank
)
1088 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1089 if (stm32l4_info
->probed
)
1092 return stm32l4_probe(bank
);
1095 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1097 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1098 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1101 const char *rev_str
= NULL
;
1102 uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1103 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1104 if (rev_id
== part_info
->revs
[i
].rev
) {
1105 rev_str
= part_info
->revs
[i
].str
;
1107 if (rev_str
!= NULL
) {
1108 snprintf(buf
, buf_size
, "%s - Rev: %s%s",
1109 part_info
->device_str
, rev_str
, stm32l4_info
->probed
?
1110 (stm32l4_info
->dual_bank_mode
? " dual-bank" : " single-bank") : "");
1116 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)%s",
1117 part_info
->device_str
, rev_id
, stm32l4_info
->probed
?
1118 (stm32l4_info
->dual_bank_mode
? " dual-bank" : " single-bank") : "");
1121 snprintf(buf
, buf_size
, "Cannot identify target as an %s device", device_families
);
1128 static int stm32l4_mass_erase(struct flash_bank
*bank
)
1130 int retval
, retval2
;
1131 struct target
*target
= bank
->target
;
1132 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1134 uint32_t action
= FLASH_MER1
;
1136 if (stm32l4_info
->part_info
->has_dual_bank
)
1137 action
|= FLASH_MER2
;
1139 if (target
->state
!= TARGET_HALTED
) {
1140 LOG_ERROR("Target not halted");
1141 return ERROR_TARGET_NOT_HALTED
;
1144 retval
= stm32l4_unlock_reg(bank
);
1145 if (retval
!= ERROR_OK
)
1148 /* mass erase flash memory */
1149 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
1150 if (retval
!= ERROR_OK
)
1153 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
);
1154 if (retval
!= ERROR_OK
)
1157 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
| FLASH_STRT
);
1158 if (retval
!= ERROR_OK
)
1161 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1164 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
1166 if (retval
!= ERROR_OK
)
1172 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
1175 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
1176 return ERROR_COMMAND_SYNTAX_ERROR
;
1179 struct flash_bank
*bank
;
1180 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1181 if (ERROR_OK
!= retval
)
1184 retval
= stm32l4_mass_erase(bank
);
1185 if (retval
== ERROR_OK
) {
1186 /* set all sectors as erased */
1187 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
1188 bank
->sectors
[i
].is_erased
= 1;
1190 command_print(CMD
, "stm32l4x mass erase complete");
1192 command_print(CMD
, "stm32l4x mass erase failed");
1198 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
1201 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1202 return ERROR_COMMAND_SYNTAX_ERROR
;
1205 struct flash_bank
*bank
;
1206 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1207 if (ERROR_OK
!= retval
)
1210 uint32_t reg_offset
, reg_addr
;
1213 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1214 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
1216 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
1217 if (ERROR_OK
!= retval
)
1220 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
1225 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
1228 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1229 return ERROR_COMMAND_SYNTAX_ERROR
;
1232 struct flash_bank
*bank
;
1233 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1234 if (ERROR_OK
!= retval
)
1237 uint32_t reg_offset
;
1239 uint32_t mask
= 0xFFFFFFFF;
1241 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1242 value
= strtoul(CMD_ARGV
[2], NULL
, 16);
1244 mask
= strtoul(CMD_ARGV
[3], NULL
, 16);
1246 command_print(CMD
, "%s Option written.\n"
1247 "INFO: a reset or power cycle is required "
1248 "for the new settings to take effect.", bank
->driver
->name
);
1250 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1254 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
1257 return ERROR_COMMAND_SYNTAX_ERROR
;
1259 struct flash_bank
*bank
;
1260 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1261 if (ERROR_OK
!= retval
)
1264 retval
= stm32l4_unlock_reg(bank
);
1265 if (ERROR_OK
!= retval
)
1268 retval
= stm32l4_unlock_option_reg(bank
);
1269 if (ERROR_OK
!= retval
)
1272 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1273 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1274 * "Note: If the read protection is set while the debugger is still
1275 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1277 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OBL_LAUNCH
);
1279 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
1281 /* Need to re-probe after change */
1282 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1283 stm32l4_info
->probed
= false;
1288 COMMAND_HANDLER(stm32l4_handle_lock_command
)
1290 struct target
*target
= NULL
;
1293 return ERROR_COMMAND_SYNTAX_ERROR
;
1295 struct flash_bank
*bank
;
1296 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1297 if (ERROR_OK
!= retval
)
1300 target
= bank
->target
;
1302 if (target
->state
!= TARGET_HALTED
) {
1303 LOG_ERROR("Target not halted");
1304 return ERROR_TARGET_NOT_HALTED
;
1307 /* set readout protection level 1 by erasing the RDP option byte */
1308 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, 0, 0x000000FF) != ERROR_OK
) {
1309 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1316 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
1318 struct target
*target
= NULL
;
1321 return ERROR_COMMAND_SYNTAX_ERROR
;
1323 struct flash_bank
*bank
;
1324 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1325 if (ERROR_OK
!= retval
)
1328 target
= bank
->target
;
1330 if (target
->state
!= TARGET_HALTED
) {
1331 LOG_ERROR("Target not halted");
1332 return ERROR_TARGET_NOT_HALTED
;
1335 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, RDP_LEVEL_0
, 0x000000FF) != ERROR_OK
) {
1336 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1343 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1346 .handler
= stm32l4_handle_lock_command
,
1347 .mode
= COMMAND_EXEC
,
1349 .help
= "Lock entire flash device.",
1353 .handler
= stm32l4_handle_unlock_command
,
1354 .mode
= COMMAND_EXEC
,
1356 .help
= "Unlock entire protected flash device.",
1359 .name
= "mass_erase",
1360 .handler
= stm32l4_handle_mass_erase_command
,
1361 .mode
= COMMAND_EXEC
,
1363 .help
= "Erase entire flash device.",
1366 .name
= "option_read",
1367 .handler
= stm32l4_handle_option_read_command
,
1368 .mode
= COMMAND_EXEC
,
1369 .usage
= "bank_id reg_offset",
1370 .help
= "Read & Display device option bytes.",
1373 .name
= "option_write",
1374 .handler
= stm32l4_handle_option_write_command
,
1375 .mode
= COMMAND_EXEC
,
1376 .usage
= "bank_id reg_offset value mask",
1377 .help
= "Write device option bit fields with provided value.",
1380 .name
= "option_load",
1381 .handler
= stm32l4_handle_option_load_command
,
1382 .mode
= COMMAND_EXEC
,
1384 .help
= "Force re-load of device options (will cause device reset).",
1386 COMMAND_REGISTRATION_DONE
1389 static const struct command_registration stm32l4_command_handlers
[] = {
1392 .mode
= COMMAND_ANY
,
1393 .help
= "stm32l4x flash command group",
1395 .chain
= stm32l4_exec_command_handlers
,
1397 COMMAND_REGISTRATION_DONE
1400 const struct flash_driver stm32l4x_flash
= {
1402 .commands
= stm32l4_command_handlers
,
1403 .flash_bank_command
= stm32l4_flash_bank_command
,
1404 .erase
= stm32l4_erase
,
1405 .protect
= stm32l4_protect
,
1406 .write
= stm32l4_write
,
1407 .read
= default_flash_read
,
1408 .probe
= stm32l4_probe
,
1409 .auto_probe
= stm32l4_auto_probe
,
1410 .erase_check
= default_flash_blank_check
,
1411 .protect_check
= stm32l4_protect_check
,
1412 .info
= get_stm32l4_info
,
1413 .free_driver_priv
= default_flash_free_driver_priv
,
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