1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/align.h>
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
34 /* STM32L4xxx series for reference.
36 * RM0351 (STM32L4x5/STM32L4x6)
37 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
39 * RM0394 (STM32L43x/44x/45x/46x)
40 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
42 * RM0432 (STM32L4R/4Sxx)
43 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
45 * STM32L476RG Datasheet (for erase timing)
46 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
48 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
49 * an option byte is available to map all sectors to the first bank.
50 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
53 * RM0394 devices have a single bank only.
55 * RM0432 devices have single and dual bank operating modes.
56 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
57 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
58 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
60 * Bank mode is controlled by two different bits in option bytes register.
62 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
63 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
65 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
66 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
70 /* STM32WBxxx series for reference.
73 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
76 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
79 /* STM32WLxxx series for reference.
82 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
85 /* STM32G0xxx series for reference.
88 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
91 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
94 /* STM32G4xxx series for reference.
96 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
97 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
99 * Cat. 2 devices have single bank only, page size is 2kByte.
101 * Cat. 3 devices have single and dual bank operating modes,
102 * Page size is 2kByte (dual mode) or 4kByte (single mode).
104 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
105 * Both banks are treated as a single OpenOCD bank.
107 * Cat. 4 devices have single bank only, page size is 2kByte.
110 /* STM32L5xxx series for reference.
112 * RM0428 (STM32L552xx/STM32L562xx)
113 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
116 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
118 #define FLASH_ERASE_TIMEOUT 250
121 /* relevant STM32L4 flags ****************************************************/
123 /* this flag indicates if the device flash is with dual bank architecture */
124 #define F_HAS_DUAL_BANK BIT(0)
125 /* this flags is used for dual bank devices only, it indicates if the
126 * 4 WRPxx are usable if the device is configured in single-bank mode */
127 #define F_USE_ALL_WRPXX BIT(1)
128 /* this flag indicates if the device embeds a TrustZone security feature */
129 #define F_HAS_TZ BIT(2)
130 /* end of STM32L4 flags ******************************************************/
133 enum stm32l4_flash_reg_index
{
134 STM32_FLASH_ACR_INDEX
,
135 STM32_FLASH_KEYR_INDEX
,
136 STM32_FLASH_OPTKEYR_INDEX
,
137 STM32_FLASH_SR_INDEX
,
138 STM32_FLASH_CR_INDEX
,
139 STM32_FLASH_OPTR_INDEX
,
140 STM32_FLASH_WRP1AR_INDEX
,
141 STM32_FLASH_WRP1BR_INDEX
,
142 STM32_FLASH_WRP2AR_INDEX
,
143 STM32_FLASH_WRP2BR_INDEX
,
144 STM32_FLASH_REG_INDEX_NUM
,
149 RDP_LEVEL_0_5
= 0x55, /* for devices with TrustZone enabled */
154 static const uint32_t stm32l4_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
155 [STM32_FLASH_ACR_INDEX
] = 0x000,
156 [STM32_FLASH_KEYR_INDEX
] = 0x008,
157 [STM32_FLASH_OPTKEYR_INDEX
] = 0x00C,
158 [STM32_FLASH_SR_INDEX
] = 0x010,
159 [STM32_FLASH_CR_INDEX
] = 0x014,
160 [STM32_FLASH_OPTR_INDEX
] = 0x020,
161 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
162 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
163 [STM32_FLASH_WRP2AR_INDEX
] = 0x04C,
164 [STM32_FLASH_WRP2BR_INDEX
] = 0x050,
167 static const uint32_t stm32l5_ns_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
168 [STM32_FLASH_ACR_INDEX
] = 0x000,
169 [STM32_FLASH_KEYR_INDEX
] = 0x008,
170 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
171 [STM32_FLASH_SR_INDEX
] = 0x020,
172 [STM32_FLASH_CR_INDEX
] = 0x028,
173 [STM32_FLASH_OPTR_INDEX
] = 0x040,
174 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
175 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
176 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
177 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
185 struct stm32l4_part_info
{
187 const char *device_str
;
188 const struct stm32l4_rev
*revs
;
189 const size_t num_revs
;
190 const uint16_t max_flash_size_kb
;
191 const uint32_t flags
; /* one bit per feature, see STM32L4 flags: macros F_XXX */
192 const uint32_t flash_regs_base
;
193 const uint32_t *default_flash_regs
;
194 const uint32_t fsize_addr
;
195 const uint32_t otp_base
;
196 const uint32_t otp_size
;
199 struct stm32l4_flash_bank
{
202 unsigned int bank1_sectors
;
205 uint32_t user_bank_size
;
206 uint32_t wrpxxr_mask
;
207 const struct stm32l4_part_info
*part_info
;
208 const uint32_t *flash_regs
;
210 enum stm32l4_rdp rdp
;
221 enum stm32l4_flash_reg_index reg_idx
;
229 /* human readable list of families this drivers supports (sorted alphabetically) */
230 static const char *device_families
= "STM32G0/G4/L4/L4+/L5/WB/WL";
232 static const struct stm32l4_rev stm32_415_revs
[] = {
233 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
236 static const struct stm32l4_rev stm32_435_revs
[] = {
237 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
240 static const struct stm32l4_rev stm32_460_revs
[] = {
241 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
244 static const struct stm32l4_rev stm32_461_revs
[] = {
245 { 0x1000, "A" }, { 0x2000, "B" },
248 static const struct stm32l4_rev stm32_462_revs
[] = {
249 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
252 static const struct stm32l4_rev stm32_464_revs
[] = {
253 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
256 static const struct stm32l4_rev stm32_466_revs
[] = {
257 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
260 static const struct stm32l4_rev stm32_468_revs
[] = {
261 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
264 static const struct stm32l4_rev stm32_469_revs
[] = {
265 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
268 static const struct stm32l4_rev stm32_470_revs
[] = {
269 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
272 static const struct stm32l4_rev stm32_471_revs
[] = {
276 static const struct stm32l4_rev stm32_472_revs
[] = {
277 { 0x1000, "A" }, { 0x2000, "B" },
280 static const struct stm32l4_rev stm32_479_revs
[] = {
284 static const struct stm32l4_rev stm32_495_revs
[] = {
288 static const struct stm32l4_rev stm32_496_revs
[] = {
292 static const struct stm32l4_rev stm32_497_revs
[] = {
296 static const struct stm32l4_part_info stm32l4_parts
[] = {
299 .revs
= stm32_415_revs
,
300 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
301 .device_str
= "STM32L47/L48xx",
302 .max_flash_size_kb
= 1024,
303 .flags
= F_HAS_DUAL_BANK
,
304 .flash_regs_base
= 0x40022000,
305 .default_flash_regs
= stm32l4_flash_regs
,
306 .fsize_addr
= 0x1FFF75E0,
307 .otp_base
= 0x1FFF7000,
312 .revs
= stm32_435_revs
,
313 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
314 .device_str
= "STM32L43/L44xx",
315 .max_flash_size_kb
= 256,
317 .flash_regs_base
= 0x40022000,
318 .default_flash_regs
= stm32l4_flash_regs
,
319 .fsize_addr
= 0x1FFF75E0,
320 .otp_base
= 0x1FFF7000,
325 .revs
= stm32_460_revs
,
326 .num_revs
= ARRAY_SIZE(stm32_460_revs
),
327 .device_str
= "STM32G07/G08xx",
328 .max_flash_size_kb
= 128,
330 .flash_regs_base
= 0x40022000,
331 .default_flash_regs
= stm32l4_flash_regs
,
332 .fsize_addr
= 0x1FFF75E0,
333 .otp_base
= 0x1FFF7000,
338 .revs
= stm32_461_revs
,
339 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
340 .device_str
= "STM32L49/L4Axx",
341 .max_flash_size_kb
= 1024,
342 .flags
= F_HAS_DUAL_BANK
,
343 .flash_regs_base
= 0x40022000,
344 .default_flash_regs
= stm32l4_flash_regs
,
345 .fsize_addr
= 0x1FFF75E0,
346 .otp_base
= 0x1FFF7000,
351 .revs
= stm32_462_revs
,
352 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
353 .device_str
= "STM32L45/L46xx",
354 .max_flash_size_kb
= 512,
356 .flash_regs_base
= 0x40022000,
357 .default_flash_regs
= stm32l4_flash_regs
,
358 .fsize_addr
= 0x1FFF75E0,
359 .otp_base
= 0x1FFF7000,
364 .revs
= stm32_464_revs
,
365 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
366 .device_str
= "STM32L41/L42xx",
367 .max_flash_size_kb
= 128,
369 .flash_regs_base
= 0x40022000,
370 .default_flash_regs
= stm32l4_flash_regs
,
371 .fsize_addr
= 0x1FFF75E0,
372 .otp_base
= 0x1FFF7000,
377 .revs
= stm32_466_revs
,
378 .num_revs
= ARRAY_SIZE(stm32_466_revs
),
379 .device_str
= "STM32G03/G04xx",
380 .max_flash_size_kb
= 64,
382 .flash_regs_base
= 0x40022000,
383 .default_flash_regs
= stm32l4_flash_regs
,
384 .fsize_addr
= 0x1FFF75E0,
385 .otp_base
= 0x1FFF7000,
390 .revs
= stm32_468_revs
,
391 .num_revs
= ARRAY_SIZE(stm32_468_revs
),
392 .device_str
= "STM32G43/G44xx",
393 .max_flash_size_kb
= 128,
395 .flash_regs_base
= 0x40022000,
396 .default_flash_regs
= stm32l4_flash_regs
,
397 .fsize_addr
= 0x1FFF75E0,
398 .otp_base
= 0x1FFF7000,
403 .revs
= stm32_469_revs
,
404 .num_revs
= ARRAY_SIZE(stm32_469_revs
),
405 .device_str
= "STM32G47/G48xx",
406 .max_flash_size_kb
= 512,
407 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
408 .flash_regs_base
= 0x40022000,
409 .default_flash_regs
= stm32l4_flash_regs
,
410 .fsize_addr
= 0x1FFF75E0,
411 .otp_base
= 0x1FFF7000,
416 .revs
= stm32_470_revs
,
417 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
418 .device_str
= "STM32L4R/L4Sxx",
419 .max_flash_size_kb
= 2048,
420 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
421 .flash_regs_base
= 0x40022000,
422 .default_flash_regs
= stm32l4_flash_regs
,
423 .fsize_addr
= 0x1FFF75E0,
424 .otp_base
= 0x1FFF7000,
429 .revs
= stm32_471_revs
,
430 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
431 .device_str
= "STM32L4P5/L4Q5x",
432 .max_flash_size_kb
= 1024,
433 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
434 .flash_regs_base
= 0x40022000,
435 .default_flash_regs
= stm32l4_flash_regs
,
436 .fsize_addr
= 0x1FFF75E0,
437 .otp_base
= 0x1FFF7000,
442 .revs
= stm32_472_revs
,
443 .num_revs
= ARRAY_SIZE(stm32_472_revs
),
444 .device_str
= "STM32L55/L56xx",
445 .max_flash_size_kb
= 512,
446 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
| F_HAS_TZ
,
447 .flash_regs_base
= 0x40022000,
448 .default_flash_regs
= stm32l5_ns_flash_regs
,
449 .fsize_addr
= 0x0BFA05E0,
450 .otp_base
= 0x0BFA0000,
455 .revs
= stm32_479_revs
,
456 .num_revs
= ARRAY_SIZE(stm32_479_revs
),
457 .device_str
= "STM32G49/G4Axx",
458 .max_flash_size_kb
= 512,
460 .flash_regs_base
= 0x40022000,
461 .default_flash_regs
= stm32l4_flash_regs
,
462 .fsize_addr
= 0x1FFF75E0,
463 .otp_base
= 0x1FFF7000,
468 .revs
= stm32_495_revs
,
469 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
470 .device_str
= "STM32WB5x",
471 .max_flash_size_kb
= 1024,
473 .flash_regs_base
= 0x58004000,
474 .default_flash_regs
= stm32l4_flash_regs
,
475 .fsize_addr
= 0x1FFF75E0,
476 .otp_base
= 0x1FFF7000,
481 .revs
= stm32_496_revs
,
482 .num_revs
= ARRAY_SIZE(stm32_496_revs
),
483 .device_str
= "STM32WB3x",
484 .max_flash_size_kb
= 512,
486 .flash_regs_base
= 0x58004000,
487 .default_flash_regs
= stm32l4_flash_regs
,
488 .fsize_addr
= 0x1FFF75E0,
489 .otp_base
= 0x1FFF7000,
494 .revs
= stm32_497_revs
,
495 .num_revs
= ARRAY_SIZE(stm32_497_revs
),
496 .device_str
= "STM32WLEx",
497 .max_flash_size_kb
= 256,
499 .flash_regs_base
= 0x58004000,
500 .default_flash_regs
= stm32l4_flash_regs
,
501 .fsize_addr
= 0x1FFF75E0,
502 .otp_base
= 0x1FFF7000,
507 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
508 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
510 struct stm32l4_flash_bank
*stm32l4_info
;
513 return ERROR_COMMAND_SYNTAX_ERROR
;
515 /* fix-up bank base address: 0 is used for normal flash memory */
517 bank
->base
= STM32_FLASH_BANK_BASE
;
519 stm32l4_info
= calloc(1, sizeof(struct stm32l4_flash_bank
));
521 return ERROR_FAIL
; /* Checkme: What better error to use?*/
522 bank
->driver_priv
= stm32l4_info
;
524 /* The flash write must be aligned to a double word (8-bytes) boundary.
525 * Ask the flash infrastructure to ensure required alignment */
526 bank
->write_start_alignment
= bank
->write_end_alignment
= 8;
528 stm32l4_info
->probed
= false;
529 stm32l4_info
->otp_enabled
= false;
530 stm32l4_info
->user_bank_size
= bank
->size
;
535 /* bitmap helper extension */
541 static void bitmap_to_ranges(unsigned long *bitmap
, unsigned int nbits
,
542 struct range
*ranges
, unsigned int *ranges_count
) {
544 bool last_bit
= 0, cur_bit
;
545 for (unsigned int i
= 0; i
< nbits
; i
++) {
546 cur_bit
= test_bit(i
, bitmap
);
548 if (cur_bit
&& !last_bit
) {
550 ranges
[*ranges_count
- 1].start
= i
;
551 ranges
[*ranges_count
- 1].end
= i
;
552 } else if (cur_bit
&& last_bit
) {
553 /* update (increment) the end this range */
554 ranges
[*ranges_count
- 1].end
= i
;
561 static inline int range_print_one(struct range
*range
, char *str
)
563 if (range
->start
== range
->end
)
564 return sprintf(str
, "[%d]", range
->start
);
566 return sprintf(str
, "[%d,%d]", range
->start
, range
->end
);
569 static char *range_print_alloc(struct range
*ranges
, unsigned int ranges_count
)
571 /* each range will be printed like the following: [start,end]
572 * start and end, both are unsigned int, an unsigned int takes 10 characters max
573 * plus 3 characters for '[', ',' and ']'
574 * thus means each range can take maximum 23 character
575 * after each range we add a ' ' as separator and finally we need the '\0'
576 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
577 char *str
= calloc(1, ranges_count
* (24 * sizeof(char)) + 1);
580 for (unsigned int i
= 0; i
< ranges_count
; i
++) {
581 ptr
+= range_print_one(&(ranges
[i
]), ptr
);
583 if (i
< ranges_count
- 1)
590 /* end of bitmap helper extension */
592 static inline bool stm32l4_is_otp(struct flash_bank
*bank
)
594 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
595 return bank
->base
== stm32l4_info
->part_info
->otp_base
;
598 static int stm32l4_otp_enable(struct flash_bank
*bank
, bool enable
)
600 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
602 if (!stm32l4_is_otp(bank
))
605 char *op_str
= enable
? "enabled" : "disabled";
607 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
609 stm32l4_info
->otp_enabled
== enable
? "already " : "",
612 stm32l4_info
->otp_enabled
= enable
;
617 static inline bool stm32l4_otp_is_enabled(struct flash_bank
*bank
)
619 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
620 return stm32l4_info
->otp_enabled
;
623 static void stm32l4_sync_rdp_tzen(struct flash_bank
*bank
, uint32_t optr_value
)
625 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
629 if (stm32l4_info
->part_info
->flags
& F_HAS_TZ
)
630 tzen
= (optr_value
& FLASH_TZEN
) != 0;
632 uint32_t rdp
= optr_value
& FLASH_RDP_MASK
;
634 /* for devices without TrustZone:
635 * RDP level 0 and 2 values are to 0xAA and 0xCC
636 * Any other value corresponds to RDP level 1
637 * for devices with TrusZone:
638 * RDP level 0 and 2 values are 0xAA and 0xCC
639 * RDP level 0.5 value is 0x55 only if TZEN = 1
640 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
643 if (rdp
!= RDP_LEVEL_0
&& rdp
!= RDP_LEVEL_2
) {
644 if (!tzen
|| (tzen
&& rdp
!= RDP_LEVEL_0_5
))
648 stm32l4_info
->tzen
= tzen
;
649 stm32l4_info
->rdp
= rdp
;
652 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
654 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
655 return stm32l4_info
->part_info
->flash_regs_base
+ reg_offset
;
658 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank
*bank
,
659 enum stm32l4_flash_reg_index reg_index
)
661 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
662 return stm32l4_get_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
]);
665 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
667 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
670 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank
*bank
,
671 enum stm32l4_flash_reg_index reg_index
, uint32_t *value
)
673 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
674 return stm32l4_read_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
677 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
679 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
682 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank
*bank
,
683 enum stm32l4_flash_reg_index reg_index
, uint32_t value
)
685 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
686 return stm32l4_write_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
689 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
692 int retval
= ERROR_OK
;
694 /* wait for busy to clear */
696 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &status
);
697 if (retval
!= ERROR_OK
)
699 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
700 if ((status
& FLASH_BSY
) == 0)
702 if (timeout
-- <= 0) {
703 LOG_ERROR("timed out waiting for flash");
709 if (status
& FLASH_WRPERR
) {
710 LOG_ERROR("stm32x device protected");
714 /* Clear but report errors */
715 if (status
& FLASH_ERROR
) {
716 if (retval
== ERROR_OK
)
718 /* If this operation fails, we ignore it and report the original
721 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, status
& FLASH_ERROR
);
727 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
731 /* first check if not already unlocked
732 * otherwise writing on STM32_FLASH_KEYR will fail
734 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
735 if (retval
!= ERROR_OK
)
738 if ((ctrl
& FLASH_LOCK
) == 0)
741 /* unlock flash registers */
742 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY1
);
743 if (retval
!= ERROR_OK
)
746 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY2
);
747 if (retval
!= ERROR_OK
)
750 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
751 if (retval
!= ERROR_OK
)
754 if (ctrl
& FLASH_LOCK
) {
755 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
756 return ERROR_TARGET_FAILURE
;
762 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
766 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
767 if (retval
!= ERROR_OK
)
770 if ((ctrl
& FLASH_OPTLOCK
) == 0)
773 /* unlock option registers */
774 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY1
);
775 if (retval
!= ERROR_OK
)
778 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY2
);
779 if (retval
!= ERROR_OK
)
782 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
783 if (retval
!= ERROR_OK
)
786 if (ctrl
& FLASH_OPTLOCK
) {
787 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
788 return ERROR_TARGET_FAILURE
;
794 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
795 uint32_t value
, uint32_t mask
)
800 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
801 if (retval
!= ERROR_OK
)
804 retval
= stm32l4_unlock_reg(bank
);
805 if (retval
!= ERROR_OK
)
808 retval
= stm32l4_unlock_option_reg(bank
);
809 if (retval
!= ERROR_OK
)
812 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
814 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
815 if (retval
!= ERROR_OK
)
818 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OPTSTRT
);
819 if (retval
!= ERROR_OK
)
822 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
825 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
| FLASH_OPTLOCK
);
827 if (retval
!= ERROR_OK
)
833 static int stm32l4_get_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
,
834 enum stm32l4_flash_reg_index reg_idx
, int offset
)
836 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
839 wrpxy
->reg_idx
= reg_idx
;
840 wrpxy
->offset
= offset
;
842 ret
= stm32l4_read_flash_reg_by_index(bank
, wrpxy
->reg_idx
, &wrpxy
->value
);
846 wrpxy
->first
= (wrpxy
->value
& stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
847 wrpxy
->last
= ((wrpxy
->value
>> 16) & stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
848 wrpxy
->used
= wrpxy
->first
<= wrpxy
->last
;
853 static int stm32l4_get_all_wrpxy(struct flash_bank
*bank
, enum stm32_bank_id dev_bank_id
,
854 struct stm32l4_wrp
*wrpxy
, unsigned int *n_wrp
)
856 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
861 /* for single bank devices there is 2 WRP regions.
862 * for dual bank devices there is 2 WRP regions per bank,
863 * if configured as single bank only 2 WRP are usable
864 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
865 * note: this should be revised, if a device will have the SWAP banks option
868 int wrp2y_sectors_offset
= -1; /* -1 : unused */
870 /* if bank_id is BANK1 or ALL_BANKS */
871 if (dev_bank_id
!= STM32_BANK2
) {
872 /* get FLASH_WRP1AR */
873 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1AR_INDEX
, 0);
878 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1BR_INDEX
, 0);
882 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
883 if ((stm32l4_info
->part_info
->flags
& F_USE_ALL_WRPXX
) && !stm32l4_info
->dual_bank_mode
)
884 wrp2y_sectors_offset
= 0;
887 /* if bank_id is BANK2 or ALL_BANKS */
888 if (dev_bank_id
!= STM32_BANK1
&& stm32l4_info
->dual_bank_mode
)
889 wrp2y_sectors_offset
= stm32l4_info
->bank1_sectors
;
891 if (wrp2y_sectors_offset
> -1) {
893 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2AR_INDEX
, wrp2y_sectors_offset
);
898 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2BR_INDEX
, wrp2y_sectors_offset
);
906 static int stm32l4_write_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
)
908 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
910 int wrp_start
= wrpxy
->first
- wrpxy
->offset
;
911 int wrp_end
= wrpxy
->last
- wrpxy
->offset
;
913 uint32_t wrp_value
= (wrp_start
& stm32l4_info
->wrpxxr_mask
) | ((wrp_end
& stm32l4_info
->wrpxxr_mask
) << 16);
915 return stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[wrpxy
->reg_idx
], wrp_value
, 0xffffffff);
918 static int stm32l4_write_all_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
, unsigned int n_wrp
)
922 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
923 ret
= stm32l4_write_one_wrpxy(bank
, &wrpxy
[i
]);
931 static int stm32l4_protect_check(struct flash_bank
*bank
)
934 struct stm32l4_wrp wrpxy
[4];
936 int ret
= stm32l4_get_all_wrpxy(bank
, STM32_ALL_BANKS
, wrpxy
, &n_wrp
);
940 /* initialize all sectors as unprotected */
941 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
942 bank
->sectors
[i
].is_protected
= 0;
944 /* now check WRPxy and mark the protected sectors */
945 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
947 for (int s
= wrpxy
[i
].first
; s
<= wrpxy
[i
].last
; s
++)
948 bank
->sectors
[s
].is_protected
= 1;
955 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
958 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
961 assert((first
<= last
) && (last
< bank
->num_sectors
));
963 if (stm32l4_is_otp(bank
)) {
964 LOG_ERROR("cannot erase OTP memory");
965 return ERROR_FLASH_OPER_UNSUPPORTED
;
968 if (bank
->target
->state
!= TARGET_HALTED
) {
969 LOG_ERROR("Target not halted");
970 return ERROR_TARGET_NOT_HALTED
;
973 retval
= stm32l4_unlock_reg(bank
);
974 if (retval
!= ERROR_OK
)
979 To erase a sector, follow the procedure below:
980 1. Check that no Flash memory operation is ongoing by
981 checking the BSY bit in the FLASH_SR register
982 2. Set the PER bit and select the page and bank
983 you wish to erase in the FLASH_CR register
984 3. Set the STRT bit in the FLASH_CR register
985 4. Wait for the BSY bit to be cleared
988 for (unsigned int i
= first
; i
<= last
; i
++) {
989 uint32_t erase_flags
;
990 erase_flags
= FLASH_PER
| FLASH_STRT
;
992 if (i
>= stm32l4_info
->bank1_sectors
) {
994 snb
= i
- stm32l4_info
->bank1_sectors
;
995 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
997 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
998 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, erase_flags
);
999 if (retval
!= ERROR_OK
)
1002 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1003 if (retval
!= ERROR_OK
)
1008 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1010 if (retval
!= ERROR_OK
)
1016 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
, unsigned int last
)
1018 struct target
*target
= bank
->target
;
1019 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1023 if (stm32l4_is_otp(bank
)) {
1024 LOG_ERROR("cannot protect/unprotect OTP memory");
1025 return ERROR_FLASH_OPER_UNSUPPORTED
;
1028 if (target
->state
!= TARGET_HALTED
) {
1029 LOG_ERROR("Target not halted");
1030 return ERROR_TARGET_NOT_HALTED
;
1033 /* the requested sectors could be located into bank1 and/or bank2 */
1034 bool use_bank2
= false;
1035 if (last
>= stm32l4_info
->bank1_sectors
) {
1036 if (first
< stm32l4_info
->bank1_sectors
) {
1037 /* the requested sectors for (un)protection are shared between
1038 * bank 1 and 2, then split the operation */
1040 /* 1- deal with bank 1 sectors */
1041 LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1042 set
? "protection" : "unprotection");
1043 ret
= stm32l4_protect(bank
, set
, first
, stm32l4_info
->bank1_sectors
- 1);
1044 if (ret
!= ERROR_OK
)
1047 /* 2- then continue with bank 2 sectors */
1048 first
= stm32l4_info
->bank1_sectors
;
1054 /* refresh the sectors' protection */
1055 ret
= stm32l4_protect_check(bank
);
1056 if (ret
!= ERROR_OK
)
1059 /* check if the desired protection is already configured */
1060 for (i
= first
; i
<= last
; i
++) {
1061 if (bank
->sectors
[i
].is_protected
!= set
)
1063 else if (i
== last
) {
1064 LOG_INFO("The specified sectors are already %s", set
? "protected" : "unprotected");
1069 /* all sectors from first to last (or part of them) could have different
1070 * protection other than the requested */
1072 struct stm32l4_wrp wrpxy
[4];
1074 ret
= stm32l4_get_all_wrpxy(bank
, use_bank2
? STM32_BANK2
: STM32_BANK1
, wrpxy
, &n_wrp
);
1075 if (ret
!= ERROR_OK
)
1078 /* use bitmap and range helpers to optimize the WRP usage */
1079 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1080 bitmap_zero(pages
, bank
->num_sectors
);
1082 for (i
= 0; i
< n_wrp
; i
++) {
1083 if (wrpxy
[i
].used
) {
1084 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1089 /* we have at most 'n_wrp' WRP areas
1090 * add one range if the user is trying to protect a fifth range */
1091 struct range ranges
[n_wrp
+ 1];
1092 unsigned int ranges_count
= 0;
1094 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1096 /* pretty-print the currently protected ranges */
1097 if (ranges_count
> 0) {
1098 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1099 LOG_DEBUG("current protected areas: %s", ranges_str
);
1102 LOG_DEBUG("current protected areas: none");
1104 if (set
) { /* flash protect */
1105 for (i
= first
; i
<= last
; i
++)
1107 } else { /* flash unprotect */
1108 for (i
= first
; i
<= last
; i
++)
1109 clear_bit(i
, pages
);
1112 /* check the ranges_count after the user request */
1113 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1115 /* pretty-print the requested areas for protection */
1116 if (ranges_count
> 0) {
1117 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1118 LOG_DEBUG("requested areas for protection: %s", ranges_str
);
1121 LOG_DEBUG("requested areas for protection: none");
1123 if (ranges_count
> n_wrp
) {
1124 LOG_ERROR("cannot set the requested protection "
1125 "(only %u write protection areas are available)" , n_wrp
);
1129 /* re-init all WRPxy as disabled (first > last)*/
1130 for (i
= 0; i
< n_wrp
; i
++) {
1131 wrpxy
[i
].first
= wrpxy
[i
].offset
+ 1;
1132 wrpxy
[i
].last
= wrpxy
[i
].offset
;
1135 /* then configure WRPxy areas */
1136 for (i
= 0; i
< ranges_count
; i
++) {
1137 wrpxy
[i
].first
= ranges
[i
].start
;
1138 wrpxy
[i
].last
= ranges
[i
].end
;
1141 /* finally write WRPxy registers */
1142 return stm32l4_write_all_wrpxy(bank
, wrpxy
, n_wrp
);
1145 /* Count is in double-words */
1146 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1147 uint32_t offset
, uint32_t count
)
1149 struct target
*target
= bank
->target
;
1150 uint32_t buffer_size
;
1151 struct working_area
*write_algorithm
;
1152 struct working_area
*source
;
1153 uint32_t address
= bank
->base
+ offset
;
1154 struct reg_param reg_params
[6];
1155 struct armv7m_algorithm armv7m_info
;
1156 int retval
= ERROR_OK
;
1158 static const uint8_t stm32l4_flash_write_code
[] = {
1159 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1162 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
1163 &write_algorithm
) != ERROR_OK
) {
1164 LOG_WARNING("no working area available, can't do block memory writes");
1165 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1168 retval
= target_write_buffer(target
, write_algorithm
->address
,
1169 sizeof(stm32l4_flash_write_code
),
1170 stm32l4_flash_write_code
);
1171 if (retval
!= ERROR_OK
) {
1172 target_free_working_area(target
, write_algorithm
);
1176 /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
1177 buffer_size
= target_get_working_area_avail(target
) & ~(2 * sizeof(uint32_t) - 1);
1178 if (buffer_size
< 256) {
1179 LOG_WARNING("large enough working area not available, can't do block memory writes");
1180 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1181 } else if (buffer_size
> 16384) {
1182 /* probably won't benefit from more than 16k ... */
1183 buffer_size
= 16384;
1186 if (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
1187 LOG_ERROR("allocating working area failed");
1188 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1191 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1192 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1194 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
1195 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
1196 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
1197 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
1198 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash status register */
1199 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
); /* flash control register */
1201 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1202 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
1203 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
1204 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
1205 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
));
1206 buf_set_u32(reg_params
[5].value
, 0, 32, stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
));
1208 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 8,
1210 ARRAY_SIZE(reg_params
), reg_params
,
1211 source
->address
, source
->size
,
1212 write_algorithm
->address
, 0,
1215 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1216 LOG_ERROR("error executing stm32l4 flash write algorithm");
1218 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
1220 if (error
& FLASH_WRPERR
)
1221 LOG_ERROR("flash memory write protected");
1224 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
1225 /* Clear but report errors */
1226 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, error
);
1227 retval
= ERROR_FAIL
;
1231 target_free_working_area(target
, source
);
1232 target_free_working_area(target
, write_algorithm
);
1234 destroy_reg_param(®_params
[0]);
1235 destroy_reg_param(®_params
[1]);
1236 destroy_reg_param(®_params
[2]);
1237 destroy_reg_param(®_params
[3]);
1238 destroy_reg_param(®_params
[4]);
1239 destroy_reg_param(®_params
[5]);
1244 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1245 uint32_t offset
, uint32_t count
)
1247 int retval
= ERROR_OK
, retval2
;
1249 if (stm32l4_is_otp(bank
) && !stm32l4_otp_is_enabled(bank
)) {
1250 LOG_ERROR("OTP memory is disabled for write commands");
1254 if (bank
->target
->state
!= TARGET_HALTED
) {
1255 LOG_ERROR("Target not halted");
1256 return ERROR_TARGET_NOT_HALTED
;
1259 /* The flash write must be aligned to a double word (8-bytes) boundary.
1260 * The flash infrastructure ensures it, do just a security check */
1261 assert(offset
% 8 == 0);
1262 assert(count
% 8 == 0);
1264 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1265 * data to be written does not go into a gap:
1266 * suppose buffer is fully contained in bank from sector 0 to sector
1267 * num->sectors - 1 and sectors are ordered according to offset
1269 struct flash_sector
*head
= &bank
->sectors
[0];
1270 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
1272 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
1273 /* buffer does not intersect head nor gap behind head */
1277 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
1278 /* buffer does not intersect tail nor gap before tail */
1282 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
1283 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
1285 /* Now check that there is no gap from head to tail, this should work
1286 * even for multiple or non-symmetric gaps
1288 while (head
< tail
) {
1289 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
1290 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
1291 bank
->base
+ head
->offset
+ head
->size
,
1292 bank
->base
+ (head
+ 1)->offset
- 1);
1293 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
1298 if (retval
!= ERROR_OK
)
1301 retval
= stm32l4_unlock_reg(bank
);
1302 if (retval
!= ERROR_OK
)
1305 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 8);
1308 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1310 if (retval
!= ERROR_OK
) {
1311 LOG_ERROR("block write failed");
1317 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
1321 /* try reading possible IDCODE registers, in the following order */
1322 uint32_t dbgmcu_idcode
[] = {DBGMCU_IDCODE_L4_G4
, DBGMCU_IDCODE_G0
, DBGMCU_IDCODE_L5
};
1324 for (unsigned int i
= 0; i
< ARRAY_SIZE(dbgmcu_idcode
); i
++) {
1325 retval
= target_read_u32(bank
->target
, dbgmcu_idcode
[i
], id
);
1326 if ((retval
== ERROR_OK
) && ((*id
& 0xfff) != 0) && ((*id
& 0xfff) != 0xfff))
1330 LOG_ERROR("can't get the device id");
1331 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
1334 static const char *get_stm32l4_rev_str(struct flash_bank
*bank
)
1336 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1337 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1340 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1341 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1342 if (rev_id
== part_info
->revs
[i
].rev
)
1343 return part_info
->revs
[i
].str
;
1348 static const char *get_stm32l4_bank_type_str(struct flash_bank
*bank
)
1350 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1351 assert(stm32l4_info
->part_info
);
1352 return stm32l4_is_otp(bank
) ? "OTP" :
1353 stm32l4_info
->dual_bank_mode
? "Flash dual" :
1357 static int stm32l4_probe(struct flash_bank
*bank
)
1359 struct target
*target
= bank
->target
;
1360 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1361 const struct stm32l4_part_info
*part_info
;
1362 uint16_t flash_size_kb
= 0xffff;
1365 stm32l4_info
->probed
= false;
1367 /* read stm32 device id registers */
1368 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
1369 if (retval
!= ERROR_OK
)
1372 const uint32_t device_id
= stm32l4_info
->idcode
& 0xFFF;
1374 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
1375 if (device_id
== stm32l4_parts
[n
].id
) {
1376 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
1381 if (!stm32l4_info
->part_info
) {
1382 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
1386 part_info
= stm32l4_info
->part_info
;
1387 const char *rev_str
= get_stm32l4_rev_str(bank
);
1388 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1390 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x - %s-bank)",
1391 stm32l4_info
->idcode
, part_info
->device_str
, rev_str
, rev_id
,
1392 get_stm32l4_bank_type_str(bank
));
1394 stm32l4_info
->flash_regs
= stm32l4_info
->part_info
->default_flash_regs
;
1396 /* read flash option register */
1397 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &options
);
1398 if (retval
!= ERROR_OK
)
1401 stm32l4_sync_rdp_tzen(bank
, options
);
1403 if (part_info
->flags
& F_HAS_TZ
)
1404 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1406 stm32l4_info
->tzen
? "enabled" : "disabled");
1408 LOG_INFO("RDP level %s (0x%02X)",
1409 stm32l4_info
->rdp
== RDP_LEVEL_0
? "0" : stm32l4_info
->rdp
== RDP_LEVEL_0_5
? "0.5" : "1",
1412 if (stm32l4_is_otp(bank
)) {
1413 bank
->size
= part_info
->otp_size
;
1415 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT
, bank
->size
, bank
->base
);
1417 /* OTP memory is considered as one sector */
1418 free(bank
->sectors
);
1419 bank
->num_sectors
= 1;
1420 bank
->sectors
= alloc_block_array(0, part_info
->otp_size
, 1);
1422 if (!bank
->sectors
) {
1423 LOG_ERROR("failed to allocate bank sectors");
1427 stm32l4_info
->probed
= true;
1429 } else if (bank
->base
!= STM32_FLASH_BANK_BASE
) {
1430 LOG_ERROR("invalid bank base address");
1434 /* get flash size from target. */
1435 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
1437 /* failed reading flash size or flash size invalid (early silicon),
1438 * default to max target family */
1439 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
1440 || flash_size_kb
> part_info
->max_flash_size_kb
) {
1441 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1442 part_info
->max_flash_size_kb
);
1443 flash_size_kb
= part_info
->max_flash_size_kb
;
1446 /* if the user sets the size manually then ignore the probed value
1447 * this allows us to work around devices that have a invalid flash size register value */
1448 if (stm32l4_info
->user_bank_size
) {
1449 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1450 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
1453 LOG_INFO("flash size = %dkbytes", flash_size_kb
);
1455 /* did we assign a flash size? */
1456 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
1458 stm32l4_info
->bank1_sectors
= 0;
1459 stm32l4_info
->hole_sectors
= 0;
1462 int page_size_kb
= 0;
1464 stm32l4_info
->dual_bank_mode
= false;
1465 bool use_dbank_bit
= false;
1467 switch (device_id
) {
1468 case 0x415: /* STM32L47/L48xx */
1469 case 0x461: /* STM32L49/L4Axx */
1470 /* if flash size is max (1M) the device is always dual bank
1471 * 0x415: has variants with 512K
1472 * 0x461: has variants with 512 and 256
1473 * for these variants:
1474 * if DUAL_BANK = 0 -> single bank
1475 * else -> dual bank without gap
1476 * note: the page size is invariant
1479 num_pages
= flash_size_kb
/ page_size_kb
;
1480 stm32l4_info
->bank1_sectors
= num_pages
;
1482 /* check DUAL_BANK bit[21] if the flash is less than 1M */
1483 if (flash_size_kb
== 1024 || (options
& BIT(21))) {
1484 stm32l4_info
->dual_bank_mode
= true;
1485 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1488 case 0x435: /* STM32L43/L44xx */
1489 case 0x460: /* STM32G07/G08xx */
1490 case 0x462: /* STM32L45/L46xx */
1491 case 0x464: /* STM32L41/L42xx */
1492 case 0x466: /* STM32G03/G04xx */
1493 case 0x468: /* STM32G43/G44xx */
1494 case 0x479: /* STM32G49/G4Axx */
1495 case 0x497: /* STM32WLEx */
1496 /* single bank flash */
1498 num_pages
= flash_size_kb
/ page_size_kb
;
1499 stm32l4_info
->bank1_sectors
= num_pages
;
1501 case 0x469: /* STM32G47/G48xx */
1502 /* STM32G47/8 can be single/dual bank:
1503 * if DUAL_BANK = 0 -> single bank
1504 * else -> dual bank WITH gap
1507 num_pages
= flash_size_kb
/ page_size_kb
;
1508 stm32l4_info
->bank1_sectors
= num_pages
;
1509 if (options
& BIT(22)) {
1510 stm32l4_info
->dual_bank_mode
= true;
1512 num_pages
= flash_size_kb
/ page_size_kb
;
1513 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1515 /* for devices with trimmed flash, there is a gap between both banks */
1516 stm32l4_info
->hole_sectors
=
1517 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
1520 case 0x470: /* STM32L4R/L4Sxx */
1521 case 0x471: /* STM32L4P5/L4Q5x */
1522 /* STM32L4R/S can be single/dual bank:
1523 * if size = 2M check DBANK bit(22)
1524 * if size = 1M check DB1M bit(21)
1525 * STM32L4P/Q can be single/dual bank
1526 * if size = 1M check DBANK bit(22)
1527 * if size = 512K check DB512K bit(21)
1530 num_pages
= flash_size_kb
/ page_size_kb
;
1531 stm32l4_info
->bank1_sectors
= num_pages
;
1532 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1533 if ((use_dbank_bit
&& (options
& BIT(22))) ||
1534 (!use_dbank_bit
&& (options
& BIT(21)))) {
1535 stm32l4_info
->dual_bank_mode
= true;
1537 num_pages
= flash_size_kb
/ page_size_kb
;
1538 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1541 case 0x472: /* STM32L55/L56xx */
1542 /* STM32L55/L56xx can be single/dual bank:
1543 * if size = 512K check DBANK bit(22)
1544 * if size = 256K check DB256K bit(21)
1547 num_pages
= flash_size_kb
/ page_size_kb
;
1548 stm32l4_info
->bank1_sectors
= num_pages
;
1549 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1550 if ((use_dbank_bit
&& (options
& BIT(22))) ||
1551 (!use_dbank_bit
&& (options
& BIT(21)))) {
1552 stm32l4_info
->dual_bank_mode
= true;
1554 num_pages
= flash_size_kb
/ page_size_kb
;
1555 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1558 case 0x495: /* STM32WB5x */
1559 case 0x496: /* STM32WB3x */
1560 /* single bank flash */
1562 num_pages
= flash_size_kb
/ page_size_kb
;
1563 stm32l4_info
->bank1_sectors
= num_pages
;
1566 LOG_ERROR("unsupported device");
1570 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
1572 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
1574 if (gap_size_kb
!= 0) {
1575 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1576 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
1577 * page_size_kb
* 1024,
1578 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
1579 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
1582 /* number of significant bits in WRPxxR differs per device,
1583 * always right adjusted, on some devices non-implemented
1584 * bits read as '0', on others as '1' ...
1585 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1588 /* use *max_flash_size* instead of actual size as the trimmed versions
1589 * certainly use the same number of bits
1590 * max_flash_size is always power of two, so max_pages too
1592 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
1593 assert(IS_PWR_OF_2(max_pages
));
1595 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1596 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
1597 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
1598 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
1600 free(bank
->sectors
);
1602 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
1603 bank
->num_sectors
= num_pages
;
1604 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
1605 if (!bank
->sectors
) {
1606 LOG_ERROR("failed to allocate bank sectors");
1610 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1611 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
1612 /* in dual bank configuration, if there is a gap between banks
1613 * we fix up the sector offset to consider this gap */
1614 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
1615 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
1616 bank
->sectors
[i
].size
= page_size_kb
* 1024;
1617 bank
->sectors
[i
].is_erased
= -1;
1618 bank
->sectors
[i
].is_protected
= 1;
1621 stm32l4_info
->probed
= true;
1625 static int stm32l4_auto_probe(struct flash_bank
*bank
)
1627 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1628 if (stm32l4_info
->probed
)
1631 return stm32l4_probe(bank
);
1634 static int get_stm32l4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
1636 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1637 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1640 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1641 command_print_sameline(cmd
, "%s - Rev %s : 0x%04x", part_info
->device_str
,
1642 get_stm32l4_rev_str(bank
), rev_id
);
1643 if (stm32l4_info
->probed
)
1644 command_print_sameline(cmd
, " - %s-bank", get_stm32l4_bank_type_str(bank
));
1646 command_print_sameline(cmd
, "Cannot identify target as an %s device", device_families
);
1652 static int stm32l4_mass_erase(struct flash_bank
*bank
)
1654 int retval
, retval2
;
1655 struct target
*target
= bank
->target
;
1656 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1658 if (stm32l4_is_otp(bank
)) {
1659 LOG_ERROR("cannot erase OTP memory");
1660 return ERROR_FLASH_OPER_UNSUPPORTED
;
1663 uint32_t action
= FLASH_MER1
;
1665 if (stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)
1666 action
|= FLASH_MER2
;
1668 if (target
->state
!= TARGET_HALTED
) {
1669 LOG_ERROR("Target not halted");
1670 return ERROR_TARGET_NOT_HALTED
;
1673 retval
= stm32l4_unlock_reg(bank
);
1674 if (retval
!= ERROR_OK
)
1677 /* mass erase flash memory */
1678 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
1679 if (retval
!= ERROR_OK
)
1682 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
);
1683 if (retval
!= ERROR_OK
)
1686 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
| FLASH_STRT
);
1687 if (retval
!= ERROR_OK
)
1690 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1693 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1695 if (retval
!= ERROR_OK
)
1701 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
1704 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
1705 return ERROR_COMMAND_SYNTAX_ERROR
;
1708 struct flash_bank
*bank
;
1709 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1710 if (retval
!= ERROR_OK
)
1713 retval
= stm32l4_mass_erase(bank
);
1714 if (retval
== ERROR_OK
)
1715 command_print(CMD
, "stm32l4x mass erase complete");
1717 command_print(CMD
, "stm32l4x mass erase failed");
1722 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
1725 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1726 return ERROR_COMMAND_SYNTAX_ERROR
;
1729 struct flash_bank
*bank
;
1730 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1731 if (retval
!= ERROR_OK
)
1734 uint32_t reg_offset
, reg_addr
;
1737 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1738 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
1740 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
1741 if (retval
!= ERROR_OK
)
1744 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
1749 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
1752 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1753 return ERROR_COMMAND_SYNTAX_ERROR
;
1756 struct flash_bank
*bank
;
1757 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1758 if (retval
!= ERROR_OK
)
1761 uint32_t reg_offset
;
1763 uint32_t mask
= 0xFFFFFFFF;
1765 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1766 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1769 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
1771 command_print(CMD
, "%s Option written.\n"
1772 "INFO: a reset or power cycle is required "
1773 "for the new settings to take effect.", bank
->driver
->name
);
1775 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1779 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
1782 return ERROR_COMMAND_SYNTAX_ERROR
;
1784 struct flash_bank
*bank
;
1785 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1786 if (retval
!= ERROR_OK
)
1789 retval
= stm32l4_unlock_reg(bank
);
1790 if (retval
!= ERROR_OK
)
1793 retval
= stm32l4_unlock_option_reg(bank
);
1794 if (retval
!= ERROR_OK
)
1797 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1798 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1799 * "Note: If the read protection is set while the debugger is still
1800 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1802 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OBL_LAUNCH
);
1804 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
1806 /* Need to re-probe after change */
1807 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1808 stm32l4_info
->probed
= false;
1813 COMMAND_HANDLER(stm32l4_handle_lock_command
)
1815 struct target
*target
= NULL
;
1818 return ERROR_COMMAND_SYNTAX_ERROR
;
1820 struct flash_bank
*bank
;
1821 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1822 if (retval
!= ERROR_OK
)
1825 if (stm32l4_is_otp(bank
)) {
1826 LOG_ERROR("cannot lock/unlock OTP memory");
1827 return ERROR_FLASH_OPER_UNSUPPORTED
;
1830 target
= bank
->target
;
1832 if (target
->state
!= TARGET_HALTED
) {
1833 LOG_ERROR("Target not halted");
1834 return ERROR_TARGET_NOT_HALTED
;
1837 /* set readout protection level 1 by erasing the RDP option byte */
1838 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1839 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
1840 RDP_LEVEL_1
, FLASH_RDP_MASK
) != ERROR_OK
) {
1841 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1848 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
1850 struct target
*target
= NULL
;
1853 return ERROR_COMMAND_SYNTAX_ERROR
;
1855 struct flash_bank
*bank
;
1856 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1857 if (retval
!= ERROR_OK
)
1860 if (stm32l4_is_otp(bank
)) {
1861 LOG_ERROR("cannot lock/unlock OTP memory");
1862 return ERROR_FLASH_OPER_UNSUPPORTED
;
1865 target
= bank
->target
;
1867 if (target
->state
!= TARGET_HALTED
) {
1868 LOG_ERROR("Target not halted");
1869 return ERROR_TARGET_NOT_HALTED
;
1872 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1873 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
1874 RDP_LEVEL_0
, FLASH_RDP_MASK
) != ERROR_OK
) {
1875 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1882 COMMAND_HANDLER(stm32l4_handle_wrp_info_command
)
1884 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
1885 return ERROR_COMMAND_SYNTAX_ERROR
;
1887 struct flash_bank
*bank
;
1888 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1889 if (retval
!= ERROR_OK
)
1892 if (stm32l4_is_otp(bank
)) {
1893 LOG_ERROR("OTP memory does not have write protection areas");
1894 return ERROR_FLASH_OPER_UNSUPPORTED
;
1897 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1898 enum stm32_bank_id dev_bank_id
= STM32_ALL_BANKS
;
1899 if (CMD_ARGC
== 2) {
1900 if (strcmp(CMD_ARGV
[1], "bank1") == 0)
1901 dev_bank_id
= STM32_BANK1
;
1902 else if (strcmp(CMD_ARGV
[1], "bank2") == 0)
1903 dev_bank_id
= STM32_BANK2
;
1905 return ERROR_COMMAND_ARGUMENT_INVALID
;
1908 if (dev_bank_id
== STM32_BANK2
) {
1909 if (!(stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)) {
1910 LOG_ERROR("this device has no second bank");
1912 } else if (!stm32l4_info
->dual_bank_mode
) {
1913 LOG_ERROR("this device is configured in single bank mode");
1919 unsigned int n_wrp
, i
;
1920 struct stm32l4_wrp wrpxy
[4];
1922 ret
= stm32l4_get_all_wrpxy(bank
, dev_bank_id
, wrpxy
, &n_wrp
);
1923 if (ret
!= ERROR_OK
)
1926 /* use bitmap and range helpers to better describe protected areas */
1927 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1928 bitmap_zero(pages
, bank
->num_sectors
);
1930 for (i
= 0; i
< n_wrp
; i
++) {
1931 if (wrpxy
[i
].used
) {
1932 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1937 /* we have at most 'n_wrp' WRP areas */
1938 struct range ranges
[n_wrp
];
1939 unsigned int ranges_count
= 0;
1941 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1943 if (ranges_count
> 0) {
1944 /* pretty-print the protected ranges */
1945 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1946 command_print(CMD
, "protected areas: %s", ranges_str
);
1949 command_print(CMD
, "no protected areas");
1954 COMMAND_HANDLER(stm32l4_handle_otp_command
)
1957 return ERROR_COMMAND_SYNTAX_ERROR
;
1959 struct flash_bank
*bank
;
1960 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1961 if (retval
!= ERROR_OK
)
1964 if (!stm32l4_is_otp(bank
)) {
1965 command_print(CMD
, "the specified bank is not an OTP memory");
1968 if (strcmp(CMD_ARGV
[1], "enable") == 0)
1969 stm32l4_otp_enable(bank
, true);
1970 else if (strcmp(CMD_ARGV
[1], "disable") == 0)
1971 stm32l4_otp_enable(bank
, false);
1972 else if (strcmp(CMD_ARGV
[1], "show") == 0)
1973 command_print(CMD
, "OTP memory bank #%d is %s for write commands.",
1974 bank
->bank_number
, stm32l4_otp_is_enabled(bank
) ? "enabled" : "disabled");
1976 return ERROR_COMMAND_SYNTAX_ERROR
;
1981 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1984 .handler
= stm32l4_handle_lock_command
,
1985 .mode
= COMMAND_EXEC
,
1987 .help
= "Lock entire flash device.",
1991 .handler
= stm32l4_handle_unlock_command
,
1992 .mode
= COMMAND_EXEC
,
1994 .help
= "Unlock entire protected flash device.",
1997 .name
= "mass_erase",
1998 .handler
= stm32l4_handle_mass_erase_command
,
1999 .mode
= COMMAND_EXEC
,
2001 .help
= "Erase entire flash device.",
2004 .name
= "option_read",
2005 .handler
= stm32l4_handle_option_read_command
,
2006 .mode
= COMMAND_EXEC
,
2007 .usage
= "bank_id reg_offset",
2008 .help
= "Read & Display device option bytes.",
2011 .name
= "option_write",
2012 .handler
= stm32l4_handle_option_write_command
,
2013 .mode
= COMMAND_EXEC
,
2014 .usage
= "bank_id reg_offset value mask",
2015 .help
= "Write device option bit fields with provided value.",
2019 .handler
= stm32l4_handle_wrp_info_command
,
2020 .mode
= COMMAND_EXEC
,
2021 .usage
= "bank_id [bank1|bank2]",
2022 .help
= "list the protected areas using WRP",
2025 .name
= "option_load",
2026 .handler
= stm32l4_handle_option_load_command
,
2027 .mode
= COMMAND_EXEC
,
2029 .help
= "Force re-load of device options (will cause device reset).",
2033 .handler
= stm32l4_handle_otp_command
,
2034 .mode
= COMMAND_EXEC
,
2035 .usage
= "<bank_id> <enable|disable|show>",
2036 .help
= "OTP (One Time Programmable) memory write enable/disable",
2038 COMMAND_REGISTRATION_DONE
2041 static const struct command_registration stm32l4_command_handlers
[] = {
2044 .mode
= COMMAND_ANY
,
2045 .help
= "stm32l4x flash command group",
2047 .chain
= stm32l4_exec_command_handlers
,
2049 COMMAND_REGISTRATION_DONE
2052 const struct flash_driver stm32l4x_flash
= {
2054 .commands
= stm32l4_command_handlers
,
2055 .flash_bank_command
= stm32l4_flash_bank_command
,
2056 .erase
= stm32l4_erase
,
2057 .protect
= stm32l4_protect
,
2058 .write
= stm32l4_write
,
2059 .read
= default_flash_read
,
2060 .probe
= stm32l4_probe
,
2061 .auto_probe
= stm32l4_auto_probe
,
2062 .erase_check
= default_flash_blank_check
,
2063 .protect_check
= stm32l4_protect_check
,
2064 .info
= get_stm32l4_info
,
2065 .free_driver_priv
= default_flash_free_driver_priv
,