1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35 #include <target/cortex_m.h>
37 /* stm32lx flash register locations */
39 #define FLASH_BASE 0x40023C00
40 #define FLASH_ACR 0x40023C00
41 #define FLASH_PECR 0x40023C04
42 #define FLASH_PDKEYR 0x40023C08
43 #define FLASH_PEKEYR 0x40023C0C
44 #define FLASH_PRGKEYR 0x40023C10
45 #define FLASH_OPTKEYR 0x40023C14
46 #define FLASH_SR 0x40023C18
47 #define FLASH_OBR 0x40023C1C
48 #define FLASH_WRPR 0x40023C20
51 #define FLASH_ACR__LATENCY (1<<0)
52 #define FLASH_ACR__PRFTEN (1<<1)
53 #define FLASH_ACR__ACC64 (1<<2)
54 #define FLASH_ACR__SLEEP_PD (1<<3)
55 #define FLASH_ACR__RUN_PD (1<<4)
58 #define FLASH_PECR__PELOCK (1<<0)
59 #define FLASH_PECR__PRGLOCK (1<<1)
60 #define FLASH_PECR__OPTLOCK (1<<2)
61 #define FLASH_PECR__PROG (1<<3)
62 #define FLASH_PECR__DATA (1<<4)
63 #define FLASH_PECR__FTDW (1<<8)
64 #define FLASH_PECR__ERASE (1<<9)
65 #define FLASH_PECR__FPRG (1<<10)
66 #define FLASH_PECR__EOPIE (1<<16)
67 #define FLASH_PECR__ERRIE (1<<17)
68 #define FLASH_PECR__OBL_LAUNCH (1<<18)
71 #define FLASH_SR__BSY (1<<0)
72 #define FLASH_SR__EOP (1<<1)
73 #define FLASH_SR__ENDHV (1<<2)
74 #define FLASH_SR__READY (1<<3)
75 #define FLASH_SR__WRPERR (1<<8)
76 #define FLASH_SR__PGAERR (1<<9)
77 #define FLASH_SR__SIZERR (1<<10)
78 #define FLASH_SR__OPTVERR (1<<11)
81 #define PEKEY1 0x89ABCDEF
82 #define PEKEY2 0x02030405
83 #define PRGKEY1 0x8C9DAEBF
84 #define PRGKEY2 0x13141516
85 #define OPTKEY1 0xFBEAD9C8
86 #define OPTKEY2 0x24252627
89 #define DBGMCU_IDCODE 0xE0042000
90 #define F_SIZE 0x1FF8004C
91 #define F_SIZE_MP 0x1FF800CC /* on 0x427 Medium+ and 0x436 HD devices */
94 #define FLASH_PAGE_SIZE 256
95 #define FLASH_SECTOR_SIZE 4096
96 #define FLASH_PAGES_PER_SECTOR 16
97 #define FLASH_BANK0_ADDRESS 0x08000000
99 /* stm32lx option byte register location */
100 #define OB_RDP 0x1FF80000
101 #define OB_USER 0x1FF80004
102 #define OB_WRP0_1 0x1FF80008
103 #define OB_WRP2_3 0x1FF8000C
106 #define OB_RDP__LEVEL0 0xFF5500AA
107 #define OB_RDP__LEVEL1 0xFFFF0000
109 /* stm32lx RCC register locations */
110 #define RCC_CR 0x40023800
111 #define RCC_ICSCR 0x40023804
112 #define RCC_CFGR 0x40023808
115 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
117 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
118 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
119 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
120 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
121 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
123 struct stm32lx_flash_bank
{
126 uint32_t user_bank_size
;
129 /* flash bank stm32lx <base> <size> 0 0 <target#>
131 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
133 struct stm32lx_flash_bank
*stm32lx_info
;
135 return ERROR_COMMAND_SYNTAX_ERROR
;
137 /* Create the bank structure */
138 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
140 /* Check allocation */
141 if (stm32lx_info
== NULL
) {
142 LOG_ERROR("failed to allocate bank structure");
146 bank
->driver_priv
= stm32lx_info
;
148 stm32lx_info
->probed
= 0;
149 stm32lx_info
->has_dual_banks
= false;
150 stm32lx_info
->user_bank_size
= bank
->size
;
155 static int stm32lx_protect_check(struct flash_bank
*bank
)
158 struct target
*target
= bank
->target
;
163 * Read the WRPR word, and check each bit (corresponding to each
166 retval
= target_read_u32(target
, FLASH_WRPR
, &wrpr
);
167 if (retval
!= ERROR_OK
)
170 for (int i
= 0; i
< 32; i
++) {
172 bank
->sectors
[i
].is_protected
= 1;
174 bank
->sectors
[i
].is_protected
= 0;
179 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
184 * It could be possible to do a mass erase if all sectors must be
185 * erased, but it is not implemented yet.
188 if (bank
->target
->state
!= TARGET_HALTED
) {
189 LOG_ERROR("Target not halted");
190 return ERROR_TARGET_NOT_HALTED
;
194 * Loop over the selected sectors and erase them
196 for (int i
= first
; i
<= last
; i
++) {
197 retval
= stm32lx_erase_sector(bank
, i
);
198 if (retval
!= ERROR_OK
)
200 bank
->sectors
[i
].is_erased
= 1;
205 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
208 LOG_WARNING("protection of the STM32L flash is not implemented");
212 static int stm32lx_write_half_pages(struct flash_bank
*bank
, uint8_t *buffer
,
213 uint32_t offset
, uint32_t count
)
215 struct target
*target
= bank
->target
;
216 uint32_t buffer_size
= 16384;
217 struct working_area
*write_algorithm
;
218 struct working_area
*source
;
219 uint32_t address
= bank
->base
+ offset
;
221 struct reg_param reg_params
[3];
222 struct armv7m_algorithm armv7m_info
;
224 int retval
= ERROR_OK
;
226 /* see contib/loaders/flash/stm32lx.S for src */
228 static const uint8_t stm32lx_flash_write_code
[] = {
230 0x00, 0x23, /* movs r3, #0 */
231 0x04, 0xe0, /* b test_done */
234 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
235 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
236 0x01, 0x33, /* adds r3, #1 */
239 0x93, 0x42, /* cmp r3, r2 */
240 0xf8, 0xd3, /* bcc write_word */
241 0x00, 0xbe, /* bkpt 0 */
244 /* Check if there is an even number of half pages (128bytes) */
246 LOG_ERROR("there should be an even number "
247 "of half pages = 128 bytes (count = %" PRIi32
" bytes)", count
);
251 /* flash write code */
252 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
253 &write_algorithm
) != ERROR_OK
) {
254 LOG_DEBUG("no working area for block memory writes");
255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
258 /* Write the flashing code */
259 retval
= target_write_buffer(target
,
260 write_algorithm
->address
,
261 sizeof(stm32lx_flash_write_code
),
262 stm32lx_flash_write_code
);
263 if (retval
!= ERROR_OK
) {
264 target_free_working_area(target
, write_algorithm
);
268 /* Allocate half pages memory */
269 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
270 if (buffer_size
> 1024)
275 if (buffer_size
<= 256) {
276 /* we already allocated the writing code, but failed to get a
277 * buffer, free the algorithm */
278 target_free_working_area(target
, write_algorithm
);
280 LOG_WARNING("no large enough working area available, can't do block memory writes");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
285 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
286 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
287 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
288 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
289 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
291 /* Enable half-page write */
292 retval
= stm32lx_enable_write_half_page(bank
);
293 if (retval
!= ERROR_OK
) {
294 target_free_working_area(target
, source
);
295 target_free_working_area(target
, write_algorithm
);
297 destroy_reg_param(®_params
[0]);
298 destroy_reg_param(®_params
[1]);
299 destroy_reg_param(®_params
[2]);
303 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
304 if (armv7m
== NULL
) {
306 /* something is very wrong if armv7m is NULL */
307 LOG_ERROR("unable to get armv7m target");
311 /* save any DEMCR flags and configure target to catch any Hard Faults */
312 uint32_t demcr_save
= armv7m
->demcr
;
313 armv7m
->demcr
= VC_HARDERR
;
315 /* Loop while there are bytes to write */
318 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
320 /* Write the next half pages */
321 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
322 if (retval
!= ERROR_OK
)
325 /* 4: Store useful information in the registers */
326 /* the destination address of the copy (R0) */
327 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
328 /* The source address of the copy (R1) */
329 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
330 /* The length of the copy (R2) */
331 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
333 /* 5: Execute the bunch of code */
334 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
335 / sizeof(*reg_params
), reg_params
,
336 write_algorithm
->address
, 0, 10000, &armv7m_info
);
337 if (retval
!= ERROR_OK
)
340 /* check for Hard Fault */
341 if (armv7m
->exception_number
== 3)
344 /* 6: Wait while busy */
345 retval
= stm32lx_wait_until_bsy_clear(bank
);
346 if (retval
!= ERROR_OK
)
349 buffer
+= this_count
;
350 address
+= this_count
;
354 /* restore previous flags */
355 armv7m
->demcr
= demcr_save
;
357 if (armv7m
->exception_number
== 3) {
359 /* the stm32l15x devices seem to have an issue when blank.
360 * if a ram loader is executed on a blank device it will
361 * Hard Fault, this issue does not happen for a already programmed device.
362 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
363 * The workaround of handling the Hard Fault exception does work, but makes the
364 * loader more complicated, as a compromise we manually write the pages, programming time
365 * is reduced by 50% using this slower method.
368 LOG_WARNING("couldn't use loader, falling back to page memory writes");
372 this_count
= (count
> 128) ? 128 : count
;
374 /* Write the next half pages */
375 retval
= target_write_buffer(target
, address
, this_count
, buffer
);
376 if (retval
!= ERROR_OK
)
379 /* Wait while busy */
380 retval
= stm32lx_wait_until_bsy_clear(bank
);
381 if (retval
!= ERROR_OK
)
384 buffer
+= this_count
;
385 address
+= this_count
;
390 if (retval
== ERROR_OK
)
391 retval
= stm32lx_lock_program_memory(bank
);
393 target_free_working_area(target
, source
);
394 target_free_working_area(target
, write_algorithm
);
396 destroy_reg_param(®_params
[0]);
397 destroy_reg_param(®_params
[1]);
398 destroy_reg_param(®_params
[2]);
403 static int stm32lx_write(struct flash_bank
*bank
, uint8_t *buffer
,
404 uint32_t offset
, uint32_t count
)
406 struct target
*target
= bank
->target
;
408 uint32_t halfpages_number
;
409 uint32_t bytes_remaining
= 0;
410 uint32_t address
= bank
->base
+ offset
;
411 uint32_t bytes_written
= 0;
414 if (bank
->target
->state
!= TARGET_HALTED
) {
415 LOG_ERROR("Target not halted");
416 return ERROR_TARGET_NOT_HALTED
;
420 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
421 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
424 retval
= stm32lx_unlock_program_memory(bank
);
425 if (retval
!= ERROR_OK
)
428 /* first we need to write any unaligned head bytes upto
429 * the next 128 byte page */
432 bytes_remaining
= MIN(count
, 128 - (offset
% 128));
434 while (bytes_remaining
> 0) {
435 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
437 /* copy remaining bytes into the write buffer */
438 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
439 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
441 retval
= target_write_buffer(target
, address
, 4, value
);
442 if (retval
!= ERROR_OK
)
443 goto reset_pg_and_lock
;
445 bytes_written
+= bytes_to_write
;
446 bytes_remaining
-= bytes_to_write
;
449 retval
= stm32lx_wait_until_bsy_clear(bank
);
450 if (retval
!= ERROR_OK
)
451 goto reset_pg_and_lock
;
454 offset
+= bytes_written
;
455 count
-= bytes_written
;
457 /* this should always pass this check here */
458 assert((offset
% 128) == 0);
460 /* calculate half pages */
461 halfpages_number
= count
/ 128;
463 if (halfpages_number
) {
464 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, 128 * halfpages_number
);
465 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
466 /* attempt slow memory writes */
467 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
468 halfpages_number
= 0;
470 if (retval
!= ERROR_OK
)
475 /* write any remaining bytes */
476 uint32_t page_bytes_written
= 128 * halfpages_number
;
477 bytes_written
+= page_bytes_written
;
478 address
+= page_bytes_written
;
479 bytes_remaining
= count
- page_bytes_written
;
481 retval
= stm32lx_unlock_program_memory(bank
);
482 if (retval
!= ERROR_OK
)
485 while (bytes_remaining
> 0) {
486 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
488 /* copy remaining bytes into the write buffer */
489 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
490 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
492 retval
= target_write_buffer(target
, address
, 4, value
);
493 if (retval
!= ERROR_OK
)
494 goto reset_pg_and_lock
;
496 bytes_written
+= bytes_to_write
;
497 bytes_remaining
-= bytes_to_write
;
500 retval
= stm32lx_wait_until_bsy_clear(bank
);
501 if (retval
!= ERROR_OK
)
502 goto reset_pg_and_lock
;
506 retval2
= stm32lx_lock_program_memory(bank
);
507 if (retval
== ERROR_OK
)
513 static int stm32lx_probe(struct flash_bank
*bank
)
515 struct target
*target
= bank
->target
;
516 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
518 uint16_t flash_size_in_kb
;
519 uint16_t max_flash_size_in_kb
;
521 uint32_t base_address
= FLASH_BANK0_ADDRESS
;
522 uint32_t second_bank_base
;
523 uint32_t first_bank_size_in_kb
;
525 stm32lx_info
->probed
= 0;
527 /* read stm32 device id register */
528 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
529 if (retval
!= ERROR_OK
)
532 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
534 /* set max flash size depending on family */
535 switch (device_id
& 0xfff) {
537 max_flash_size_in_kb
= 128;
540 /* single bank, high density */
541 max_flash_size_in_kb
= 256;
544 /* According to ST, the devices with id 0x436 have dual bank flash and comes with
545 * a total flash size of 384k or 256kb. However, the first bank is always 192kb,
546 * and second one holds the rest. The reason is that the 256kb version is actually
547 * the same physical flash but only the first 256kb are verified.
549 max_flash_size_in_kb
= 384;
550 first_bank_size_in_kb
= 192;
551 stm32lx_info
->has_dual_banks
= true;
554 /* Dual bank, high density */
555 max_flash_size_in_kb
= 512;
556 first_bank_size_in_kb
= 192;
557 stm32lx_info
->has_dual_banks
= true;
560 LOG_WARNING("Cannot identify target as a STM32L family.");
564 /* Get the flash size from target. 0x427 and 0x436 devices use a
565 * different location for the Flash Size register, please see RM0038 r8 or
567 if ((device_id
& 0xfff) == 0x427 || (device_id
& 0xfff) == 0x436 ||
568 (device_id
& 0xfff) == 0x437)
569 retval
= target_read_u16(target
, F_SIZE_MP
, &flash_size_in_kb
);
571 retval
= target_read_u16(target
, F_SIZE
, &flash_size_in_kb
);
573 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
574 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
576 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x436) {
577 if (flash_size_in_kb
== 0)
578 flash_size_in_kb
= 384;
579 else if (flash_size_in_kb
== 1)
580 flash_size_in_kb
= 256;
583 /* Failed reading flash size or flash size invalid (early silicon),
584 * default to max target family */
585 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
586 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
587 max_flash_size_in_kb
);
588 flash_size_in_kb
= max_flash_size_in_kb
;
589 } else if (flash_size_in_kb
> max_flash_size_in_kb
) {
590 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
591 flash_size_in_kb
, max_flash_size_in_kb
, max_flash_size_in_kb
);
592 flash_size_in_kb
= max_flash_size_in_kb
;
595 if (stm32lx_info
->has_dual_banks
) {
596 /* Use the configured base address to determine if this is the first or second flash bank.
597 * Verify that the base address is reasonably correct and determine the flash bank size
599 second_bank_base
= base_address
+ first_bank_size_in_kb
* 1024;
600 if (bank
->base
== second_bank_base
) {
601 /* This is the second bank */
602 base_address
= second_bank_base
;
603 flash_size_in_kb
= flash_size_in_kb
- first_bank_size_in_kb
;
604 } else if (bank
->base
== 0 || bank
->base
== base_address
) {
605 /* This is the first bank */
606 flash_size_in_kb
= first_bank_size_in_kb
;
608 LOG_WARNING("STM32L flash bank base address config is incorrect."
609 " 0x%" PRIx32
" but should rather be 0x%" PRIx32
" or 0x%" PRIx32
,
610 bank
->base
, base_address
, second_bank_base
);
613 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32
,
614 bank
->bank_number
, flash_size_in_kb
, base_address
);
616 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32
, flash_size_in_kb
, base_address
);
619 /* if the user sets the size manually then ignore the probed value
620 * this allows us to work around devices that have a invalid flash size register value */
621 if (stm32lx_info
->user_bank_size
) {
622 flash_size_in_kb
= stm32lx_info
->user_bank_size
/ 1024;
623 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb
);
626 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
627 * 16 pages for a protection area */
629 /* calculate numbers of sectors (4kB per sector) */
630 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
634 bank
->sectors
= NULL
;
637 bank
->size
= flash_size_in_kb
* 1024;
638 bank
->base
= base_address
;
639 bank
->num_sectors
= num_sectors
;
640 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
641 if (bank
->sectors
== NULL
) {
642 LOG_ERROR("failed to allocate bank sectors");
646 for (i
= 0; i
< num_sectors
; i
++) {
647 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
648 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
649 bank
->sectors
[i
].is_erased
= -1;
650 bank
->sectors
[i
].is_protected
= 1;
653 stm32lx_info
->probed
= 1;
658 static int stm32lx_auto_probe(struct flash_bank
*bank
)
660 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
662 if (stm32lx_info
->probed
)
665 return stm32lx_probe(bank
);
668 static int stm32lx_erase_check(struct flash_bank
*bank
)
670 struct target
*target
= bank
->target
;
671 const int buffer_size
= 4096;
674 int retval
= ERROR_OK
;
676 if (bank
->target
->state
!= TARGET_HALTED
) {
677 LOG_ERROR("Target not halted");
678 return ERROR_TARGET_NOT_HALTED
;
681 uint8_t *buffer
= malloc(buffer_size
);
682 if (buffer
== NULL
) {
683 LOG_ERROR("failed to allocate read buffer");
687 for (i
= 0; i
< bank
->num_sectors
; i
++) {
689 bank
->sectors
[i
].is_erased
= 1;
691 /* Loop chunk by chunk over the sector */
692 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
) {
695 if (chunk
> (j
- bank
->sectors
[i
].size
))
696 chunk
= (j
- bank
->sectors
[i
].size
);
698 retval
= target_read_memory(target
, bank
->base
699 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
700 if (retval
!= ERROR_OK
)
703 for (nBytes
= 0; nBytes
< chunk
; nBytes
++) {
704 if (buffer
[nBytes
] != 0x00) {
705 bank
->sectors
[i
].is_erased
= 0;
710 if (retval
!= ERROR_OK
)
718 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
720 /* This method must return a string displaying information about the bank */
722 uint32_t dbgmcu_idcode
;
724 /* read stm32 device id register */
725 int retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE
, &dbgmcu_idcode
);
726 if (retval
!= ERROR_OK
)
729 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
730 uint16_t rev_id
= dbgmcu_idcode
>> 16;
731 const char *device_str
;
732 const char *rev_str
= NULL
;
736 device_str
= "STM32L1xx (Low/Medium Density)";
762 device_str
= "STM32L1xx (Medium+ Density)";
772 device_str
= "STM32L1xx (Medium+/High Density)";
790 device_str
= "STM32L1xx (Medium+/High Density)";
794 snprintf(buf
, buf_size
, "Cannot identify target as a STM32L1");
799 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
801 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
806 static const struct command_registration stm32lx_exec_command_handlers
[] = {
807 COMMAND_REGISTRATION_DONE
810 static const struct command_registration stm32lx_command_handlers
[] = {
814 .help
= "stm32lx flash command group",
816 .chain
= stm32lx_exec_command_handlers
,
818 COMMAND_REGISTRATION_DONE
821 struct flash_driver stm32lx_flash
= {
823 .commands
= stm32lx_command_handlers
,
824 .flash_bank_command
= stm32lx_flash_bank_command
,
825 .erase
= stm32lx_erase
,
826 .protect
= stm32lx_protect
,
827 .write
= stm32lx_write
,
828 .read
= default_flash_read
,
829 .probe
= stm32lx_probe
,
830 .auto_probe
= stm32lx_auto_probe
,
831 .erase_check
= stm32lx_erase_check
,
832 .protect_check
= stm32lx_protect_check
,
833 .info
= stm32lx_get_info
,
836 /* Static methods implementation */
837 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
839 struct target
*target
= bank
->target
;
844 * Unlocking the program memory is done by unlocking the PECR,
845 * then by writing the 2 PRGKEY to the PRGKEYR register
848 /* check flash is not already unlocked */
849 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
850 if (retval
!= ERROR_OK
)
853 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
856 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
857 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
858 if (retval
!= ERROR_OK
)
861 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
862 if (retval
!= ERROR_OK
)
865 /* Make sure it worked */
866 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
867 if (retval
!= ERROR_OK
)
870 if (reg32
& FLASH_PECR__PELOCK
) {
871 LOG_ERROR("PELOCK is not cleared :(");
872 return ERROR_FLASH_OPERATION_FAILED
;
875 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY1
);
876 if (retval
!= ERROR_OK
)
878 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY2
);
879 if (retval
!= ERROR_OK
)
882 /* Make sure it worked */
883 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
884 if (retval
!= ERROR_OK
)
887 if (reg32
& FLASH_PECR__PRGLOCK
) {
888 LOG_ERROR("PRGLOCK is not cleared :(");
889 return ERROR_FLASH_OPERATION_FAILED
;
895 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
897 struct target
*target
= bank
->target
;
902 * Unlock the program memory, then set the FPRG bit in the PECR register.
904 retval
= stm32lx_unlock_program_memory(bank
);
905 if (retval
!= ERROR_OK
)
908 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
909 if (retval
!= ERROR_OK
)
912 reg32
|= FLASH_PECR__FPRG
;
913 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
914 if (retval
!= ERROR_OK
)
917 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
918 if (retval
!= ERROR_OK
)
921 reg32
|= FLASH_PECR__PROG
;
922 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
927 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
929 struct target
*target
= bank
->target
;
933 /* To lock the program memory, simply set the lock bit and lock PECR */
935 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
936 if (retval
!= ERROR_OK
)
939 reg32
|= FLASH_PECR__PRGLOCK
;
940 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
941 if (retval
!= ERROR_OK
)
944 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
945 if (retval
!= ERROR_OK
)
948 reg32
|= FLASH_PECR__PELOCK
;
949 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
950 if (retval
!= ERROR_OK
)
956 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
958 struct target
*target
= bank
->target
;
963 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
964 * first unlock the memory, loop over the pages of this sector
965 * and write 0x0 to its first word.
968 retval
= stm32lx_unlock_program_memory(bank
);
969 if (retval
!= ERROR_OK
)
972 for (int page
= 0; page
< FLASH_PAGES_PER_SECTOR
; page
++) {
973 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
974 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
975 if (retval
!= ERROR_OK
)
978 retval
= stm32lx_wait_until_bsy_clear(bank
);
979 if (retval
!= ERROR_OK
)
982 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
984 retval
= target_write_u32(target
, addr
, 0x0);
985 if (retval
!= ERROR_OK
)
988 retval
= stm32lx_wait_until_bsy_clear(bank
);
989 if (retval
!= ERROR_OK
)
993 retval
= stm32lx_lock_program_memory(bank
);
994 if (retval
!= ERROR_OK
)
1000 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
1002 struct target
*target
= bank
->target
;
1004 int retval
= ERROR_OK
;
1007 /* wait for busy to clear */
1009 retval
= target_read_u32(target
, FLASH_SR
, &status
);
1010 if (retval
!= ERROR_OK
)
1013 if ((status
& FLASH_SR__BSY
) == 0)
1015 if (timeout
-- <= 0) {
1016 LOG_ERROR("timed out waiting for flash");
1022 if (status
& FLASH_SR__WRPERR
) {
1023 LOG_ERROR("access denied / write protected");
1024 retval
= ERROR_FAIL
;
1027 if (status
& FLASH_SR__PGAERR
) {
1028 LOG_ERROR("invalid program address");
1029 retval
= ERROR_FAIL
;
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