1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
32 #include <target/arm.h>
33 #include <helper/binarybuffer.h>
34 #include <target/algorithm.h>
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
48 /* FLASH_CR0 register bits */
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
62 /* FLASH_CR1 register bits */
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
77 /* FLASH_ER register bits */
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
88 struct str7x_flash_bank
{
89 uint32_t *sector_bits
;
92 uint32_t register_base
;
95 struct str7x_mem_layout
{
96 uint32_t sector_start
;
101 enum str7x_status_codes
{
102 STR7X_CMD_SUCCESS
= 0,
103 STR7X_INVALID_COMMAND
= 1,
104 STR7X_SRC_ADDR_ERROR
= 2,
105 STR7X_DST_ADDR_ERROR
= 3,
106 STR7X_SRC_ADDR_NOT_MAPPED
= 4,
107 STR7X_DST_ADDR_NOT_MAPPED
= 5,
108 STR7X_COUNT_ERROR
= 6,
109 STR7X_INVALID_SECTOR
= 7,
110 STR7X_SECTOR_NOT_BLANK
= 8,
111 STR7X_SECTOR_NOT_PREPARED
= 9,
112 STR7X_COMPARE_ERROR
= 10,
116 static const struct str7x_mem_layout mem_layout_str7bank0
[] = {
117 {0x00000000, 0x02000, 0x01},
118 {0x00002000, 0x02000, 0x02},
119 {0x00004000, 0x02000, 0x04},
120 {0x00006000, 0x02000, 0x08},
121 {0x00008000, 0x08000, 0x10},
122 {0x00010000, 0x10000, 0x20},
123 {0x00020000, 0x10000, 0x40},
124 {0x00030000, 0x10000, 0x80}
127 static const struct str7x_mem_layout mem_layout_str7bank1
[] = {
128 {0x00000000, 0x02000, 0x10000},
129 {0x00002000, 0x02000, 0x20000}
132 static int str7x_get_flash_adr(struct flash_bank
*bank
, uint32_t reg
)
134 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
135 return str7x_info
->register_base
| reg
;
138 static int str7x_build_block_list(struct flash_bank
*bank
)
140 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
144 int b0_sectors
= 0, b1_sectors
= 0;
146 switch (bank
->size
) {
160 LOG_ERROR("BUG: unknown bank->size encountered");
164 num_sectors
= b0_sectors
+ b1_sectors
;
166 bank
->num_sectors
= num_sectors
;
167 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
168 str7x_info
->sector_bits
= malloc(sizeof(uint32_t) * num_sectors
);
172 for (i
= 0; i
< b0_sectors
; i
++) {
173 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank0
[i
].sector_start
;
174 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank0
[i
].sector_size
;
175 bank
->sectors
[num_sectors
].is_erased
= -1;
176 /* the reset_init handler marks all the sectors unprotected,
177 * matching hardware after reset; keep the driver in sync
179 bank
->sectors
[num_sectors
].is_protected
= 0;
180 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank0
[i
].sector_bit
;
183 for (i
= 0; i
< b1_sectors
; i
++) {
184 bank
->sectors
[num_sectors
].offset
= mem_layout_str7bank1
[i
].sector_start
;
185 bank
->sectors
[num_sectors
].size
= mem_layout_str7bank1
[i
].sector_size
;
186 bank
->sectors
[num_sectors
].is_erased
= -1;
187 /* the reset_init handler marks all the sectors unprotected,
188 * matching hardware after reset; keep the driver in sync
190 bank
->sectors
[num_sectors
].is_protected
= 0;
191 str7x_info
->sector_bits
[num_sectors
++] = mem_layout_str7bank1
[i
].sector_bit
;
197 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
199 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command
)
201 struct str7x_flash_bank
*str7x_info
;
204 return ERROR_COMMAND_SYNTAX_ERROR
;
206 str7x_info
= malloc(sizeof(struct str7x_flash_bank
));
207 bank
->driver_priv
= str7x_info
;
209 /* set default bits for str71x flash */
210 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA1
| FLASH_BSYA0
);
211 str7x_info
->disable_bit
= (1 << 1);
213 if (strcmp(CMD_ARGV
[6], "STR71x") == 0)
214 str7x_info
->register_base
= 0x40100000;
215 else if (strcmp(CMD_ARGV
[6], "STR73x") == 0) {
216 str7x_info
->register_base
= 0x80100000;
217 str7x_info
->busy_bits
= (FLASH_LOCK
| FLASH_BSYA0
);
218 } else if (strcmp(CMD_ARGV
[6], "STR75x") == 0) {
219 str7x_info
->register_base
= 0x20100000;
220 str7x_info
->disable_bit
= (1 << 0);
222 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV
[6]);
224 return ERROR_FLASH_BANK_INVALID
;
227 str7x_build_block_list(bank
);
232 /* wait for flash to become idle or report errors.
234 FIX!!! what's the maximum timeout??? The documentation doesn't
235 state any maximum time.... by inspection it seems > 1000ms is to be
238 10000ms is long enough that it should cover anything, yet not
239 quite be equivalent to an infinite loop.
242 static int str7x_waitbusy(struct flash_bank
*bank
)
246 struct target
*target
= bank
->target
;
247 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
249 for (i
= 0 ; i
< 10000; i
++) {
251 err
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), &retval
);
255 if ((retval
& str7x_info
->busy_bits
) == 0)
260 LOG_ERROR("Timed out waiting for str7x flash");
265 static int str7x_result(struct flash_bank
*bank
)
267 struct target
*target
= bank
->target
;
268 uint32_t flash_flags
;
271 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), &flash_flags
);
272 if (retval
!= ERROR_OK
)
275 if (flash_flags
& FLASH_WPF
) {
276 LOG_ERROR("str7x hw write protection set");
279 if (flash_flags
& FLASH_RESER
) {
280 LOG_ERROR("str7x suspended program erase not resumed");
283 if (flash_flags
& FLASH_10ER
) {
284 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
287 if (flash_flags
& FLASH_PGER
) {
288 LOG_ERROR("str7x program error");
291 if (flash_flags
& FLASH_ERER
) {
292 LOG_ERROR("str7x erase error");
295 if (retval
== ERROR_OK
) {
296 if (flash_flags
& FLASH_ERR
) {
297 /* this should always be set if one of the others are set... */
298 LOG_ERROR("str7x write operation failed / bad setup");
306 static int str7x_protect_check(struct flash_bank
*bank
)
308 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
309 struct target
*target
= bank
->target
;
312 uint32_t flash_flags
;
314 if (bank
->target
->state
!= TARGET_HALTED
) {
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED
;
320 retval
= target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVWPAR
), &flash_flags
);
321 if (retval
!= ERROR_OK
)
324 for (i
= 0; i
< bank
->num_sectors
; i
++) {
325 if (flash_flags
& str7x_info
->sector_bits
[i
])
326 bank
->sectors
[i
].is_protected
= 0;
328 bank
->sectors
[i
].is_protected
= 1;
334 static int str7x_erase(struct flash_bank
*bank
, int first
, int last
)
336 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
337 struct target
*target
= bank
->target
;
341 uint32_t sectors
= 0;
344 if (bank
->target
->state
!= TARGET_HALTED
) {
345 LOG_ERROR("Target not halted");
346 return ERROR_TARGET_NOT_HALTED
;
349 for (i
= first
; i
<= last
; i
++)
350 sectors
|= str7x_info
->sector_bits
[i
];
352 LOG_DEBUG("sectors: 0x%" PRIx32
"", sectors
);
354 /* clear FLASH_ER register */
355 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
360 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
365 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR1
), cmd
);
369 cmd
= FLASH_SER
| FLASH_WMS
;
370 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
374 err
= str7x_waitbusy(bank
);
378 err
= str7x_result(bank
);
382 for (i
= first
; i
<= last
; i
++)
383 bank
->sectors
[i
].is_erased
= 1;
388 static int str7x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
390 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
391 struct target
*target
= bank
->target
;
394 uint32_t protect_blocks
;
396 if (bank
->target
->state
!= TARGET_HALTED
) {
397 LOG_ERROR("Target not halted");
398 return ERROR_TARGET_NOT_HALTED
;
401 protect_blocks
= 0xFFFFFFFF;
404 for (i
= first
; i
<= last
; i
++)
405 protect_blocks
&= ~(str7x_info
->sector_bits
[i
]);
408 /* clear FLASH_ER register */
410 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
415 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
419 cmd
= str7x_get_flash_adr(bank
, FLASH_NVWPAR
);
420 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), cmd
);
424 cmd
= protect_blocks
;
425 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), cmd
);
429 cmd
= FLASH_SPR
| FLASH_WMS
;
430 err
= target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
434 err
= str7x_waitbusy(bank
);
438 err
= str7x_result(bank
);
445 static int str7x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
446 uint32_t offset
, uint32_t count
)
448 struct str7x_flash_bank
*str7x_info
= bank
->driver_priv
;
449 struct target
*target
= bank
->target
;
450 uint32_t buffer_size
= 32768;
451 struct working_area
*write_algorithm
;
452 struct working_area
*source
;
453 uint32_t address
= bank
->base
+ offset
;
454 struct reg_param reg_params
[6];
455 struct arm_algorithm arm_algo
;
456 int retval
= ERROR_OK
;
458 /* see contib/loaders/flash/str7x.s for src */
460 static const uint32_t str7x_flash_write_code
[] = {
462 0xe3a04201, /* mov r4, #0x10000000 */
463 0xe5824000, /* str r4, [r2, #0x0] */
464 0xe5821010, /* str r1, [r2, #0x10] */
465 0xe4904004, /* ldr r4, [r0], #4 */
466 0xe5824008, /* str r4, [r2, #0x8] */
467 0xe4904004, /* ldr r4, [r0], #4 */
468 0xe582400c, /* str r4, [r2, #0xc] */
469 0xe3a04209, /* mov r4, #0x90000000 */
470 0xe5824000, /* str r4, [r2, #0x0] */
472 0xe5924000, /* ldr r4, [r2, #0x0] */
473 0xe1140005, /* tst r4, r5 */
474 0x1afffffc, /* bne busy */
475 0xe5924014, /* ldr r4, [r2, #0x14] */
476 0xe31400ff, /* tst r4, #0xff */
477 0x03140c01, /* tsteq r4, #0x100 */
478 0x1a000002, /* bne exit */
479 0xe2811008, /* add r1, r1, #0x8 */
480 0xe2533001, /* subs r3, r3, #1 */
481 0x1affffec, /* bne write */
483 0xeafffffe, /* b exit */
486 /* flash write code */
487 if (target_alloc_working_area_try(target
, sizeof(str7x_flash_write_code
),
488 &write_algorithm
) != ERROR_OK
) {
489 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
492 uint8_t code
[sizeof(str7x_flash_write_code
)];
493 target_buffer_set_u32_array(target
, code
, ARRAY_SIZE(str7x_flash_write_code
),
494 str7x_flash_write_code
);
495 target_write_buffer(target
, write_algorithm
->address
, sizeof(code
), code
);
498 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
500 if (buffer_size
<= 256) {
501 /* we already allocated the writing code, but failed to get a
502 * buffer, free the algorithm */
503 target_free_working_area(target
, write_algorithm
);
505 LOG_WARNING("no large enough working area available, can't do block memory writes");
506 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
510 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
511 arm_algo
.core_mode
= ARM_MODE_SVC
;
512 arm_algo
.core_state
= ARM_STATE_ARM
;
514 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
515 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
516 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
517 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
518 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
519 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
522 uint32_t thisrun_count
= (count
> (buffer_size
/ 8)) ? (buffer_size
/ 8) : count
;
524 target_write_buffer(target
, source
->address
, thisrun_count
* 8, buffer
);
526 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
527 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
528 buf_set_u32(reg_params
[2].value
, 0, 32, str7x_get_flash_adr(bank
, FLASH_CR0
));
529 buf_set_u32(reg_params
[3].value
, 0, 32, thisrun_count
);
530 buf_set_u32(reg_params
[5].value
, 0, 32, str7x_info
->busy_bits
);
532 retval
= target_run_algorithm(target
, 0, NULL
, 6, reg_params
,
533 write_algorithm
->address
,
534 write_algorithm
->address
+ (sizeof(str7x_flash_write_code
) - 4),
536 if (retval
!= ERROR_OK
)
539 if (buf_get_u32(reg_params
[4].value
, 0, 32) != 0x00) {
540 retval
= str7x_result(bank
);
544 buffer
+= thisrun_count
* 8;
545 address
+= thisrun_count
* 8;
546 count
-= thisrun_count
;
549 target_free_working_area(target
, source
);
550 target_free_working_area(target
, write_algorithm
);
552 destroy_reg_param(®_params
[0]);
553 destroy_reg_param(®_params
[1]);
554 destroy_reg_param(®_params
[2]);
555 destroy_reg_param(®_params
[3]);
556 destroy_reg_param(®_params
[4]);
557 destroy_reg_param(®_params
[5]);
562 static int str7x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
563 uint32_t offset
, uint32_t count
)
565 struct target
*target
= bank
->target
;
566 uint32_t dwords_remaining
= (count
/ 8);
567 uint32_t bytes_remaining
= (count
& 0x00000007);
568 uint32_t address
= bank
->base
+ offset
;
569 uint32_t bytes_written
= 0;
572 uint32_t check_address
= offset
;
575 if (bank
->target
->state
!= TARGET_HALTED
) {
576 LOG_ERROR("Target not halted");
577 return ERROR_TARGET_NOT_HALTED
;
581 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment", offset
);
582 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
585 for (i
= 0; i
< bank
->num_sectors
; i
++) {
586 uint32_t sec_start
= bank
->sectors
[i
].offset
;
587 uint32_t sec_end
= sec_start
+ bank
->sectors
[i
].size
;
589 /* check if destination falls within the current sector */
590 if ((check_address
>= sec_start
) && (check_address
< sec_end
)) {
591 /* check if destination ends in the current sector */
592 if (offset
+ count
< sec_end
)
593 check_address
= offset
+ count
;
595 check_address
= sec_end
;
599 if (check_address
!= offset
+ count
)
600 return ERROR_FLASH_DST_OUT_OF_BANK
;
602 /* clear FLASH_ER register */
603 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_ER
), 0x0);
605 /* multiple dwords (8-byte) to be programmed? */
606 if (dwords_remaining
> 0) {
607 /* try using a block write */
608 retval
= str7x_write_block(bank
, buffer
, offset
, dwords_remaining
);
609 if (retval
!= ERROR_OK
) {
610 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
611 /* if block write failed (no sufficient working area),
612 * we use normal (slow) single dword accesses */
613 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
618 buffer
+= dwords_remaining
* 8;
619 address
+= dwords_remaining
* 8;
620 dwords_remaining
= 0;
624 while (dwords_remaining
> 0) {
627 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
630 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
633 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
634 4, 1, buffer
+ bytes_written
);
638 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
639 4, 1, buffer
+ bytes_written
);
642 /* start programming cycle */
643 cmd
= FLASH_DWPG
| FLASH_WMS
;
644 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
647 err
= str7x_waitbusy(bank
);
651 err
= str7x_result(bank
);
659 if (bytes_remaining
) {
660 uint8_t last_dword
[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
662 /* copy the last remaining bytes into the write buffer */
663 memcpy(last_dword
, buffer
+bytes_written
, bytes_remaining
);
667 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
670 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), address
);
673 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
677 target_write_memory(target
, str7x_get_flash_adr(bank
, FLASH_DR1
),
678 4, 1, last_dword
+ 4);
680 /* start programming cycle */
681 cmd
= FLASH_DWPG
| FLASH_WMS
;
682 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), cmd
);
685 err
= str7x_waitbusy(bank
);
689 err
= str7x_result(bank
);
697 static int str7x_probe(struct flash_bank
*bank
)
703 COMMAND_HANDLER(str7x_handle_part_id_command
)
709 static int get_str7x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
711 /* Setting the write protection on a sector is a permanent change but it
712 * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
713 * protection state of the sectors, not the temporary.
715 snprintf(buf
, buf_size
, "STR7x flash protection info is only valid after a power cycle, "
716 "clearing the protection is only temporary and may not be reflected in the current "
721 COMMAND_HANDLER(str7x_handle_disable_jtag_command
)
723 struct target
*target
= NULL
;
724 struct str7x_flash_bank
*str7x_info
= NULL
;
727 uint16_t ProtectionLevel
= 0;
728 uint16_t ProtectionRegs
;
731 return ERROR_COMMAND_SYNTAX_ERROR
;
733 struct flash_bank
*bank
;
734 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
735 if (ERROR_OK
!= retval
)
738 str7x_info
= bank
->driver_priv
;
740 target
= bank
->target
;
742 if (target
->state
!= TARGET_HALTED
) {
743 LOG_ERROR("Target not halted");
744 return ERROR_TARGET_NOT_HALTED
;
747 /* first we get protection status */
749 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR0
), ®
);
751 if (!(reg
& str7x_info
->disable_bit
))
754 target_read_u32(target
, str7x_get_flash_adr(bank
, FLASH_NVAPR1
), ®
);
755 ProtectionRegs
= ~(reg
>> 16);
757 while (((ProtectionRegs
) != 0) && (ProtectionLevel
< 16)) {
758 ProtectionRegs
>>= 1;
762 if (ProtectionLevel
== 0) {
763 flash_cmd
= FLASH_SPR
;
764 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
765 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFB8);
766 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
), 0xFFFFFFFD);
767 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
768 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
770 flash_cmd
= FLASH_SPR
;
771 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
772 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_AR
), 0x4010DFBC);
773 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_DR0
),
774 ~(1 << (15 + ProtectionLevel
)));
775 flash_cmd
= FLASH_SPR
| FLASH_WMS
;
776 target_write_u32(target
, str7x_get_flash_adr(bank
, FLASH_CR0
), flash_cmd
);
782 static const struct command_registration str7x_exec_command_handlers
[] = {
784 .name
= "disable_jtag",
786 .handler
= str7x_handle_disable_jtag_command
,
787 .mode
= COMMAND_EXEC
,
788 .help
= "disable jtag access",
790 COMMAND_REGISTRATION_DONE
793 static const struct command_registration str7x_command_handlers
[] = {
797 .help
= "str7x flash command group",
799 .chain
= str7x_exec_command_handlers
,
801 COMMAND_REGISTRATION_DONE
804 struct flash_driver str7x_flash
= {
806 .commands
= str7x_command_handlers
,
807 .flash_bank_command
= str7x_flash_bank_command
,
808 .erase
= str7x_erase
,
809 .protect
= str7x_protect
,
810 .write
= str7x_write
,
811 .read
= default_flash_read
,
812 .probe
= str7x_probe
,
813 .auto_probe
= str7x_probe
,
814 .erase_check
= default_flash_blank_check
,
815 .protect_check
= str7x_protect_check
,
816 .info
= get_str7x_info
,
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