1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_auto_probe(struct flash_bank_s
*bank
);
44 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int stm32x_protect_check(struct flash_bank_s
*bank
);
46 int stm32x_erase_check(struct flash_bank_s
*bank
);
47 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
49 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 flash_driver_t stm32x_flash
=
58 .register_commands
= stm32x_register_commands
,
59 .flash_bank_command
= stm32x_flash_bank_command
,
60 .erase
= stm32x_erase
,
61 .protect
= stm32x_protect
,
62 .write
= stm32x_write
,
63 .probe
= stm32x_probe
,
64 .auto_probe
= stm32x_auto_probe
,
65 .erase_check
= stm32x_erase_check
,
66 .protect_check
= stm32x_protect_check
,
70 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
72 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
74 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
76 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
77 "unlock protected device");
78 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
80 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
81 "read device option bytes");
82 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
83 "write device option bytes");
87 /* flash bank stm32x <base> <size> 0 0 <target#>
89 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
91 stm32x_flash_bank_t
*stm32x_info
;
95 WARNING("incomplete flash_bank stm32x configuration");
96 return ERROR_FLASH_BANK_INVALID
;
99 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
100 bank
->driver_priv
= stm32x_info
;
102 stm32x_info
->write_algorithm
= NULL
;
103 stm32x_info
->probed
= 0;
108 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
110 target_t
*target
= bank
->target
;
113 target_read_u32(target
, STM32_FLASH_SR
, &status
);
118 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
122 /* wait for busy to clear */
123 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
125 DEBUG("status: 0x%x", status
);
132 int stm32x_read_options(struct flash_bank_s
*bank
)
135 stm32x_flash_bank_t
*stm32x_info
= NULL
;
136 target_t
*target
= bank
->target
;
138 stm32x_info
= bank
->driver_priv
;
140 /* read current option bytes */
141 target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
143 stm32x_info
->option_bytes
.user_options
= (u16
)0xFFF8|((optiondata
>> 2) & 0x07);
144 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
146 if (optiondata
& (1 << OPT_READOUT
))
147 INFO("Device Security Bit Set");
149 /* each bit refers to a 4bank protection */
150 target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
152 stm32x_info
->option_bytes
.protection
[0] = (u16
)optiondata
;
153 stm32x_info
->option_bytes
.protection
[1] = (u16
)(optiondata
>> 8);
154 stm32x_info
->option_bytes
.protection
[2] = (u16
)(optiondata
>> 16);
155 stm32x_info
->option_bytes
.protection
[3] = (u16
)(optiondata
>> 24);
160 int stm32x_erase_options(struct flash_bank_s
*bank
)
162 stm32x_flash_bank_t
*stm32x_info
= NULL
;
163 target_t
*target
= bank
->target
;
166 stm32x_info
= bank
->driver_priv
;
168 /* read current options */
169 stm32x_read_options(bank
);
171 /* unlock flash registers */
172 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
173 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
175 /* unlock option flash registers */
176 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
177 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
179 /* erase option bytes */
180 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
181 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
183 status
= stm32x_wait_status_busy(bank
, 10);
185 if( status
& FLASH_WRPRTERR
)
186 return ERROR_FLASH_OPERATION_FAILED
;
187 if( status
& FLASH_PGERR
)
188 return ERROR_FLASH_OPERATION_FAILED
;
190 /* clear readout protection and complementary option bytes
191 * this will also force a device unlock if set */
192 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
197 int stm32x_write_options(struct flash_bank_s
*bank
)
199 stm32x_flash_bank_t
*stm32x_info
= NULL
;
200 target_t
*target
= bank
->target
;
203 stm32x_info
= bank
->driver_priv
;
205 /* unlock flash registers */
206 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
207 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
209 /* unlock option flash registers */
210 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
211 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
213 /* program option bytes */
214 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
216 /* write user option byte */
217 target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
219 status
= stm32x_wait_status_busy(bank
, 10);
221 if( status
& FLASH_WRPRTERR
)
222 return ERROR_FLASH_OPERATION_FAILED
;
223 if( status
& FLASH_PGERR
)
224 return ERROR_FLASH_OPERATION_FAILED
;
226 /* write protection byte 1 */
227 target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
229 status
= stm32x_wait_status_busy(bank
, 10);
231 if( status
& FLASH_WRPRTERR
)
232 return ERROR_FLASH_OPERATION_FAILED
;
233 if( status
& FLASH_PGERR
)
234 return ERROR_FLASH_OPERATION_FAILED
;
236 /* write protection byte 2 */
237 target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
239 status
= stm32x_wait_status_busy(bank
, 10);
241 if( status
& FLASH_WRPRTERR
)
242 return ERROR_FLASH_OPERATION_FAILED
;
243 if( status
& FLASH_PGERR
)
244 return ERROR_FLASH_OPERATION_FAILED
;
246 /* write protection byte 3 */
247 target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
249 status
= stm32x_wait_status_busy(bank
, 10);
251 if( status
& FLASH_WRPRTERR
)
252 return ERROR_FLASH_OPERATION_FAILED
;
253 if( status
& FLASH_PGERR
)
254 return ERROR_FLASH_OPERATION_FAILED
;
256 /* write protection byte 4 */
257 target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
259 status
= stm32x_wait_status_busy(bank
, 10);
261 if( status
& FLASH_WRPRTERR
)
262 return ERROR_FLASH_OPERATION_FAILED
;
263 if( status
& FLASH_PGERR
)
264 return ERROR_FLASH_OPERATION_FAILED
;
266 /* write readout protection bit */
267 target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
269 status
= stm32x_wait_status_busy(bank
, 10);
271 if( status
& FLASH_WRPRTERR
)
272 return ERROR_FLASH_OPERATION_FAILED
;
273 if( status
& FLASH_PGERR
)
274 return ERROR_FLASH_OPERATION_FAILED
;
276 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
281 int stm32x_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
283 target_t
*target
= bank
->target
;
288 if ((first
< 0) || (last
> bank
->num_sectors
))
289 return ERROR_FLASH_SECTOR_INVALID
;
291 if (target
->state
!= TARGET_HALTED
)
293 return ERROR_TARGET_NOT_HALTED
;
296 buffer
= malloc(256);
298 for (i
= first
; i
<= last
; i
++)
300 bank
->sectors
[i
].is_erased
= 1;
302 target
->type
->read_memory(target
, bank
->base
+ bank
->sectors
[i
].offset
, 4, 256/4, buffer
);
304 for (nBytes
= 0; nBytes
< 256; nBytes
++)
306 if (buffer
[nBytes
] != 0xFF)
308 bank
->sectors
[i
].is_erased
= 0;
319 int stm32x_protect_check(struct flash_bank_s
*bank
)
321 target_t
*target
= bank
->target
;
327 if (target
->state
!= TARGET_HALTED
)
329 return ERROR_TARGET_NOT_HALTED
;
332 /* each bit refers to a 4bank protection */
333 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
335 /* each protection bit is for 4 1K pages */
336 num_bits
= (bank
->num_sectors
/ 4);
338 for (i
= 0; i
< num_bits
; i
++)
342 if( protection
& (1 << i
))
345 for (s
= 0; s
< 4; s
++)
346 bank
->sectors
[(i
* 4) + s
].is_protected
= set
;
352 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
354 target_t
*target
= bank
->target
;
359 /* unlock flash registers */
360 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
361 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
363 for (i
= first
; i
<= last
; i
++)
365 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
366 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
367 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
369 status
= stm32x_wait_status_busy(bank
, 10);
371 if( status
& FLASH_WRPRTERR
)
372 return ERROR_FLASH_OPERATION_FAILED
;
373 if( status
& FLASH_PGERR
)
374 return ERROR_FLASH_OPERATION_FAILED
;
375 bank
->sectors
[i
].is_erased
= 1;
378 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
383 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
385 stm32x_flash_bank_t
*stm32x_info
= NULL
;
386 target_t
*target
= bank
->target
;
387 u16 prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
392 stm32x_info
= bank
->driver_priv
;
394 if (target
->state
!= TARGET_HALTED
)
396 return ERROR_TARGET_NOT_HALTED
;
399 if ((first
&& (first
% 4)) || ((last
+ 1) && (last
+ 1) % 4))
401 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
402 return ERROR_FLASH_SECTOR_INVALID
;
405 /* each bit refers to a 4bank protection */
406 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
408 prot_reg
[0] = (u16
)protection
;
409 prot_reg
[1] = (u16
)(protection
>> 8);
410 prot_reg
[2] = (u16
)(protection
>> 16);
411 prot_reg
[3] = (u16
)(protection
>> 24);
413 for (i
= first
; i
<= last
; i
++)
416 bit
= (i
/ 4) - (reg
* 8);
419 prot_reg
[reg
] &= ~(1 << bit
);
421 prot_reg
[reg
] |= (1 << bit
);
424 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
427 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
428 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
429 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
430 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
432 return stm32x_write_options(bank
);
435 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
437 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
438 target_t
*target
= bank
->target
;
439 u32 buffer_size
= 8192;
440 working_area_t
*source
;
441 u32 address
= bank
->base
+ offset
;
442 reg_param_t reg_params
[4];
443 armv7m_algorithm_t armv7m_info
;
444 int retval
= ERROR_OK
;
446 u8 stm32x_flash_write_code
[] = {
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
451 0x23, 0x60, /* str r3, [r4, #0] */
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
457 0xFB, 0xD0, /* beq busy */
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
459 0x01, 0xD1, /* bne exit */
460 0x01, 0x3A, /* subs r2, r2, #1 */
461 0xED, 0xD1, /* bne write */
463 0xFE, 0xE7, /* b exit */
464 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
465 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
468 /* flash write code */
469 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
471 WARNING("no working area available, can't do block memory writes");
472 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
475 target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
478 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
481 if (buffer_size
<= 256)
483 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
484 if (stm32x_info
->write_algorithm
)
485 target_free_working_area(target
, stm32x_info
->write_algorithm
);
487 WARNING("no large enough working area available, can't do block memory writes");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
492 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
493 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
494 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
496 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
497 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
498 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
499 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
503 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
505 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
507 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
508 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
509 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
511 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, stm32x_info
->write_algorithm
->address
, \
512 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
514 ERROR("error executing str7x flash write algorithm");
518 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
520 retval
= ERROR_FLASH_OPERATION_FAILED
;
524 buffer
+= thisrun_count
* 2;
525 address
+= thisrun_count
* 2;
526 count
-= thisrun_count
;
529 target_free_working_area(target
, source
);
530 target_free_working_area(target
, stm32x_info
->write_algorithm
);
532 destroy_reg_param(®_params
[0]);
533 destroy_reg_param(®_params
[1]);
534 destroy_reg_param(®_params
[2]);
535 destroy_reg_param(®_params
[3]);
540 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
542 target_t
*target
= bank
->target
;
543 u32 words_remaining
= (count
/ 2);
544 u32 bytes_remaining
= (count
& 0x00000001);
545 u32 address
= bank
->base
+ offset
;
546 u32 bytes_written
= 0;
552 WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
556 /* unlock flash registers */
557 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
558 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
560 /* multiple half words (2-byte) to be programmed? */
561 if (words_remaining
> 0)
563 /* try using a block write */
564 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
566 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
568 /* if block write failed (no sufficient working area),
569 * we use normal (slow) single dword accesses */
570 WARNING("couldn't use block writes, falling back to single memory accesses");
572 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
574 ERROR("flash writing failed with error code: 0x%x", retval
);
575 return ERROR_FLASH_OPERATION_FAILED
;
580 buffer
+= words_remaining
* 2;
581 address
+= words_remaining
* 2;
586 while (words_remaining
> 0)
588 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
589 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
591 status
= stm32x_wait_status_busy(bank
, 5);
593 if( status
& FLASH_WRPRTERR
)
594 return ERROR_FLASH_OPERATION_FAILED
;
595 if( status
& FLASH_PGERR
)
596 return ERROR_FLASH_OPERATION_FAILED
;
605 u8 last_halfword
[2] = {0xff, 0xff};
608 while(bytes_remaining
> 0)
610 last_halfword
[i
++] = *(buffer
+ bytes_written
);
615 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
616 target_write_u16(target
, address
, *(u16
*)last_halfword
);
618 status
= stm32x_wait_status_busy(bank
, 5);
620 if( status
& FLASH_WRPRTERR
)
621 return ERROR_FLASH_OPERATION_FAILED
;
622 if( status
& FLASH_PGERR
)
623 return ERROR_FLASH_OPERATION_FAILED
;
626 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
631 int stm32x_probe(struct flash_bank_s
*bank
)
633 target_t
*target
= bank
->target
;
634 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
639 stm32x_info
->probed
= 0;
641 /* read stm32 device id register */
642 target_read_u32(target
, 0xE0042000, &device_id
);
643 INFO( "device id = 0x%08x", device_id
);
645 if (!(device_id
& 0x410))
647 WARNING( "Cannot identify target as a STM32 family." );
648 return ERROR_FLASH_OPERATION_FAILED
;
651 /* get flash size from target */
652 target_read_u16(target
, 0x1FFFF7E0, &num_sectors
);
654 /* check for early silicon rev A */
655 if ((device_id
>> 16) == 0 )
657 /* number of sectors incorrect on revA */
658 WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
662 INFO( "flash size = %dkbytes", num_sectors
);
664 bank
->base
= 0x08000000;
665 bank
->size
= num_sectors
* 1024;
666 bank
->num_sectors
= num_sectors
;
667 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
669 for (i
= 0; i
< num_sectors
; i
++)
671 bank
->sectors
[i
].offset
= i
* 1024;
672 bank
->sectors
[i
].size
= 1024;
673 bank
->sectors
[i
].is_erased
= -1;
674 bank
->sectors
[i
].is_protected
= 1;
677 stm32x_info
->probed
= 1;
682 int stm32x_auto_probe(struct flash_bank_s
*bank
)
684 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
685 if (stm32x_info
->probed
)
687 return stm32x_probe(bank
);
690 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
695 int stm32x_erase_check(struct flash_bank_s
*bank
)
697 return stm32x_blank_check(bank
, 0, bank
->num_sectors
- 1);
700 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
702 snprintf(buf
, buf_size
, "stm32x flash driver info" );
706 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
709 target_t
*target
= NULL
;
710 stm32x_flash_bank_t
*stm32x_info
= NULL
;
714 command_print(cmd_ctx
, "stm32x lock <bank>");
718 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
721 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
725 stm32x_info
= bank
->driver_priv
;
727 target
= bank
->target
;
729 if (target
->state
!= TARGET_HALTED
)
731 return ERROR_TARGET_NOT_HALTED
;
734 if (stm32x_erase_options(bank
) != ERROR_OK
)
736 command_print(cmd_ctx
, "stm32x failed to erase options");
740 /* set readout protection */
741 stm32x_info
->option_bytes
.RDP
= 0;
743 if (stm32x_write_options(bank
) != ERROR_OK
)
745 command_print(cmd_ctx
, "stm32x failed to lock device");
749 command_print(cmd_ctx
, "stm32x locked");
754 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
757 target_t
*target
= NULL
;
758 stm32x_flash_bank_t
*stm32x_info
= NULL
;
762 command_print(cmd_ctx
, "stm32x unlock <bank>");
766 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
769 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
773 stm32x_info
= bank
->driver_priv
;
775 target
= bank
->target
;
777 if (target
->state
!= TARGET_HALTED
)
779 return ERROR_TARGET_NOT_HALTED
;
782 if (stm32x_erase_options(bank
) != ERROR_OK
)
784 command_print(cmd_ctx
, "stm32x failed to unlock device");
788 if (stm32x_write_options(bank
) != ERROR_OK
)
790 command_print(cmd_ctx
, "stm32x failed to lock device");
794 command_print(cmd_ctx
, "stm32x unlocked");
799 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
803 target_t
*target
= NULL
;
804 stm32x_flash_bank_t
*stm32x_info
= NULL
;
808 command_print(cmd_ctx
, "stm32x options_read <bank>");
812 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
815 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
819 stm32x_info
= bank
->driver_priv
;
821 target
= bank
->target
;
823 if (target
->state
!= TARGET_HALTED
)
825 return ERROR_TARGET_NOT_HALTED
;
828 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
829 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
831 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
832 command_print(cmd_ctx
, "Option Byte Complement Error");
834 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
835 command_print(cmd_ctx
, "Readout Protection On");
837 command_print(cmd_ctx
, "Readout Protection Off");
839 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
840 command_print(cmd_ctx
, "Software Watchdog");
842 command_print(cmd_ctx
, "Hardware Watchdog");
844 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
845 command_print(cmd_ctx
, "Stop: No reset generated");
847 command_print(cmd_ctx
, "Stop: Reset generated");
849 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
850 command_print(cmd_ctx
, "Standby: No reset generated");
852 command_print(cmd_ctx
, "Standby: Reset generated");
857 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
860 target_t
*target
= NULL
;
861 stm32x_flash_bank_t
*stm32x_info
= NULL
;
862 u16 optionbyte
= 0xF8;
866 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
870 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
873 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
877 stm32x_info
= bank
->driver_priv
;
879 target
= bank
->target
;
881 if (target
->state
!= TARGET_HALTED
)
883 return ERROR_TARGET_NOT_HALTED
;
886 if (strcmp(args
[1], "SWWDG") == 0)
888 optionbyte
|= (1<<0);
892 optionbyte
&= ~(1<<0);
895 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
897 optionbyte
|= (1<<1);
901 optionbyte
&= ~(1<<1);
904 if (strcmp(args
[3], "NORSTSTOP") == 0)
906 optionbyte
|= (1<<2);
910 optionbyte
&= ~(1<<2);
913 if (stm32x_erase_options(bank
) != ERROR_OK
)
915 command_print(cmd_ctx
, "stm32x failed to erase options");
919 stm32x_info
->option_bytes
.user_options
= optionbyte
;
921 if (stm32x_write_options(bank
) != ERROR_OK
)
923 command_print(cmd_ctx
, "stm32x failed to write options");
927 command_print(cmd_ctx
, "stm32x write options complete");
932 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
934 target_t
*target
= NULL
;
935 stm32x_flash_bank_t
*stm32x_info
= NULL
;
941 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
945 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
948 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
952 stm32x_info
= bank
->driver_priv
;
954 target
= bank
->target
;
956 if (target
->state
!= TARGET_HALTED
)
958 return ERROR_TARGET_NOT_HALTED
;
961 /* unlock option flash registers */
962 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
963 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
965 /* mass erase flash memory */
966 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
967 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
969 status
= stm32x_wait_status_busy(bank
, 10);
971 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
973 if( status
& FLASH_WRPRTERR
)
975 command_print(cmd_ctx
, "stm32x device protected");
979 if( status
& FLASH_PGERR
)
981 command_print(cmd_ctx
, "stm32x device programming failed");
985 command_print(cmd_ctx
, "stm32x mass erase complete");
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