1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
45 static u8 output_value
= 0x0;
46 static int dev_mem_fd
;
47 static void *gpio_controller
;
48 static volatile u8
*gpio_data_register
;
49 static volatile u8
*gpio_data_direction_register
;
51 /* low level command set
53 int ep93xx_read(void);
54 void ep93xx_write(int tck
, int tms
, int tdi
);
55 void ep93xx_reset(int trst
, int srst
);
57 int ep93xx_speed(int speed
);
58 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
);
59 int ep93xx_init(void);
60 int ep93xx_quit(void);
62 struct timespec ep93xx_zzzz
;
64 jtag_interface_t ep93xx_interface
=
68 .execute_queue
= bitbang_execute_queue
,
70 .support_statemove
= 0,
72 .speed
= ep93xx_speed
,
73 .register_commands
= ep93xx_register_commands
,
78 bitbang_interface_t ep93xx_bitbang
=
81 .write
= ep93xx_write
,
87 return !!(*gpio_data_register
& TDO_BIT
);
90 void ep93xx_write(int tck
, int tms
, int tdi
)
93 output_value
|= TCK_BIT
;
95 output_value
&= TCK_BIT
;
98 output_value
|= TMS_BIT
;
100 output_value
&= TMS_BIT
;
103 output_value
|= TDI_BIT
;
105 output_value
&= TDI_BIT
;
107 *gpio_data_register
= output_value
;
108 nanosleep(ep93xx_zzzz
);
111 /* (1) assert or (0) deassert reset lines */
112 void ep93xx_reset(int trst
, int srst
)
115 output_value
|= TRST_BIT
;
117 output_value
&= TRST_BIT
;
120 output_value
|= SRST_BIT
;
122 output_value
&= SRST_BIT
;
124 *gpio_data_register
= output_value
;
125 nanosleep(ep93xx_zzzz
);
128 int ep93xx_speed(int speed
)
134 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
)
140 static int set_gonk_mode(void)
145 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
146 MAP_SHARED
, dev_mem_fd
, 0x80930000);
147 if (syscon
== MAP_FAILED
) {
149 return ERROR_JTAG_INIT_FAILED
;
152 devicecfg
= *((volatile int *)(syscon
+ 0x80));
153 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
154 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
156 munmap(syscon
, 4096);
161 int ep93xx_init(void)
165 bitbang_interface
= &ep93xx_bitbang
;
167 ep93xx_zzzz
.tv_sec
= 0;
168 ep93xx_zzzz
.tv_nsec
= 10000000;
170 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
171 if (dev_mem_fd
< 0) {
173 return ERROR_JTAG_INIT_FAILED
;
176 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
177 MAP_SHARED
, dev_mem_fd
, 0x80840000);
178 if (gpio_controller
== MAP_FAILED
) {
181 return ERROR_JTAG_INIT_FAILED
;
184 ret
= set_gonk_mode();
185 if (ret
!= ERROR_OK
) {
186 munmap(gpio_controller
, 4096);
192 /* Use GPIO port A. */
193 gpio_data_register
= gpio_controller
+ 0x00;
194 gpio_data_direction_register
= gpio_controller
+ 0x10;
197 /* Use GPIO port B. */
198 gpio_data_register
= gpio_controller
+ 0x04;
199 gpio_data_direction_register
= gpio_controller
+ 0x14;
201 /* Use GPIO port C. */
202 gpio_data_register
= gpio_controller
+ 0x08;
203 gpio_data_direction_register
= gpio_controller
+ 0x18;
205 /* Use GPIO port D. */
206 gpio_data_register
= gpio_controller
+ 0x0c;
207 gpio_data_direction_register
= gpio_controller
+ 0x1c;
210 /* Use GPIO port C. */
211 gpio_data_register
= gpio_controller
+ 0x08;
212 gpio_data_direction_register
= gpio_controller
+ 0x18;
214 printf("gpio_data_register = %08x\n", gpio_data_register
);
215 printf("gpio_data_direction_reg = %08x\n", gpio_data_direction_register
);
217 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
218 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
219 * TMS/TRST/SRST high.
221 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
222 *gpio_data_register
= output_value
;
223 nanosleep(ep93xx_zzzz
);
226 * Configure the direction register. 1 = output, 0 = input.
228 *gpio_data_direction_register
=
229 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
231 nanosleep(ep93xx_zzzz
);
235 int ep93xx_quit(void)
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