1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm720t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 /* forward declarations */
45 int arm720t_target_create(struct target_s
*target
,Jim_Interp
*interp
);
46 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm720t_quit(void);
48 int arm720t_arch_state(struct target_s
*target
);
49 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
51 int arm720t_soft_reset_halt(struct target_s
*target
);
53 target_type_t arm720t_target
=
58 .arch_state
= arm720t_arch_state
,
61 .resume
= arm7_9_resume
,
64 .assert_reset
= arm7_9_assert_reset
,
65 .deassert_reset
= arm7_9_deassert_reset
,
66 .soft_reset_halt
= arm720t_soft_reset_halt
,
68 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
70 .read_memory
= arm720t_read_memory
,
71 .write_memory
= arm720t_write_memory
,
72 .bulk_write_memory
= arm7_9_bulk_write_memory
,
73 .checksum_memory
= arm7_9_checksum_memory
,
74 .blank_check_memory
= arm7_9_blank_check_memory
,
76 .run_algorithm
= armv4_5_run_algorithm
,
78 .add_breakpoint
= arm7_9_add_breakpoint
,
79 .remove_breakpoint
= arm7_9_remove_breakpoint
,
80 .add_watchpoint
= arm7_9_add_watchpoint
,
81 .remove_watchpoint
= arm7_9_remove_watchpoint
,
83 .register_commands
= arm720t_register_commands
,
84 .target_create
= arm720t_target_create
,
85 .init_target
= arm720t_init_target
,
86 .examine
= arm7tdmi_examine
,
90 int arm720t_scan_cp15(target_t
*target
, u32 out
, u32
*in
, int instruction
, int clock
)
92 armv4_5_common_t
*armv4_5
= target
->arch_info
;
93 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
94 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
95 scan_field_t fields
[2];
97 u8 instruction_buf
= instruction
;
99 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
101 jtag_add_end_state(TAP_PD
);
102 arm_jtag_scann(jtag_info
, 0xf);
103 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
105 fields
[0].device
= jtag_info
->chain_pos
;
106 fields
[0].num_bits
= 1;
107 fields
[0].out_value
= &instruction_buf
;
108 fields
[0].out_mask
= NULL
;
109 fields
[0].in_value
= NULL
;
110 fields
[0].in_check_value
= NULL
;
111 fields
[0].in_check_mask
= NULL
;
112 fields
[0].in_handler
= NULL
;
113 fields
[0].in_handler_priv
= NULL
;
115 fields
[1].device
= jtag_info
->chain_pos
;
116 fields
[1].num_bits
= 32;
117 fields
[1].out_value
= out_buf
;
118 fields
[1].out_mask
= NULL
;
119 fields
[1].in_value
= NULL
;
122 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
123 fields
[1].in_handler_priv
= in
;
126 fields
[1].in_handler
= NULL
;
127 fields
[1].in_handler_priv
= NULL
;
129 fields
[1].in_check_value
= NULL
;
130 fields
[1].in_check_mask
= NULL
;
132 jtag_add_dr_scan(2, fields
, -1);
135 jtag_add_runtest(0, -1);
137 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
138 jtag_execute_queue();
141 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
143 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
145 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
151 int arm720t_read_cp15(target_t
*target
, u32 opcode
, u32
*value
)
153 /* fetch CP15 opcode */
154 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
156 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
157 /* "EXECUTE" stage (1) */
158 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
159 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
160 /* "EXECUTE" stage (2) */
161 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
162 /* "EXECUTE" stage (3), CDATA is read */
163 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
168 int arm720t_write_cp15(target_t
*target
, u32 opcode
, u32 value
)
170 /* fetch CP15 opcode */
171 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
173 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
174 /* "EXECUTE" stage (1) */
175 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
176 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
177 /* "EXECUTE" stage (2) */
178 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
179 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
184 u32
arm720t_get_ttb(target_t
*target
)
188 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
189 jtag_execute_queue();
196 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
200 /* read cp15 control register */
201 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
202 jtag_execute_queue();
205 cp15_control
&= ~0x1U
;
207 if (d_u_cache
|| i_cache
)
208 cp15_control
&= ~0x4U
;
210 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
213 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
217 /* read cp15 control register */
218 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
219 jtag_execute_queue();
222 cp15_control
|= 0x1U
;
224 if (d_u_cache
|| i_cache
)
225 cp15_control
|= 0x4U
;
227 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
230 void arm720t_post_debug_entry(target_t
*target
)
232 armv4_5_common_t
*armv4_5
= target
->arch_info
;
233 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
234 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
235 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
237 /* examine cp15 control reg */
238 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
239 jtag_execute_queue();
240 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t
->cp15_control_reg
);
242 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
243 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
244 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
246 /* save i/d fault status and address register */
247 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
248 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
249 jtag_execute_queue();
252 void arm720t_pre_restore_context(target_t
*target
)
254 armv4_5_common_t
*armv4_5
= target
->arch_info
;
255 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
256 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
257 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
259 /* restore i/d fault status and address register */
260 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
261 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
264 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
266 armv4_5_common_t
*armv4_5
= target
->arch_info
;
267 arm7_9_common_t
*arm7_9
;
268 arm7tdmi_common_t
*arm7tdmi
;
269 arm720t_common_t
*arm720t
;
271 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
276 arm7_9
= armv4_5
->arch_info
;
277 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
282 arm7tdmi
= arm7_9
->arch_info
;
283 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
288 arm720t
= arm7tdmi
->arch_info
;
289 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
294 *armv4_5_p
= armv4_5
;
296 *arm7tdmi_p
= arm7tdmi
;
297 *arm720t_p
= arm720t
;
302 int arm720t_arch_state(struct target_s
*target
)
304 armv4_5_common_t
*armv4_5
= target
->arch_info
;
305 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
306 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
307 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
311 "disabled", "enabled"
314 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
316 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
320 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
321 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
322 "MMU: %s, Cache: %s",
323 armv4_5_state_strings
[armv4_5
->core_state
],
324 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
325 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
326 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
327 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
328 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
329 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
334 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
337 armv4_5_common_t
*armv4_5
= target
->arch_info
;
338 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
339 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
340 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
342 /* disable cache, but leave MMU enabled */
343 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
344 arm720t_disable_mmu_caches(target
, 0, 1, 0);
346 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
348 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
349 arm720t_enable_mmu_caches(target
, 0, 1, 0);
354 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
358 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
364 int arm720t_soft_reset_halt(struct target_s
*target
)
366 armv4_5_common_t
*armv4_5
= target
->arch_info
;
367 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
368 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
369 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
370 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
374 long long then
=timeval_ms();
376 while (!(timeout
=((timeval_ms()-then
)>1000)))
378 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
380 embeddedice_read_reg(dbg_stat
);
381 jtag_execute_queue();
396 LOG_ERROR("Failed to halt CPU after 1 sec");
397 return ERROR_TARGET_TIMEOUT
;
400 target
->state
= TARGET_HALTED
;
402 /* SVC, ARM state, IRQ and FIQ disabled */
403 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
404 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
405 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
407 /* start fetching from 0x0 */
408 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
409 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
410 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
412 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
413 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
415 arm720t_disable_mmu_caches(target
, 1, 1, 1);
416 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
417 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
418 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
420 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
425 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
427 arm7tdmi_init_target(cmd_ctx
, target
);
433 int arm720t_quit(void)
439 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, int chain_pos
, const char *variant
)
441 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
442 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
444 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
446 arm7tdmi
->arch_info
= arm720t
;
447 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
449 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
450 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
452 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
453 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
454 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
455 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
456 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
457 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
458 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
459 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
464 int arm720t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
466 arm720t_common_t
*arm720t
= calloc(1,sizeof(arm720t_common_t
));
468 arm720t_init_arch_info(target
, arm720t
, target
->chain_position
, target
->variant
);
473 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
476 command_t
*arm720t_cmd
;
479 retval
= arm7tdmi_register_commands(cmd_ctx
);
481 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
483 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
484 register_command(cmd_ctx
, arm720t_cmd
, "virt2phys", arm720t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
486 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
487 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
488 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
490 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
491 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
492 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
497 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
500 target_t
*target
= get_current_target(cmd_ctx
);
501 armv4_5_common_t
*armv4_5
;
502 arm7_9_common_t
*arm7_9
;
503 arm7tdmi_common_t
*arm7tdmi
;
504 arm720t_common_t
*arm720t
;
505 arm_jtag_t
*jtag_info
;
507 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
509 command_print(cmd_ctx
, "current target isn't an ARM720t target");
513 jtag_info
= &arm7_9
->jtag_info
;
515 if (target
->state
!= TARGET_HALTED
)
517 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
521 /* one or more argument, access a single register (write if second argument is given */
524 u32 opcode
= strtoul(args
[0], NULL
, 0);
529 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
531 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
534 jtag_execute_queue();
536 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
540 u32 value
= strtoul(args
[1], NULL
, 0);
541 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
543 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
546 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
553 int arm720t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
555 target_t
*target
= get_current_target(cmd_ctx
);
556 armv4_5_common_t
*armv4_5
;
557 arm7_9_common_t
*arm7_9
;
558 arm7tdmi_common_t
*arm7tdmi
;
559 arm720t_common_t
*arm720t
;
560 arm_jtag_t
*jtag_info
;
562 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
564 command_print(cmd_ctx
, "current target isn't an ARM720t target");
568 jtag_info
= &arm7_9
->jtag_info
;
570 if (target
->state
!= TARGET_HALTED
)
572 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
576 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
579 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
581 target_t
*target
= get_current_target(cmd_ctx
);
582 armv4_5_common_t
*armv4_5
;
583 arm7_9_common_t
*arm7_9
;
584 arm7tdmi_common_t
*arm7tdmi
;
585 arm720t_common_t
*arm720t
;
586 arm_jtag_t
*jtag_info
;
588 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
590 command_print(cmd_ctx
, "current target isn't an ARM720t target");
594 jtag_info
= &arm7_9
->jtag_info
;
596 if (target
->state
!= TARGET_HALTED
)
598 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
602 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
605 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
607 target_t
*target
= get_current_target(cmd_ctx
);
608 armv4_5_common_t
*armv4_5
;
609 arm7_9_common_t
*arm7_9
;
610 arm7tdmi_common_t
*arm7tdmi
;
611 arm720t_common_t
*arm720t
;
612 arm_jtag_t
*jtag_info
;
614 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
616 command_print(cmd_ctx
, "current target isn't an ARM720t target");
620 jtag_info
= &arm7_9
->jtag_info
;
622 if (target
->state
!= TARGET_HALTED
)
624 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
628 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
633 * Local Variables: ***
634 * c-basic-offset: 4 ***
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