src/target/arm7_9_common.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  *                                                                         *
  13  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  14  *   hontor@126.com                                                        *
  15  ***************************************************************************/
  16
  17 #ifndef OPENOCD_TARGET_ARM7_9_COMMON_H
  18 #define OPENOCD_TARGET_ARM7_9_COMMON_H
  19
  20 #include "arm.h"
  21 #include "arm_jtag.h"
  22
  23 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
  24
  25 /**
  26  * Structure for items that are common between both ARM7 and ARM9 targets.
  27  */
  28 struct arm7_9_common {
  29         struct arm arm;
  30         uint32_t common_magic;
  31
  32         struct arm_jtag jtag_info; /**< JTAG information for target */
  33         struct reg_cache *eice_cache; /**< Embedded ICE register cache */
  34
  35         uint32_t arm_bkpt; /**< ARM breakpoint instruction */
  36         uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
  37
  38         int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
  39         int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
  40         int breakpoint_count; /**< Current number of set breakpoints */
  41         int wp_available; /**< Current number of available watchpoint units */
  42         int wp_available_max; /**< Maximum number of available watchpoint units */
  43         int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
  44         int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
  45         int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
  46         int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
  47         bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
  48         bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
  49
  50         bool has_single_step;
  51         bool has_monitor_mode;
  52         bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
  53
  54         bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
  55
  56         bool fast_memory_access;
  57         bool dcc_downloads;
  58
  59         struct working_area *dcc_working_area;
  60
  61         int (*examine_debug_reason)(struct target *target);
  62         /**< Function for determining why debug state was entered */
  63
  64         void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
  65         /**< Function for changing from Thumb to ARM mode */
  66
  67         void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
  68         /**< Function for reading the core registers */
  69
  70         void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
  71                         void *buffer, int size);
  72         void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
  73         /**< Function for reading CPSR or SPSR */
  74
  75         void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
  76         /**< Function for writing to CPSR or SPSR */
  77
  78         void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
  79         /**< Function for writing an immediate value to CPSR or SPSR */
  80
  81         void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
  82
  83         void (*load_word_regs)(struct target *target, uint32_t mask);
  84         void (*load_hword_reg)(struct target *target, int num);
  85         void (*load_byte_reg)(struct target *target, int num);
  86
  87         void (*store_word_regs)(struct target *target, uint32_t mask);
  88         void (*store_hword_reg)(struct target *target, int num);
  89         void (*store_byte_reg)(struct target *target, int num);
  90
  91         void (*write_pc)(struct target *target, uint32_t pc);
  92         /**< Function for writing to the program counter */
  93
  94         void (*branch_resume)(struct target *target);
  95         void (*branch_resume_thumb)(struct target *target);
  96
  97         void (*enable_single_step)(struct target *target, uint32_t next_pc);
  98         void (*disable_single_step)(struct target *target);
  99
 100         void (*set_special_dbgrq)(struct target *target);
 101         /**< Function for setting DBGRQ if the normal way won't work */
 102
 103         int (*post_debug_entry)(struct target *target);
 104         /**< Callback function called after entering debug mode */
 105
 106         void (*pre_restore_context)(struct target *target);
 107         /**< Callback function called before restoring the processor context */
 108
 109         /**
 110          * Variant specific memory write function that does not dispatch to bulk_write_memory.
 111          * Used as a fallback when bulk writes are unavailable, or for writing data needed to
 112          * do the bulk writes.
 113          */
 114         int (*write_memory)(struct target *target, target_addr_t address,
 115                         uint32_t size, uint32_t count, const uint8_t *buffer);
 116         /**
 117          * Write target memory in multiples of 4 bytes, optimized for
 118          * writing large quantities of data.
 119          */
 120         int (*bulk_write_memory)(struct target *target, target_addr_t address,
 121                         uint32_t count, const uint8_t *buffer);
 122 };
 123
 124 static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
 125 {
 126         return container_of(target->arch_info, struct arm7_9_common, arm);
 127 }
 128
 129 static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
 130 {
 131         return arm7_9->common_magic == ARM7_9_COMMON_MAGIC;
 132 }
 133
 134 extern const struct command_registration arm7_9_command_handlers[];
 135
 136 int arm7_9_poll(struct target *target);
 137
 138 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
 139
 140 int arm7_9_assert_reset(struct target *target);
 141 int arm7_9_deassert_reset(struct target *target);
 142 int arm7_9_reset_request_halt(struct target *target);
 143 int arm7_9_early_halt(struct target *target);
 144 int arm7_9_soft_reset_halt(struct target *target);
 145
 146 int arm7_9_halt(struct target *target);
 147 int arm7_9_resume(struct target *target, int current, target_addr_t address,
 148                 int handle_breakpoints, int debug_execution);
 149 int arm7_9_step(struct target *target, int current, target_addr_t address,
 150                 int handle_breakpoints);
 151 int arm7_9_read_memory(struct target *target, target_addr_t address,
 152                 uint32_t size, uint32_t count, uint8_t *buffer);
 153 int arm7_9_write_memory(struct target *target, target_addr_t address,
 154                 uint32_t size, uint32_t count, const uint8_t *buffer);
 155 int arm7_9_write_memory_opt(struct target *target, target_addr_t address,
 156                 uint32_t size, uint32_t count, const uint8_t *buffer);
 157 int arm7_9_write_memory_no_opt(struct target *target, uint32_t address,
 158                 uint32_t size, uint32_t count, const uint8_t *buffer);
 159 int arm7_9_bulk_write_memory(struct target *target, target_addr_t address,
 160                 uint32_t count, const uint8_t *buffer);
 161
 162 int arm7_9_run_algorithm(struct target *target, int num_mem_params,
 163                 struct mem_param *mem_params, int num_reg_prams,
 164                 struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
 165
 166 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 167 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 168 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 169 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 170
 171 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
 172 void arm7_9_disable_eice_step(struct target *target);
 173
 174 int arm7_9_execute_sys_speed(struct target *target);
 175
 176 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
 177 int arm7_9_examine(struct target *target);
 178 void arm7_9_deinit(struct target *target);
 179 int arm7_9_check_reset(struct target *target);
 180
 181 int arm7_9_endianness_callback(jtag_callback_data_t pu8_in,
 182                 jtag_callback_data_t i_size, jtag_callback_data_t i_be,
 183                 jtag_callback_data_t i_flip);
 184
 185 #endif /* OPENOCD_TARGET_ARM7_9_COMMON_H */