1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 /* forward declarations */
47 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
48 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
49 int arm7tdmi_quit(void);
51 /* target function declarations */
52 int arm7tdmi_poll(struct target_s
*target
);
53 int arm7tdmi_halt(target_t
*target
);
55 target_type_t arm7tdmi_target
=
60 .arch_state
= armv4_5_arch_state
,
62 .target_request_data
= arm7_9_target_request_data
,
65 .resume
= arm7_9_resume
,
68 .assert_reset
= arm7_9_assert_reset
,
69 .deassert_reset
= arm7_9_deassert_reset
,
70 .soft_reset_halt
= arm7_9_soft_reset_halt
,
72 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
74 .read_memory
= arm7_9_read_memory
,
75 .write_memory
= arm7_9_write_memory
,
76 .bulk_write_memory
= arm7_9_bulk_write_memory
,
77 .checksum_memory
= arm7_9_checksum_memory
,
78 .blank_check_memory
= arm7_9_blank_check_memory
,
80 .run_algorithm
= armv4_5_run_algorithm
,
82 .add_breakpoint
= arm7_9_add_breakpoint
,
83 .remove_breakpoint
= arm7_9_remove_breakpoint
,
84 .add_watchpoint
= arm7_9_add_watchpoint
,
85 .remove_watchpoint
= arm7_9_remove_watchpoint
,
87 .register_commands
= arm7tdmi_register_commands
,
88 .target_command
= arm7tdmi_target_command
,
89 .init_target
= arm7tdmi_init_target
,
90 .examine
= arm7tdmi_examine
,
94 int arm7tdmi_examine_debug_reason(target_t
*target
)
96 /* get pointers to arch-specific information */
97 armv4_5_common_t
*armv4_5
= target
->arch_info
;
98 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
100 /* only check the debug reason if we don't know it already */
101 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
102 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
104 scan_field_t fields
[2];
108 jtag_add_end_state(TAP_PD
);
110 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
111 fields
[0].num_bits
= 1;
112 fields
[0].out_value
= NULL
;
113 fields
[0].out_mask
= NULL
;
114 fields
[0].in_value
= &breakpoint
;
115 fields
[0].in_check_value
= NULL
;
116 fields
[0].in_check_mask
= NULL
;
117 fields
[0].in_handler
= NULL
;
118 fields
[0].in_handler_priv
= NULL
;
120 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
121 fields
[1].num_bits
= 32;
122 fields
[1].out_value
= NULL
;
123 fields
[1].out_mask
= NULL
;
124 fields
[1].in_value
= databus
;
125 fields
[1].in_check_value
= NULL
;
126 fields
[1].in_check_mask
= NULL
;
127 fields
[1].in_handler
= NULL
;
128 fields
[1].in_handler_priv
= NULL
;
130 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
131 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
133 jtag_add_dr_scan(2, fields
, TAP_PD
);
134 jtag_execute_queue();
136 fields
[0].in_value
= NULL
;
137 fields
[0].out_value
= &breakpoint
;
138 fields
[1].in_value
= NULL
;
139 fields
[1].out_value
= databus
;
141 jtag_add_dr_scan(2, fields
, TAP_PD
);
144 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
146 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
152 static int arm7tdmi_num_bits
[]={1, 32};
153 static __inline
int arm7tdmi_clock_out_inner(arm_jtag_t
*jtag_info
, u32 out
, int breakpoint
)
155 u32 values
[2]={breakpoint
, flip_u32(out
, 32)};
157 jtag_add_dr_out(jtag_info
->chain_pos
,
163 jtag_add_runtest(0, -1);
168 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
169 static __inline
int arm7tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 out
, u32
*deprecated
, int breakpoint
)
171 jtag_add_end_state(TAP_PD
);
172 arm_jtag_scann(jtag_info
, 0x1);
173 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
175 return arm7tdmi_clock_out_inner(jtag_info
, out
, breakpoint
);
178 /* clock the target, reading the databus */
179 int arm7tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
181 scan_field_t fields
[2];
183 jtag_add_end_state(TAP_PD
);
184 arm_jtag_scann(jtag_info
, 0x1);
185 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
187 fields
[0].device
= jtag_info
->chain_pos
;
188 fields
[0].num_bits
= 1;
189 fields
[0].out_value
= NULL
;
190 fields
[0].out_mask
= NULL
;
191 fields
[0].in_value
= NULL
;
192 fields
[0].in_check_value
= NULL
;
193 fields
[0].in_check_mask
= NULL
;
194 fields
[0].in_handler
= NULL
;
195 fields
[0].in_handler_priv
= NULL
;
197 fields
[1].device
= jtag_info
->chain_pos
;
198 fields
[1].num_bits
= 32;
199 fields
[1].out_value
= NULL
;
200 fields
[1].out_mask
= NULL
;
201 fields
[1].in_value
= NULL
;
202 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
203 fields
[1].in_handler_priv
= in
;
204 fields
[1].in_check_value
= NULL
;
205 fields
[1].in_check_mask
= NULL
;
207 jtag_add_dr_scan(2, fields
, -1);
209 jtag_add_runtest(0, -1);
211 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
213 jtag_execute_queue();
217 LOG_DEBUG("in: 0x%8.8x", *in
);
221 LOG_ERROR("BUG: called with in == NULL");
229 /* clock the target, and read the databus
230 * the *in pointer points to a buffer where elements of 'size' bytes
231 * are stored in big (be==1) or little (be==0) endianness
233 int arm7tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
235 scan_field_t fields
[2];
237 jtag_add_end_state(TAP_PD
);
238 arm_jtag_scann(jtag_info
, 0x1);
239 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
241 fields
[0].device
= jtag_info
->chain_pos
;
242 fields
[0].num_bits
= 1;
243 fields
[0].out_value
= NULL
;
244 fields
[0].out_mask
= NULL
;
245 fields
[0].in_value
= NULL
;
246 fields
[0].in_check_value
= NULL
;
247 fields
[0].in_check_mask
= NULL
;
248 fields
[0].in_handler
= NULL
;
249 fields
[0].in_handler_priv
= NULL
;
251 fields
[1].device
= jtag_info
->chain_pos
;
252 fields
[1].num_bits
= 32;
253 fields
[1].out_value
= NULL
;
254 fields
[1].out_mask
= NULL
;
255 fields
[1].in_value
= NULL
;
259 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be32_flip
: arm_jtag_buf_to_le32_flip
;
262 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be16_flip
: arm_jtag_buf_to_le16_flip
;
265 fields
[1].in_handler
= arm_jtag_buf_to_8_flip
;
268 fields
[1].in_handler_priv
= in
;
269 fields
[1].in_check_value
= NULL
;
270 fields
[1].in_check_mask
= NULL
;
272 jtag_add_dr_scan(2, fields
, -1);
274 jtag_add_runtest(0, -1);
276 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
278 jtag_execute_queue();
282 LOG_DEBUG("in: 0x%8.8x", *(u32
*)in
);
286 LOG_ERROR("BUG: called with in == NULL");
294 void arm7tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
296 /* get pointers to arch-specific information */
297 armv4_5_common_t
*armv4_5
= target
->arch_info
;
298 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
299 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
301 /* save r0 before using it and put system in ARM state
302 * to allow common handling of ARM and THUMB debugging */
304 /* fetch STR r0, [r0] */
305 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
306 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
307 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
308 /* nothing fetched, STR r0, [r0] in Execute (2) */
309 arm7tdmi_clock_data_in(jtag_info
, r0
);
311 /* MOV r0, r15 fetched, STR in Decode */
312 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), NULL
, 0);
313 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
314 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
315 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
316 /* nothing fetched, STR r0, [r0] in Execute (2) */
317 arm7tdmi_clock_data_in(jtag_info
, pc
);
319 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
320 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
321 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
322 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
323 /* nothing fetched, data for LDR r0, [PC, #0] */
324 arm7tdmi_clock_out(jtag_info
, 0x0, NULL
, 0);
325 /* nothing fetched, data from previous cycle is written to register */
326 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
329 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), NULL
, 0);
330 /* NOP fetched, BX in Decode, MOV in Execute */
331 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
332 /* NOP fetched, BX in Execute (1) */
333 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
335 jtag_execute_queue();
337 /* fix program counter:
338 * MOV r0, r15 was the 4th instruction (+6)
339 * reading PC in Thumb state gives address of instruction + 4
345 void arm7tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
348 /* get pointers to arch-specific information */
349 armv4_5_common_t
*armv4_5
= target
->arch_info
;
350 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
351 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
353 /* STMIA r0-15, [r0] at debug speed
354 * register values will start to appear on 4th DCLK
356 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
358 /* fetch NOP, STM in DECODE stage */
359 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
360 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
361 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
363 for (i
= 0; i
<= 15; i
++)
366 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
367 arm7tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
372 void arm7tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
375 /* get pointers to arch-specific information */
376 armv4_5_common_t
*armv4_5
= target
->arch_info
;
377 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
378 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
379 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
380 u32
*buf_u32
= buffer
;
381 u16
*buf_u16
= buffer
;
384 /* STMIA r0-15, [r0] at debug speed
385 * register values will start to appear on 4th DCLK
387 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
389 /* fetch NOP, STM in DECODE stage */
390 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
391 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
392 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
394 for (i
= 0; i
<= 15; i
++)
396 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
402 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
405 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
408 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
416 void arm7tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
418 /* get pointers to arch-specific information */
419 armv4_5_common_t
*armv4_5
= target
->arch_info
;
420 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
421 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
424 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), NULL
, 0);
427 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), NULL
, 0);
428 /* fetch NOP, STR in DECODE stage */
429 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
430 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
431 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
432 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
433 arm7tdmi_clock_data_in(jtag_info
, xpsr
);
437 void arm7tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
439 /* get pointers to arch-specific information */
440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
441 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
442 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
444 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
447 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), NULL
, 0);
448 /* MSR2 fetched, MSR1 in DECODE */
449 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), NULL
, 0);
450 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
451 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), NULL
, 0);
452 /* nothing fetched, MSR1 in EXECUTE (2) */
453 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
454 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
455 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), NULL
, 0);
456 /* nothing fetched, MSR2 in EXECUTE (2) */
457 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
458 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
459 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
460 /* nothing fetched, MSR3 in EXECUTE (2) */
461 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
462 /* NOP fetched, MSR4 in EXECUTE (1) */
463 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
464 /* nothing fetched, MSR4 in EXECUTE (2) */
465 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
468 void arm7tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
470 /* get pointers to arch-specific information */
471 armv4_5_common_t
*armv4_5
= target
->arch_info
;
472 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
473 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
475 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
478 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), NULL
, 0);
479 /* NOP fetched, MSR in DECODE */
480 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
481 /* NOP fetched, MSR in EXECUTE (1) */
482 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
483 /* nothing fetched, MSR in EXECUTE (2) */
484 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
488 void arm7tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
491 /* get pointers to arch-specific information */
492 armv4_5_common_t
*armv4_5
= target
->arch_info
;
493 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
494 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
496 /* LDMIA r0-15, [r0] at debug speed
497 * register values will start to appear on 4th DCLK
499 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
501 /* fetch NOP, LDM in DECODE stage */
502 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
503 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
504 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
506 for (i
= 0; i
<= 15; i
++)
509 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
510 arm7tdmi_clock_out_inner(jtag_info
, core_regs
[i
], 0);
512 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
516 void arm7tdmi_load_word_regs(target_t
*target
, u32 mask
)
518 /* get pointers to arch-specific information */
519 armv4_5_common_t
*armv4_5
= target
->arch_info
;
520 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
521 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
523 /* put system-speed load-multiple into the pipeline */
524 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
525 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
526 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), NULL
, 0);
530 void arm7tdmi_load_hword_reg(target_t
*target
, int num
)
532 /* get pointers to arch-specific information */
533 armv4_5_common_t
*armv4_5
= target
->arch_info
;
534 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
535 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
537 /* put system-speed load half-word into the pipeline */
538 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
539 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
540 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), NULL
, 0);
544 void arm7tdmi_load_byte_reg(target_t
*target
, int num
)
546 /* get pointers to arch-specific information */
547 armv4_5_common_t
*armv4_5
= target
->arch_info
;
548 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
549 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
551 /* put system-speed load byte into the pipeline */
552 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
553 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
554 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), NULL
, 0);
558 void arm7tdmi_store_word_regs(target_t
*target
, u32 mask
)
560 /* get pointers to arch-specific information */
561 armv4_5_common_t
*armv4_5
= target
->arch_info
;
562 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
563 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
565 /* put system-speed store-multiple into the pipeline */
566 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
567 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
568 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), NULL
, 0);
572 void arm7tdmi_store_hword_reg(target_t
*target
, int num
)
574 /* get pointers to arch-specific information */
575 armv4_5_common_t
*armv4_5
= target
->arch_info
;
576 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
577 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
579 /* put system-speed store half-word into the pipeline */
580 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
581 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
582 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), NULL
, 0);
586 void arm7tdmi_store_byte_reg(target_t
*target
, int num
)
588 /* get pointers to arch-specific information */
589 armv4_5_common_t
*armv4_5
= target
->arch_info
;
590 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
591 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
593 /* put system-speed store byte into the pipeline */
594 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
595 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
596 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), NULL
, 0);
600 void arm7tdmi_write_pc(target_t
*target
, u32 pc
)
602 /* get pointers to arch-specific information */
603 armv4_5_common_t
*armv4_5
= target
->arch_info
;
604 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
605 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
607 /* LDMIA r0-15, [r0] at debug speed
608 * register values will start to appear on 4th DCLK
610 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL
, 0);
611 /* fetch NOP, LDM in DECODE stage */
612 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
613 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
614 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
615 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
616 arm7tdmi_clock_out_inner(jtag_info
, pc
, 0);
617 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
618 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
619 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
620 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
621 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
622 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
623 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
624 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
627 void arm7tdmi_branch_resume(target_t
*target
)
629 /* get pointers to arch-specific information */
630 armv4_5_common_t
*armv4_5
= target
->arch_info
;
631 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
632 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
634 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
635 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_B(0xfffffa, 0), 0);
639 void arm7tdmi_branch_resume_thumb(target_t
*target
)
643 /* get pointers to arch-specific information */
644 armv4_5_common_t
*armv4_5
= target
->arch_info
;
645 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
646 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
647 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
649 /* LDMIA r0, [r0] at debug speed
650 * register values will start to appear on 4th DCLK
652 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL
, 0);
654 /* fetch NOP, LDM in DECODE stage */
655 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
656 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
657 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
658 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
659 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
660 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
661 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
663 /* Branch and eXchange */
664 arm7tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), NULL
, 0);
666 embeddedice_read_reg(dbg_stat
);
668 /* fetch NOP, BX in DECODE stage */
669 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
671 /* target is now in Thumb state */
672 embeddedice_read_reg(dbg_stat
);
674 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
675 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
677 /* target is now in Thumb state */
678 embeddedice_read_reg(dbg_stat
);
681 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
682 /* fetch NOP, LDR in Decode */
683 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
684 /* fetch NOP, LDR in Execute */
685 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
686 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
687 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
688 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
689 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
691 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
692 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
694 embeddedice_read_reg(dbg_stat
);
696 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 1);
697 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f8), NULL
, 0);
701 void arm7tdmi_build_reg_cache(target_t
*target
)
703 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
704 /* get pointers to arch-specific information */
705 armv4_5_common_t
*armv4_5
= target
->arch_info
;
707 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
708 armv4_5
->core_cache
= (*cache_p
);
711 int arm7tdmi_examine(struct target_s
*target
)
714 armv4_5_common_t
*armv4_5
= target
->arch_info
;
715 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
716 if (!target
->type
->examined
)
718 /* get pointers to arch-specific information */
719 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
720 reg_cache_t
*t
=embeddedice_build_reg_cache(target
, arm7_9
);
725 arm7_9
->eice_cache
= (*cache_p
);
729 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
730 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
731 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
733 target
->type
->examined
= 1;
735 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
737 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
741 if ((retval
=etm_setup(target
))!=ERROR_OK
)
747 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
750 arm7tdmi_build_reg_cache(target
);
756 int arm7tdmi_quit(void)
762 int arm7tdmi_init_arch_info(target_t
*target
, arm7tdmi_common_t
*arm7tdmi
, int chain_pos
, char *variant
)
764 armv4_5_common_t
*armv4_5
;
765 arm7_9_common_t
*arm7_9
;
767 arm7_9
= &arm7tdmi
->arm7_9_common
;
768 armv4_5
= &arm7_9
->armv4_5_common
;
770 /* prepare JTAG information for the new target */
771 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
772 arm7_9
->jtag_info
.scann_size
= 4;
774 /* register arch-specific functions */
775 arm7_9
->examine_debug_reason
= arm7tdmi_examine_debug_reason
;
776 arm7_9
->change_to_arm
= arm7tdmi_change_to_arm
;
777 arm7_9
->read_core_regs
= arm7tdmi_read_core_regs
;
778 arm7_9
->read_core_regs_target_buffer
= arm7tdmi_read_core_regs_target_buffer
;
779 arm7_9
->read_xpsr
= arm7tdmi_read_xpsr
;
781 arm7_9
->write_xpsr
= arm7tdmi_write_xpsr
;
782 arm7_9
->write_xpsr_im8
= arm7tdmi_write_xpsr_im8
;
783 arm7_9
->write_core_regs
= arm7tdmi_write_core_regs
;
785 arm7_9
->load_word_regs
= arm7tdmi_load_word_regs
;
786 arm7_9
->load_hword_reg
= arm7tdmi_load_hword_reg
;
787 arm7_9
->load_byte_reg
= arm7tdmi_load_byte_reg
;
789 arm7_9
->store_word_regs
= arm7tdmi_store_word_regs
;
790 arm7_9
->store_hword_reg
= arm7tdmi_store_hword_reg
;
791 arm7_9
->store_byte_reg
= arm7tdmi_store_byte_reg
;
793 arm7_9
->write_pc
= arm7tdmi_write_pc
;
794 arm7_9
->branch_resume
= arm7tdmi_branch_resume
;
795 arm7_9
->branch_resume_thumb
= arm7tdmi_branch_resume_thumb
;
797 arm7_9
->enable_single_step
= arm7_9_enable_eice_step
;
798 arm7_9
->disable_single_step
= arm7_9_disable_eice_step
;
800 arm7_9
->pre_debug_entry
= NULL
;
801 arm7_9
->post_debug_entry
= NULL
;
803 arm7_9
->pre_restore_context
= NULL
;
804 arm7_9
->post_restore_context
= NULL
;
806 /* initialize arch-specific breakpoint handling */
807 arm7_9
->arm_bkpt
= 0xdeeedeee;
808 arm7_9
->thumb_bkpt
= 0xdeee;
810 arm7_9
->dbgreq_adjust_pc
= 2;
811 arm7_9
->arch_info
= arm7tdmi
;
813 arm7tdmi
->arch_info
= NULL
;
814 arm7tdmi
->common_magic
= ARM7TDMI_COMMON_MAGIC
;
818 arm7tdmi
->variant
= strdup(variant
);
822 arm7tdmi
->variant
= strdup("");
825 arm7_9_init_arch_info(target
, arm7_9
);
830 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
831 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
834 char *variant
= NULL
;
835 arm7tdmi_common_t
*arm7tdmi
= malloc(sizeof(arm7tdmi_common_t
));
836 memset(arm7tdmi
, 0, sizeof(*arm7tdmi
));
840 LOG_ERROR("'target arm7tdmi' requires at least one additional argument");
844 chain_pos
= strtoul(args
[3], NULL
, 0);
849 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
854 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
)
858 retval
= arm7_9_register_commands(cmd_ctx
);
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