1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 /* forward declarations */
47 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
48 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
51 /* target function declarations */
52 int arm7tdmi_poll(struct target_s
*target
);
53 int arm7tdmi_halt(target_t
*target
);
55 target_type_t arm7tdmi_target
=
60 .arch_state
= armv4_5_arch_state
,
62 .target_request_data
= arm7_9_target_request_data
,
65 .resume
= arm7_9_resume
,
68 .assert_reset
= arm7_9_assert_reset
,
69 .deassert_reset
= arm7_9_deassert_reset
,
70 .soft_reset_halt
= arm7_9_soft_reset_halt
,
72 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
74 .read_memory
= arm7_9_read_memory
,
75 .write_memory
= arm7_9_write_memory
,
76 .bulk_write_memory
= arm7_9_bulk_write_memory
,
77 .checksum_memory
= arm7_9_checksum_memory
,
79 .run_algorithm
= armv4_5_run_algorithm
,
81 .add_breakpoint
= arm7_9_add_breakpoint
,
82 .remove_breakpoint
= arm7_9_remove_breakpoint
,
83 .add_watchpoint
= arm7_9_add_watchpoint
,
84 .remove_watchpoint
= arm7_9_remove_watchpoint
,
86 .register_commands
= arm7tdmi_register_commands
,
87 .target_command
= arm7tdmi_target_command
,
88 .init_target
= arm7tdmi_init_target
,
89 .examine
= arm7tdmi_examine
,
93 int arm7tdmi_examine_debug_reason(target_t
*target
)
95 /* get pointers to arch-specific information */
96 armv4_5_common_t
*armv4_5
= target
->arch_info
;
97 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
99 /* only check the debug reason if we don't know it already */
100 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
101 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
103 scan_field_t fields
[2];
107 jtag_add_end_state(TAP_PD
);
109 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
110 fields
[0].num_bits
= 1;
111 fields
[0].out_value
= NULL
;
112 fields
[0].out_mask
= NULL
;
113 fields
[0].in_value
= &breakpoint
;
114 fields
[0].in_check_value
= NULL
;
115 fields
[0].in_check_mask
= NULL
;
116 fields
[0].in_handler
= NULL
;
117 fields
[0].in_handler_priv
= NULL
;
119 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
120 fields
[1].num_bits
= 32;
121 fields
[1].out_value
= NULL
;
122 fields
[1].out_mask
= NULL
;
123 fields
[1].in_value
= databus
;
124 fields
[1].in_check_value
= NULL
;
125 fields
[1].in_check_mask
= NULL
;
126 fields
[1].in_handler
= NULL
;
127 fields
[1].in_handler_priv
= NULL
;
129 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
130 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
132 jtag_add_dr_scan(2, fields
, TAP_PD
);
133 jtag_execute_queue();
135 fields
[0].in_value
= NULL
;
136 fields
[0].out_value
= &breakpoint
;
137 fields
[1].in_value
= NULL
;
138 fields
[1].out_value
= databus
;
140 jtag_add_dr_scan(2, fields
, TAP_PD
);
143 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
145 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
151 static int arm7tdmi_num_bits
[]={1, 32};
152 static __inline
int arm7tdmi_clock_out_inner(arm_jtag_t
*jtag_info
, u32 out
, int breakpoint
)
154 u32 values
[2]={breakpoint
, flip_u32(out
, 32)};
156 jtag_add_dr_out(jtag_info
->chain_pos
,
162 jtag_add_runtest(0, -1);
167 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
168 static __inline
int arm7tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 out
, u32
*deprecated
, int breakpoint
)
170 jtag_add_end_state(TAP_PD
);
171 arm_jtag_scann(jtag_info
, 0x1);
172 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
174 return arm7tdmi_clock_out_inner(jtag_info
, out
, breakpoint
);
177 /* clock the target, reading the databus */
178 int arm7tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
180 scan_field_t fields
[2];
182 jtag_add_end_state(TAP_PD
);
183 arm_jtag_scann(jtag_info
, 0x1);
184 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
186 fields
[0].device
= jtag_info
->chain_pos
;
187 fields
[0].num_bits
= 1;
188 fields
[0].out_value
= NULL
;
189 fields
[0].out_mask
= NULL
;
190 fields
[0].in_value
= NULL
;
191 fields
[0].in_check_value
= NULL
;
192 fields
[0].in_check_mask
= NULL
;
193 fields
[0].in_handler
= NULL
;
194 fields
[0].in_handler_priv
= NULL
;
196 fields
[1].device
= jtag_info
->chain_pos
;
197 fields
[1].num_bits
= 32;
198 fields
[1].out_value
= NULL
;
199 fields
[1].out_mask
= NULL
;
200 fields
[1].in_value
= NULL
;
201 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
202 fields
[1].in_handler_priv
= in
;
203 fields
[1].in_check_value
= NULL
;
204 fields
[1].in_check_mask
= NULL
;
206 jtag_add_dr_scan(2, fields
, -1);
208 jtag_add_runtest(0, -1);
210 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
212 jtag_execute_queue();
216 LOG_DEBUG("in: 0x%8.8x", *in
);
220 LOG_ERROR("BUG: called with in == NULL");
228 /* clock the target, and read the databus
229 * the *in pointer points to a buffer where elements of 'size' bytes
230 * are stored in big (be==1) or little (be==0) endianness
232 int arm7tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
234 scan_field_t fields
[2];
236 jtag_add_end_state(TAP_PD
);
237 arm_jtag_scann(jtag_info
, 0x1);
238 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
240 fields
[0].device
= jtag_info
->chain_pos
;
241 fields
[0].num_bits
= 1;
242 fields
[0].out_value
= NULL
;
243 fields
[0].out_mask
= NULL
;
244 fields
[0].in_value
= NULL
;
245 fields
[0].in_check_value
= NULL
;
246 fields
[0].in_check_mask
= NULL
;
247 fields
[0].in_handler
= NULL
;
248 fields
[0].in_handler_priv
= NULL
;
250 fields
[1].device
= jtag_info
->chain_pos
;
251 fields
[1].num_bits
= 32;
252 fields
[1].out_value
= NULL
;
253 fields
[1].out_mask
= NULL
;
254 fields
[1].in_value
= NULL
;
258 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be32_flip
: arm_jtag_buf_to_le32_flip
;
261 fields
[1].in_handler
= (be
) ? arm_jtag_buf_to_be16_flip
: arm_jtag_buf_to_le16_flip
;
264 fields
[1].in_handler
= arm_jtag_buf_to_8_flip
;
267 fields
[1].in_handler_priv
= in
;
268 fields
[1].in_check_value
= NULL
;
269 fields
[1].in_check_mask
= NULL
;
271 jtag_add_dr_scan(2, fields
, -1);
273 jtag_add_runtest(0, -1);
275 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
277 jtag_execute_queue();
281 LOG_DEBUG("in: 0x%8.8x", *in
);
285 LOG_ERROR("BUG: called with in == NULL");
293 void arm7tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
295 /* get pointers to arch-specific information */
296 armv4_5_common_t
*armv4_5
= target
->arch_info
;
297 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
298 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
300 /* save r0 before using it and put system in ARM state
301 * to allow common handling of ARM and THUMB debugging */
303 /* fetch STR r0, [r0] */
304 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
305 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
306 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
307 /* nothing fetched, STR r0, [r0] in Execute (2) */
308 arm7tdmi_clock_data_in(jtag_info
, r0
);
310 /* MOV r0, r15 fetched, STR in Decode */
311 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), NULL
, 0);
312 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
313 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
314 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
315 /* nothing fetched, STR r0, [r0] in Execute (2) */
316 arm7tdmi_clock_data_in(jtag_info
, pc
);
318 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
319 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
320 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
321 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
322 /* nothing fetched, data for LDR r0, [PC, #0] */
323 arm7tdmi_clock_out(jtag_info
, 0x0, NULL
, 0);
324 /* nothing fetched, data from previous cycle is written to register */
325 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
328 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), NULL
, 0);
329 /* NOP fetched, BX in Decode, MOV in Execute */
330 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
331 /* NOP fetched, BX in Execute (1) */
332 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
334 jtag_execute_queue();
336 /* fix program counter:
337 * MOV r0, r15 was the 4th instruction (+6)
338 * reading PC in Thumb state gives address of instruction + 4
344 void arm7tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
347 /* get pointers to arch-specific information */
348 armv4_5_common_t
*armv4_5
= target
->arch_info
;
349 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
350 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
352 /* STMIA r0-15, [r0] at debug speed
353 * register values will start to appear on 4th DCLK
355 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
357 /* fetch NOP, STM in DECODE stage */
358 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
359 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
360 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
362 for (i
= 0; i
<= 15; i
++)
365 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
366 arm7tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
371 void arm7tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
374 /* get pointers to arch-specific information */
375 armv4_5_common_t
*armv4_5
= target
->arch_info
;
376 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
377 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
378 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
379 u32
*buf_u32
= buffer
;
380 u16
*buf_u16
= buffer
;
383 /* STMIA r0-15, [r0] at debug speed
384 * register values will start to appear on 4th DCLK
386 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
388 /* fetch NOP, STM in DECODE stage */
389 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
390 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
391 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
393 for (i
= 0; i
<= 15; i
++)
395 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
401 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
404 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
407 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
415 void arm7tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
417 /* get pointers to arch-specific information */
418 armv4_5_common_t
*armv4_5
= target
->arch_info
;
419 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
420 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
423 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), NULL
, 0);
426 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), NULL
, 0);
427 /* fetch NOP, STR in DECODE stage */
428 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
429 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
430 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
431 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
432 arm7tdmi_clock_data_in(jtag_info
, xpsr
);
436 void arm7tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
438 /* get pointers to arch-specific information */
439 armv4_5_common_t
*armv4_5
= target
->arch_info
;
440 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
441 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
443 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
446 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), NULL
, 0);
447 /* MSR2 fetched, MSR1 in DECODE */
448 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), NULL
, 0);
449 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
450 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), NULL
, 0);
451 /* nothing fetched, MSR1 in EXECUTE (2) */
452 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
453 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
454 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), NULL
, 0);
455 /* nothing fetched, MSR2 in EXECUTE (2) */
456 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
457 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
458 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
459 /* nothing fetched, MSR3 in EXECUTE (2) */
460 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
461 /* NOP fetched, MSR4 in EXECUTE (1) */
462 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
463 /* nothing fetched, MSR4 in EXECUTE (2) */
464 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
467 void arm7tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
469 /* get pointers to arch-specific information */
470 armv4_5_common_t
*armv4_5
= target
->arch_info
;
471 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
472 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
474 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
477 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), NULL
, 0);
478 /* NOP fetched, MSR in DECODE */
479 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
480 /* NOP fetched, MSR in EXECUTE (1) */
481 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
482 /* nothing fetched, MSR in EXECUTE (2) */
483 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
487 void arm7tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
490 /* get pointers to arch-specific information */
491 armv4_5_common_t
*armv4_5
= target
->arch_info
;
492 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
493 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
495 /* LDMIA r0-15, [r0] at debug speed
496 * register values will start to appear on 4th DCLK
498 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
500 /* fetch NOP, LDM in DECODE stage */
501 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
502 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
503 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
505 for (i
= 0; i
<= 15; i
++)
508 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
509 arm7tdmi_clock_out_inner(jtag_info
, core_regs
[i
], 0);
511 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
515 void arm7tdmi_load_word_regs(target_t
*target
, u32 mask
)
517 /* get pointers to arch-specific information */
518 armv4_5_common_t
*armv4_5
= target
->arch_info
;
519 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
520 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
522 /* put system-speed load-multiple into the pipeline */
523 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
524 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
525 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), NULL
, 0);
529 void arm7tdmi_load_hword_reg(target_t
*target
, int num
)
531 /* get pointers to arch-specific information */
532 armv4_5_common_t
*armv4_5
= target
->arch_info
;
533 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
534 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
536 /* put system-speed load half-word into the pipeline */
537 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
538 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
539 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), NULL
, 0);
543 void arm7tdmi_load_byte_reg(target_t
*target
, int num
)
545 /* get pointers to arch-specific information */
546 armv4_5_common_t
*armv4_5
= target
->arch_info
;
547 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
548 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
550 /* put system-speed load byte into the pipeline */
551 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
552 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
553 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), NULL
, 0);
557 void arm7tdmi_store_word_regs(target_t
*target
, u32 mask
)
559 /* get pointers to arch-specific information */
560 armv4_5_common_t
*armv4_5
= target
->arch_info
;
561 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
562 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
564 /* put system-speed store-multiple into the pipeline */
565 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
566 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
567 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), NULL
, 0);
571 void arm7tdmi_store_hword_reg(target_t
*target
, int num
)
573 /* get pointers to arch-specific information */
574 armv4_5_common_t
*armv4_5
= target
->arch_info
;
575 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
576 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
578 /* put system-speed store half-word into the pipeline */
579 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
580 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
581 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), NULL
, 0);
585 void arm7tdmi_store_byte_reg(target_t
*target
, int num
)
587 /* get pointers to arch-specific information */
588 armv4_5_common_t
*armv4_5
= target
->arch_info
;
589 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
590 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
592 /* put system-speed store byte into the pipeline */
593 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
594 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
595 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), NULL
, 0);
599 void arm7tdmi_write_pc(target_t
*target
, u32 pc
)
601 /* get pointers to arch-specific information */
602 armv4_5_common_t
*armv4_5
= target
->arch_info
;
603 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
604 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
606 /* LDMIA r0-15, [r0] at debug speed
607 * register values will start to appear on 4th DCLK
609 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL
, 0);
610 /* fetch NOP, LDM in DECODE stage */
611 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
612 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
613 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
614 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
615 arm7tdmi_clock_out_inner(jtag_info
, pc
, 0);
616 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
617 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
618 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
619 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
620 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
621 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
622 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
623 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
626 void arm7tdmi_branch_resume(target_t
*target
)
628 /* get pointers to arch-specific information */
629 armv4_5_common_t
*armv4_5
= target
->arch_info
;
630 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
631 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
633 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
634 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_B(0xfffffa, 0), 0);
638 void arm7tdmi_branch_resume_thumb(target_t
*target
)
642 /* get pointers to arch-specific information */
643 armv4_5_common_t
*armv4_5
= target
->arch_info
;
644 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
645 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
646 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
648 /* LDMIA r0, [r0] at debug speed
649 * register values will start to appear on 4th DCLK
651 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL
, 0);
653 /* fetch NOP, LDM in DECODE stage */
654 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
655 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
656 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
657 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
658 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
659 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
660 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
662 /* Branch and eXchange */
663 arm7tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), NULL
, 0);
665 embeddedice_read_reg(dbg_stat
);
667 /* fetch NOP, BX in DECODE stage */
668 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
670 /* target is now in Thumb state */
671 embeddedice_read_reg(dbg_stat
);
673 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
674 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
676 /* target is now in Thumb state */
677 embeddedice_read_reg(dbg_stat
);
680 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
681 /* fetch NOP, LDR in Decode */
682 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
683 /* fetch NOP, LDR in Execute */
684 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
685 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
686 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
687 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
688 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
690 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
691 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
693 embeddedice_read_reg(dbg_stat
);
695 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 1);
696 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f8), NULL
, 0);
700 void arm7tdmi_build_reg_cache(target_t
*target
)
702 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
703 /* get pointers to arch-specific information */
704 armv4_5_common_t
*armv4_5
= target
->arch_info
;
706 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
707 armv4_5
->core_cache
= (*cache_p
);
710 int arm7tdmi_examine(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
713 armv4_5_common_t
*armv4_5
= target
->arch_info
;
714 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
715 if (!target
->type
->examined
)
717 /* get pointers to arch-specific information */
718 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
719 reg_cache_t
*t
=embeddedice_build_reg_cache(target
, arm7_9
);
724 arm7_9
->eice_cache
= (*cache_p
);
728 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
729 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
730 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
732 target
->type
->examined
= 1;
734 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
736 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
740 if ((retval
=etm_setup(target
))!=ERROR_OK
)
746 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
749 arm7tdmi_build_reg_cache(target
);
761 int arm7tdmi_init_arch_info(target_t
*target
, arm7tdmi_common_t
*arm7tdmi
, int chain_pos
, char *variant
)
763 armv4_5_common_t
*armv4_5
;
764 arm7_9_common_t
*arm7_9
;
766 arm7_9
= &arm7tdmi
->arm7_9_common
;
767 armv4_5
= &arm7_9
->armv4_5_common
;
769 /* prepare JTAG information for the new target */
770 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
771 arm7_9
->jtag_info
.scann_size
= 4;
773 /* register arch-specific functions */
774 arm7_9
->examine_debug_reason
= arm7tdmi_examine_debug_reason
;
775 arm7_9
->change_to_arm
= arm7tdmi_change_to_arm
;
776 arm7_9
->read_core_regs
= arm7tdmi_read_core_regs
;
777 arm7_9
->read_core_regs_target_buffer
= arm7tdmi_read_core_regs_target_buffer
;
778 arm7_9
->read_xpsr
= arm7tdmi_read_xpsr
;
780 arm7_9
->write_xpsr
= arm7tdmi_write_xpsr
;
781 arm7_9
->write_xpsr_im8
= arm7tdmi_write_xpsr_im8
;
782 arm7_9
->write_core_regs
= arm7tdmi_write_core_regs
;
784 arm7_9
->load_word_regs
= arm7tdmi_load_word_regs
;
785 arm7_9
->load_hword_reg
= arm7tdmi_load_hword_reg
;
786 arm7_9
->load_byte_reg
= arm7tdmi_load_byte_reg
;
788 arm7_9
->store_word_regs
= arm7tdmi_store_word_regs
;
789 arm7_9
->store_hword_reg
= arm7tdmi_store_hword_reg
;
790 arm7_9
->store_byte_reg
= arm7tdmi_store_byte_reg
;
792 arm7_9
->write_pc
= arm7tdmi_write_pc
;
793 arm7_9
->branch_resume
= arm7tdmi_branch_resume
;
794 arm7_9
->branch_resume_thumb
= arm7tdmi_branch_resume_thumb
;
796 arm7_9
->enable_single_step
= arm7_9_enable_eice_step
;
797 arm7_9
->disable_single_step
= arm7_9_disable_eice_step
;
799 arm7_9
->pre_debug_entry
= NULL
;
800 arm7_9
->post_debug_entry
= NULL
;
802 arm7_9
->pre_restore_context
= NULL
;
803 arm7_9
->post_restore_context
= NULL
;
805 /* initialize arch-specific breakpoint handling */
806 arm7_9
->arm_bkpt
= 0xdeeedeee;
807 arm7_9
->thumb_bkpt
= 0xdeee;
809 arm7_9
->sw_bkpts_use_wp
= 1;
810 arm7_9
->sw_bkpts_enabled
= 0;
811 arm7_9
->dbgreq_adjust_pc
= 2;
812 arm7_9
->arch_info
= arm7tdmi
;
814 arm7tdmi
->arch_info
= NULL
;
815 arm7tdmi
->common_magic
= ARM7TDMI_COMMON_MAGIC
;
819 arm7tdmi
->variant
= strdup(variant
);
823 arm7tdmi
->variant
= strdup("");
826 arm7_9_init_arch_info(target
, arm7_9
);
831 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
832 int arm7tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
835 char *variant
= NULL
;
836 arm7tdmi_common_t
*arm7tdmi
= malloc(sizeof(arm7tdmi_common_t
));
837 memset(arm7tdmi
, 0, sizeof(*arm7tdmi
));
841 LOG_ERROR("'target arm7tdmi' requires at least one additional argument");
845 chain_pos
= strtoul(args
[3], NULL
, 0);
850 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
855 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
)
859 retval
= arm7_9_register_commands(cmd_ctx
);
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