1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
53 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_soft_reset_halt(struct target_s
*target
);
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59 target_type_t arm920t_target
=
64 .arch_state
= arm920t_arch_state
,
67 .resume
= arm7_9_resume
,
70 .assert_reset
= arm7_9_assert_reset
,
71 .deassert_reset
= arm7_9_deassert_reset
,
72 .soft_reset_halt
= arm920t_soft_reset_halt
,
73 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
75 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
77 .read_memory
= arm920t_read_memory
,
78 .write_memory
= arm920t_write_memory
,
79 .bulk_write_memory
= arm7_9_bulk_write_memory
,
81 .run_algorithm
= armv4_5_run_algorithm
,
83 .add_breakpoint
= arm7_9_add_breakpoint
,
84 .remove_breakpoint
= arm7_9_remove_breakpoint
,
85 .add_watchpoint
= arm7_9_add_watchpoint
,
86 .remove_watchpoint
= arm7_9_remove_watchpoint
,
88 .register_commands
= arm920t_register_commands
,
89 .target_command
= arm920t_target_command
,
90 .init_target
= arm920t_init_target
,
94 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
96 armv4_5_common_t
*armv4_5
= target
->arch_info
;
97 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
98 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
99 scan_field_t fields
[4];
100 u8 access_type_buf
= 1;
101 u8 reg_addr_buf
= reg_addr
& 0x3f;
104 jtag_add_end_state(TAP_RTI
);
105 arm_jtag_scann(jtag_info
, 0xf);
106 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
108 fields
[0].device
= jtag_info
->chain_pos
;
109 fields
[0].num_bits
= 1;
110 fields
[0].out_value
= &access_type_buf
;
111 fields
[0].out_mask
= NULL
;
112 fields
[0].in_value
= NULL
;
113 fields
[0].in_check_value
= NULL
;
114 fields
[0].in_check_mask
= NULL
;
115 fields
[0].in_handler
= NULL
;
116 fields
[0].in_handler_priv
= NULL
;
118 fields
[1].device
= jtag_info
->chain_pos
;
119 fields
[1].num_bits
= 32;
120 fields
[1].out_value
= NULL
;
121 fields
[1].out_mask
= NULL
;
122 fields
[1].in_value
= NULL
;
123 fields
[1].in_check_value
= NULL
;
124 fields
[1].in_check_mask
= NULL
;
125 fields
[1].in_handler
= NULL
;
126 fields
[1].in_handler_priv
= NULL
;
128 fields
[2].device
= jtag_info
->chain_pos
;
129 fields
[2].num_bits
= 6;
130 fields
[2].out_value
= ®_addr_buf
;
131 fields
[2].out_mask
= NULL
;
132 fields
[2].in_value
= NULL
;
133 fields
[2].in_check_value
= NULL
;
134 fields
[2].in_check_mask
= NULL
;
135 fields
[2].in_handler
= NULL
;
136 fields
[2].in_handler_priv
= NULL
;
138 fields
[3].device
= jtag_info
->chain_pos
;
139 fields
[3].num_bits
= 1;
140 fields
[3].out_value
= &nr_w_buf
;
141 fields
[3].out_mask
= NULL
;
142 fields
[3].in_value
= NULL
;
143 fields
[3].in_check_value
= NULL
;
144 fields
[3].in_check_mask
= NULL
;
145 fields
[3].in_handler
= NULL
;
146 fields
[3].in_handler_priv
= NULL
;
148 jtag_add_dr_scan(4, fields
, -1, NULL
);
150 fields
[1].in_handler_priv
= value
;
151 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
153 jtag_add_dr_scan(4, fields
, -1, NULL
);
155 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
156 jtag_execute_queue();
157 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
163 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
165 armv4_5_common_t
*armv4_5
= target
->arch_info
;
166 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
167 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
168 scan_field_t fields
[4];
169 u8 access_type_buf
= 1;
170 u8 reg_addr_buf
= reg_addr
& 0x3f;
174 buf_set_u32(value_buf
, 0, 32, value
);
176 jtag_add_end_state(TAP_RTI
);
177 arm_jtag_scann(jtag_info
, 0xf);
178 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
180 fields
[0].device
= jtag_info
->chain_pos
;
181 fields
[0].num_bits
= 1;
182 fields
[0].out_value
= &access_type_buf
;
183 fields
[0].out_mask
= NULL
;
184 fields
[0].in_value
= NULL
;
185 fields
[0].in_check_value
= NULL
;
186 fields
[0].in_check_mask
= NULL
;
187 fields
[0].in_handler
= NULL
;
188 fields
[0].in_handler_priv
= NULL
;
190 fields
[1].device
= jtag_info
->chain_pos
;
191 fields
[1].num_bits
= 32;
192 fields
[1].out_value
= value_buf
;
193 fields
[1].out_mask
= NULL
;
194 fields
[1].in_value
= NULL
;
195 fields
[1].in_check_value
= NULL
;
196 fields
[1].in_check_mask
= NULL
;
197 fields
[1].in_handler
= NULL
;
198 fields
[1].in_handler_priv
= NULL
;
200 fields
[2].device
= jtag_info
->chain_pos
;
201 fields
[2].num_bits
= 6;
202 fields
[2].out_value
= ®_addr_buf
;
203 fields
[2].out_mask
= NULL
;
204 fields
[2].in_value
= NULL
;
205 fields
[2].in_check_value
= NULL
;
206 fields
[2].in_check_mask
= NULL
;
207 fields
[2].in_handler
= NULL
;
208 fields
[2].in_handler_priv
= NULL
;
210 fields
[3].device
= jtag_info
->chain_pos
;
211 fields
[3].num_bits
= 1;
212 fields
[3].out_value
= &nr_w_buf
;
213 fields
[3].out_mask
= NULL
;
214 fields
[3].in_value
= NULL
;
215 fields
[3].in_check_value
= NULL
;
216 fields
[3].in_check_mask
= NULL
;
217 fields
[3].in_handler
= NULL
;
218 fields
[3].in_handler_priv
= NULL
;
220 jtag_add_dr_scan(4, fields
, -1, NULL
);
222 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
223 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
229 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
231 armv4_5_common_t
*armv4_5
= target
->arch_info
;
232 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
233 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
234 scan_field_t fields
[4];
235 u8 access_type_buf
= 0; /* interpreted access */
236 u8 reg_addr_buf
= 0x0;
238 u8 cp15_opcode_buf
[4];
240 jtag_add_end_state(TAP_RTI
);
241 arm_jtag_scann(jtag_info
, 0xf);
242 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
244 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
246 fields
[0].device
= jtag_info
->chain_pos
;
247 fields
[0].num_bits
= 1;
248 fields
[0].out_value
= &access_type_buf
;
249 fields
[0].out_mask
= NULL
;
250 fields
[0].in_value
= NULL
;
251 fields
[0].in_check_value
= NULL
;
252 fields
[0].in_check_mask
= NULL
;
253 fields
[0].in_handler
= NULL
;
254 fields
[0].in_handler_priv
= NULL
;
256 fields
[1].device
= jtag_info
->chain_pos
;
257 fields
[1].num_bits
= 32;
258 fields
[1].out_value
= cp15_opcode_buf
;
259 fields
[1].out_mask
= NULL
;
260 fields
[1].in_value
= NULL
;
261 fields
[1].in_check_value
= NULL
;
262 fields
[1].in_check_mask
= NULL
;
263 fields
[1].in_handler
= NULL
;
264 fields
[1].in_handler_priv
= NULL
;
266 fields
[2].device
= jtag_info
->chain_pos
;
267 fields
[2].num_bits
= 6;
268 fields
[2].out_value
= ®_addr_buf
;
269 fields
[2].out_mask
= NULL
;
270 fields
[2].in_value
= NULL
;
271 fields
[2].in_check_value
= NULL
;
272 fields
[2].in_check_mask
= NULL
;
273 fields
[2].in_handler
= NULL
;
274 fields
[2].in_handler_priv
= NULL
;
276 fields
[3].device
= jtag_info
->chain_pos
;
277 fields
[3].num_bits
= 1;
278 fields
[3].out_value
= &nr_w_buf
;
279 fields
[3].out_mask
= NULL
;
280 fields
[3].in_value
= NULL
;
281 fields
[3].in_check_value
= NULL
;
282 fields
[3].in_check_mask
= NULL
;
283 fields
[3].in_handler
= NULL
;
284 fields
[3].in_handler_priv
= NULL
;
286 jtag_add_dr_scan(4, fields
, -1, NULL
);
288 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
289 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
290 arm7_9_execute_sys_speed(target
);
292 if (jtag_execute_queue() != ERROR_OK
)
294 ERROR("failed executing JTAG queue, exiting");
301 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
303 armv4_5_common_t
*armv4_5
= target
->arch_info
;
308 /* load address into R1 */
310 arm9tdmi_write_core_regs(target
, 0x2, regs
);
312 /* read-modify-write CP15 test state register
313 * to enable interpreted access mode */
314 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
315 jtag_execute_queue();
316 cp15c15
|= 1; /* set interpret mode */
317 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
319 /* execute CP15 instruction and ARM load (reading from coprocessor) */
320 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
322 /* disable interpreted access mode */
323 cp15c15
&= ~1U; /* clear interpret mode */
324 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
326 /* retrieve value from R0 */
328 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
329 jtag_execute_queue();
331 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
332 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
335 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
336 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
341 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
344 armv4_5_common_t
*armv4_5
= target
->arch_info
;
347 /* load value, address into R0, R1 */
350 arm9tdmi_write_core_regs(target
, 0x3, regs
);
352 /* read-modify-write CP15 test state register
353 * to enable interpreted access mode */
354 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
355 jtag_execute_queue();
356 cp15c15
|= 1; /* set interpret mode */
357 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
359 /* execute CP15 instruction and ARM store (writing to coprocessor) */
360 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
362 /* disable interpreted access mode */
363 cp15c15
&= ~1U; /* set interpret mode */
364 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
366 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
367 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
370 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
371 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
376 u32
arm920t_get_ttb(target_t
*target
)
381 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
387 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
391 /* read cp15 control register */
392 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
393 jtag_execute_queue();
396 cp15_control
&= ~0x1U
;
399 cp15_control
&= ~0x4U
;
402 cp15_control
&= ~0x1000U
;
404 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
407 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
411 /* read cp15 control register */
412 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
413 jtag_execute_queue();
416 cp15_control
|= 0x1U
;
419 cp15_control
|= 0x4U
;
422 cp15_control
|= 0x1000U
;
424 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
427 void arm920t_post_debug_entry(target_t
*target
)
430 armv4_5_common_t
*armv4_5
= target
->arch_info
;
431 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
432 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
433 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
435 /* examine cp15 control reg */
436 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
437 jtag_execute_queue();
438 DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
440 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
443 /* identify caches */
444 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
445 jtag_execute_queue();
446 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
449 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
450 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
451 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
453 /* save i/d fault status and address register */
454 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
455 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
456 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
457 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
459 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
460 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
462 if (arm920t
->preserve_cache
)
464 /* read-modify-write CP15 test state register
465 * to disable I/D-cache linefills */
466 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
467 jtag_execute_queue();
469 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
473 void arm920t_pre_restore_context(target_t
*target
)
476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
477 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
478 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
479 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
481 /* restore i/d fault status and address register */
482 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
483 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
484 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
485 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
487 /* read-modify-write CP15 test state register
488 * to reenable I/D-cache linefills */
489 if (arm920t
->preserve_cache
)
491 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
492 jtag_execute_queue();
494 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
498 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
500 armv4_5_common_t
*armv4_5
= target
->arch_info
;
501 arm7_9_common_t
*arm7_9
;
502 arm9tdmi_common_t
*arm9tdmi
;
503 arm920t_common_t
*arm920t
;
505 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
510 arm7_9
= armv4_5
->arch_info
;
511 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
516 arm9tdmi
= arm7_9
->arch_info
;
517 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
522 arm920t
= arm9tdmi
->arch_info
;
523 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
528 *armv4_5_p
= armv4_5
;
530 *arm9tdmi_p
= arm9tdmi
;
531 *arm920t_p
= arm920t
;
536 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
538 armv4_5_common_t
*armv4_5
= target
->arch_info
;
539 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
540 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
541 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
545 "disabled", "enabled"
548 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
550 ERROR("BUG: called for a non-ARMv4/5 target");
554 snprintf(buf
, buf_size
,
555 "target halted in %s state due to %s, current mode: %s\n"
556 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
557 "MMU: %s, D-Cache: %s, I-Cache: %s",
558 armv4_5_state_strings
[armv4_5
->core_state
],
559 target_debug_reason_strings
[target
->debug_reason
],
560 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
561 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
562 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
563 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
564 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
565 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
570 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
574 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
579 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
582 armv4_5_common_t
*armv4_5
= target
->arch_info
;
583 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
584 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
585 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
587 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
590 if (((size
== 4) || (size
== 2)) && (count
== 1))
592 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
594 DEBUG("D-Cache enabled, writing through to main memory");
598 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
601 /* cacheable & bufferable means write-back region */
603 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
606 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
608 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
609 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
616 int arm920t_soft_reset_halt(struct target_s
*target
)
618 armv4_5_common_t
*armv4_5
= target
->arch_info
;
619 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
620 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
621 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
622 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
624 if (target
->state
== TARGET_RUNNING
)
626 target
->type
->halt(target
);
629 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
631 embeddedice_read_reg(dbg_stat
);
632 jtag_execute_queue();
635 target
->state
= TARGET_HALTED
;
637 /* SVC, ARM state, IRQ and FIQ disabled */
638 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
639 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
640 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
642 /* start fetching from 0x0 */
643 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
644 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
645 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
647 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
648 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
650 arm920t_disable_mmu_caches(target
, 1, 1, 1);
651 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
652 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
653 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
655 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
660 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
662 arm9tdmi_init_target(cmd_ctx
, target
);
674 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
676 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
677 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
679 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
681 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
683 arm9tdmi
->arch_info
= arm920t
;
684 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
686 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
687 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
689 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
690 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
691 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
692 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
693 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
694 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
695 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
696 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
698 /* disabling linefills leads to lockups, so keep them enabled for now
699 * this doesn't affect correctness, but might affect timing issues, if
700 * important data is evicted from the cache during the debug session
702 arm920t
->preserve_cache
= 0;
704 /* override hw single-step capability from ARM9TDMI */
705 arm7_9
->has_single_step
= 1;
710 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
713 char *variant
= NULL
;
714 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
718 ERROR("'target arm920t' requires at least one additional argument");
722 chain_pos
= strtoul(args
[3], NULL
, 0);
727 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
729 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
734 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
737 command_t
*arm920t_cmd
;
740 retval
= arm9tdmi_register_commands(cmd_ctx
);
742 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
744 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
745 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
746 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
747 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
749 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
750 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
751 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
753 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
754 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
755 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
757 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
758 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
763 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
765 target_t
*target
= get_current_target(cmd_ctx
);
766 armv4_5_common_t
*armv4_5
;
767 arm7_9_common_t
*arm7_9
;
768 arm9tdmi_common_t
*arm9tdmi
;
769 arm920t_common_t
*arm920t
;
770 arm_jtag_t
*jtag_info
;
772 u32 cp15_ctrl
, cp15_ctrl_saved
;
775 u32 C15_C_D_Ind
, C15_C_I_Ind
;
778 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
783 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
787 if ((output
= fopen(args
[0], "w")) == NULL
)
789 DEBUG("error opening cache content file");
793 for (i
= 0; i
< 16; i
++)
794 regs_p
[i
] = ®s
[i
];
796 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
798 command_print(cmd_ctx
, "current target isn't an ARM920t target");
802 jtag_info
= &arm7_9
->jtag_info
;
804 /* disable MMU and Caches */
805 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
806 jtag_execute_queue();
807 cp15_ctrl_saved
= cp15_ctrl
;
808 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
809 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
811 /* read CP15 test state register */
812 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
813 jtag_execute_queue();
815 /* read DCache content */
816 fprintf(output
, "DCache:\n");
818 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
819 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
821 fprintf(output
, "\nsegment: %i\n----------", segment
);
823 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
824 regs
[0] = 0x0 | (segment
<< 5);
825 arm9tdmi_write_core_regs(target
, 0x1, regs
);
827 /* set interpret mode */
829 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
831 /* D CAM Read, loads current victim into C15.C.D.Ind */
832 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
834 /* read current victim */
835 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
837 /* clear interpret mode */
839 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
841 for (index
= 0; index
< 64; index
++)
843 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
844 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
845 arm9tdmi_write_core_regs(target
, 0x1, regs
);
847 /* set interpret mode */
849 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
851 /* Write DCache victim */
852 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
855 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
858 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
860 /* clear interpret mode */
862 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
864 /* read D RAM and CAM content */
865 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
866 jtag_execute_queue();
868 d_cache
[segment
][index
].cam
= regs
[9];
871 regs
[9] &= 0xfffffffe;
872 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
874 for (i
= 1; i
< 9; i
++)
876 d_cache
[segment
][index
].data
[i
] = regs
[i
];
877 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
882 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
883 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
884 arm9tdmi_write_core_regs(target
, 0x1, regs
);
886 /* set interpret mode */
888 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
890 /* Write DCache victim */
891 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
893 /* clear interpret mode */
895 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
898 /* read ICache content */
899 fprintf(output
, "ICache:\n");
901 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
902 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
904 fprintf(output
, "segment: %i\n----------", segment
);
906 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
907 regs
[0] = 0x0 | (segment
<< 5);
908 arm9tdmi_write_core_regs(target
, 0x1, regs
);
910 /* set interpret mode */
912 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
914 /* I CAM Read, loads current victim into C15.C.I.Ind */
915 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
917 /* read current victim */
918 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
920 /* clear interpret mode */
922 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
924 for (index
= 0; index
< 64; index
++)
926 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
927 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
928 arm9tdmi_write_core_regs(target
, 0x1, regs
);
930 /* set interpret mode */
932 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
934 /* Write ICache victim */
935 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
938 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
941 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
943 /* clear interpret mode */
945 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
947 /* read I RAM and CAM content */
948 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
949 jtag_execute_queue();
951 i_cache
[segment
][index
].cam
= regs
[9];
954 regs
[9] &= 0xfffffffe;
955 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
957 for (i
= 1; i
< 9; i
++)
959 i_cache
[segment
][index
].data
[i
] = regs
[i
];
960 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
966 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
967 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
968 arm9tdmi_write_core_regs(target
, 0x1, regs
);
970 /* set interpret mode */
972 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
974 /* Write ICache victim */
975 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
977 /* clear interpret mode */
979 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
982 /* restore CP15 MMU and Cache settings */
983 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
985 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
989 /* mark registers dirty */
990 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
991 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
992 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= 1;
993 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= 1;
994 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= 1;
995 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= 1;
996 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= 1;
997 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= 1;
998 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= 1;
999 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= 1;
1004 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1006 target_t
*target
= get_current_target(cmd_ctx
);
1007 armv4_5_common_t
*armv4_5
;
1008 arm7_9_common_t
*arm7_9
;
1009 arm9tdmi_common_t
*arm9tdmi
;
1010 arm920t_common_t
*arm920t
;
1011 arm_jtag_t
*jtag_info
;
1013 u32 cp15_ctrl
, cp15_ctrl_saved
;
1018 u32 Dlockdown
, Ilockdown
;
1019 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1024 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1028 if ((output
= fopen(args
[0], "w")) == NULL
)
1030 DEBUG("error opening mmu content file");
1034 for (i
= 0; i
< 16; i
++)
1035 regs_p
[i
] = ®s
[i
];
1037 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1039 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1043 jtag_info
= &arm7_9
->jtag_info
;
1045 /* disable MMU and Caches */
1046 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1047 jtag_execute_queue();
1048 cp15_ctrl_saved
= cp15_ctrl
;
1049 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1050 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1052 /* read CP15 test state register */
1053 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1054 jtag_execute_queue();
1056 /* prepare reading D TLB content
1059 /* set interpret mode */
1061 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1063 /* Read D TLB lockdown */
1064 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1066 /* clear interpret mode */
1068 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1070 /* read D TLB lockdown stored to r1 */
1071 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1072 jtag_execute_queue();
1073 Dlockdown
= regs
[1];
1075 for (victim
= 0; victim
< 64; victim
+= 8)
1077 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1078 * base remains unchanged, victim goes through entries 0 to 63 */
1079 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1080 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1082 /* set interpret mode */
1084 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1086 /* Write D TLB lockdown */
1087 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1089 /* Read D TLB CAM */
1090 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1092 /* clear interpret mode */
1094 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1096 /* read D TLB CAM content stored to r2-r9 */
1097 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1098 jtag_execute_queue();
1100 for (i
= 0; i
< 8; i
++)
1101 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1104 for (victim
= 0; victim
< 64; victim
++)
1106 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1107 * base remains unchanged, victim goes through entries 0 to 63 */
1108 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1109 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1111 /* set interpret mode */
1113 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1115 /* Write D TLB lockdown */
1116 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1118 /* Read D TLB RAM1 */
1119 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1121 /* Read D TLB RAM2 */
1122 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1124 /* clear interpret mode */
1126 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1128 /* read D TLB RAM content stored to r2 and r3 */
1129 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1130 jtag_execute_queue();
1132 d_tlb
[victim
].ram1
= regs
[2];
1133 d_tlb
[victim
].ram2
= regs
[3];
1136 /* restore D TLB lockdown */
1137 regs
[1] = Dlockdown
;
1138 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1140 /* Write D TLB lockdown */
1141 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1143 /* prepare reading I TLB content
1146 /* set interpret mode */
1148 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1150 /* Read I TLB lockdown */
1151 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1153 /* clear interpret mode */
1155 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1157 /* read I TLB lockdown stored to r1 */
1158 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1159 jtag_execute_queue();
1160 Ilockdown
= regs
[1];
1162 for (victim
= 0; victim
< 64; victim
+= 8)
1164 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1165 * base remains unchanged, victim goes through entries 0 to 63 */
1166 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1167 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1169 /* set interpret mode */
1171 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1173 /* Write I TLB lockdown */
1174 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1176 /* Read I TLB CAM */
1177 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1179 /* clear interpret mode */
1181 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1183 /* read I TLB CAM content stored to r2-r9 */
1184 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1185 jtag_execute_queue();
1187 for (i
= 0; i
< 8; i
++)
1188 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1191 for (victim
= 0; victim
< 64; victim
++)
1193 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1194 * base remains unchanged, victim goes through entries 0 to 63 */
1195 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1196 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1198 /* set interpret mode */
1200 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1202 /* Write I TLB lockdown */
1203 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1205 /* Read I TLB RAM1 */
1206 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1208 /* Read I TLB RAM2 */
1209 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1211 /* clear interpret mode */
1213 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1215 /* read I TLB RAM content stored to r2 and r3 */
1216 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1217 jtag_execute_queue();
1219 i_tlb
[victim
].ram1
= regs
[2];
1220 i_tlb
[victim
].ram2
= regs
[3];
1223 /* restore I TLB lockdown */
1224 regs
[1] = Ilockdown
;
1225 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1227 /* Write I TLB lockdown */
1228 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1230 /* restore CP15 MMU and Cache settings */
1231 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1233 /* output data to file */
1234 fprintf(output
, "D TLB content:\n");
1235 for (i
= 0; i
< 64; i
++)
1237 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1240 fprintf(output
, "\n\nI TLB content:\n");
1241 for (i
= 0; i
< 64; i
++)
1243 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1246 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1250 /* mark registers dirty */
1251 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
1252 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
1253 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= 1;
1254 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= 1;
1255 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= 1;
1256 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= 1;
1257 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= 1;
1258 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= 1;
1259 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= 1;
1260 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= 1;
1264 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1267 target_t
*target
= get_current_target(cmd_ctx
);
1268 armv4_5_common_t
*armv4_5
;
1269 arm7_9_common_t
*arm7_9
;
1270 arm9tdmi_common_t
*arm9tdmi
;
1271 arm920t_common_t
*arm920t
;
1272 arm_jtag_t
*jtag_info
;
1274 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1276 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1280 jtag_info
= &arm7_9
->jtag_info
;
1282 if (target
->state
!= TARGET_HALTED
)
1284 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1288 /* one or more argument, access a single register (write if second argument is given */
1291 int address
= strtoul(args
[0], NULL
, 0);
1296 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1298 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1301 jtag_execute_queue();
1303 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1307 u32 value
= strtoul(args
[1], NULL
, 0);
1308 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1310 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1313 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1320 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1323 target_t
*target
= get_current_target(cmd_ctx
);
1324 armv4_5_common_t
*armv4_5
;
1325 arm7_9_common_t
*arm7_9
;
1326 arm9tdmi_common_t
*arm9tdmi
;
1327 arm920t_common_t
*arm920t
;
1328 arm_jtag_t
*jtag_info
;
1330 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1332 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1336 jtag_info
= &arm7_9
->jtag_info
;
1338 if (target
->state
!= TARGET_HALTED
)
1340 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1344 /* one or more argument, access a single register (write if second argument is given */
1347 u32 opcode
= strtoul(args
[0], NULL
, 0);
1352 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1354 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1358 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1362 u32 value
= strtoul(args
[1], NULL
, 0);
1363 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1365 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1368 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1372 u32 value
= strtoul(args
[1], NULL
, 0);
1373 u32 address
= strtoul(args
[2], NULL
, 0);
1374 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1376 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1379 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1384 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1390 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1392 target_t
*target
= get_current_target(cmd_ctx
);
1393 armv4_5_common_t
*armv4_5
;
1394 arm7_9_common_t
*arm7_9
;
1395 arm9tdmi_common_t
*arm9tdmi
;
1396 arm920t_common_t
*arm920t
;
1398 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1400 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1404 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1407 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1409 target_t
*target
= get_current_target(cmd_ctx
);
1410 armv4_5_common_t
*armv4_5
;
1411 arm7_9_common_t
*arm7_9
;
1412 arm9tdmi_common_t
*arm9tdmi
;
1413 arm920t_common_t
*arm920t
;
1414 arm_jtag_t
*jtag_info
;
1416 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1418 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1422 jtag_info
= &arm7_9
->jtag_info
;
1424 if (target
->state
!= TARGET_HALTED
)
1426 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1430 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1433 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1435 target_t
*target
= get_current_target(cmd_ctx
);
1436 armv4_5_common_t
*armv4_5
;
1437 arm7_9_common_t
*arm7_9
;
1438 arm9tdmi_common_t
*arm9tdmi
;
1439 arm920t_common_t
*arm920t
;
1440 arm_jtag_t
*jtag_info
;
1442 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1444 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1448 jtag_info
= &arm7_9
->jtag_info
;
1450 if (target
->state
!= TARGET_HALTED
)
1452 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1456 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1459 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1461 target_t
*target
= get_current_target(cmd_ctx
);
1462 armv4_5_common_t
*armv4_5
;
1463 arm7_9_common_t
*arm7_9
;
1464 arm9tdmi_common_t
*arm9tdmi
;
1465 arm920t_common_t
*arm920t
;
1466 arm_jtag_t
*jtag_info
;
1468 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1470 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1474 jtag_info
= &arm7_9
->jtag_info
;
1476 if (target
->state
!= TARGET_HALTED
)
1478 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1482 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)