1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include <helper/time_support.h>
26 #include "target_type.h"
28 #include "arm_opcodes.h"
32 * For information about the ARM920T, see ARM DDI 0151C especially
33 * Chapter 9 about debug support, which shows how to manipulate each
34 * of the different scan chains:
36 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
37 * 1 ... debugging; watchpoint and breakpoint status, etc; also
38 * MMU and cache access in conjunction with scan chain 15
40 * 3 ... external boundary scan (SoC-specific, unused here)
41 * 4 ... access to cache tag RAM
43 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
44 * "interpreted" works with a few actual MRC/MCR instructions
45 * "physical" provides register-like behaviors.
47 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
51 #define _DEBUG_INSTRUCTION_EXECUTION_
54 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
56 static int arm920t_read_cp15_physical(struct target
*target
,
57 int reg_addr
, uint32_t *value
)
59 struct arm920t_common
*arm920t
= target_to_arm920(target
);
60 struct arm_jtag
*jtag_info
;
61 struct scan_field fields
[4];
62 uint8_t access_type_buf
= 1;
63 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
66 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
68 jtag_set_end_state(TAP_IDLE
);
69 arm_jtag_scann(jtag_info
, 0xf);
70 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
72 fields
[0].tap
= jtag_info
->tap
;
73 fields
[0].num_bits
= 1;
74 fields
[0].out_value
= &access_type_buf
;
75 fields
[0].in_value
= NULL
;
77 fields
[1].tap
= jtag_info
->tap
;
78 fields
[1].num_bits
= 32;
79 fields
[1].out_value
= NULL
;
80 fields
[1].in_value
= NULL
;
82 fields
[2].tap
= jtag_info
->tap
;
83 fields
[2].num_bits
= 6;
84 fields
[2].out_value
= ®_addr_buf
;
85 fields
[2].in_value
= NULL
;
87 fields
[3].tap
= jtag_info
->tap
;
88 fields
[3].num_bits
= 1;
89 fields
[3].out_value
= &nr_w_buf
;
90 fields
[3].in_value
= NULL
;
92 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
94 fields
[1].in_value
= (uint8_t *)value
;
96 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
98 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
100 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
101 jtag_execute_queue();
102 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
108 static int arm920t_write_cp15_physical(struct target
*target
,
109 int reg_addr
, uint32_t value
)
111 struct arm920t_common
*arm920t
= target_to_arm920(target
);
112 struct arm_jtag
*jtag_info
;
113 struct scan_field fields
[4];
114 uint8_t access_type_buf
= 1;
115 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
116 uint8_t nr_w_buf
= 1;
117 uint8_t value_buf
[4];
119 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
121 buf_set_u32(value_buf
, 0, 32, value
);
123 jtag_set_end_state(TAP_IDLE
);
124 arm_jtag_scann(jtag_info
, 0xf);
125 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
127 fields
[0].tap
= jtag_info
->tap
;
128 fields
[0].num_bits
= 1;
129 fields
[0].out_value
= &access_type_buf
;
130 fields
[0].in_value
= NULL
;
132 fields
[1].tap
= jtag_info
->tap
;
133 fields
[1].num_bits
= 32;
134 fields
[1].out_value
= value_buf
;
135 fields
[1].in_value
= NULL
;
137 fields
[2].tap
= jtag_info
->tap
;
138 fields
[2].num_bits
= 6;
139 fields
[2].out_value
= ®_addr_buf
;
140 fields
[2].in_value
= NULL
;
142 fields
[3].tap
= jtag_info
->tap
;
143 fields
[3].num_bits
= 1;
144 fields
[3].out_value
= &nr_w_buf
;
145 fields
[3].in_value
= NULL
;
147 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
149 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
150 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
156 static int arm920t_execute_cp15(struct target
*target
, uint32_t cp15_opcode
,
160 struct arm920t_common
*arm920t
= target_to_arm920(target
);
161 struct arm_jtag
*jtag_info
;
162 struct scan_field fields
[4];
163 uint8_t access_type_buf
= 0; /* interpreted access */
164 uint8_t reg_addr_buf
= 0x0;
165 uint8_t nr_w_buf
= 0;
166 uint8_t cp15_opcode_buf
[4];
168 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
170 jtag_set_end_state(TAP_IDLE
);
171 arm_jtag_scann(jtag_info
, 0xf);
172 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
174 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
176 fields
[0].tap
= jtag_info
->tap
;
177 fields
[0].num_bits
= 1;
178 fields
[0].out_value
= &access_type_buf
;
179 fields
[0].in_value
= NULL
;
181 fields
[1].tap
= jtag_info
->tap
;
182 fields
[1].num_bits
= 32;
183 fields
[1].out_value
= cp15_opcode_buf
;
184 fields
[1].in_value
= NULL
;
186 fields
[2].tap
= jtag_info
->tap
;
187 fields
[2].num_bits
= 6;
188 fields
[2].out_value
= ®_addr_buf
;
189 fields
[2].in_value
= NULL
;
191 fields
[3].tap
= jtag_info
->tap
;
192 fields
[3].num_bits
= 1;
193 fields
[3].out_value
= &nr_w_buf
;
194 fields
[3].in_value
= NULL
;
196 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
198 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
199 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
200 retval
= arm7_9_execute_sys_speed(target
);
201 if (retval
!= ERROR_OK
)
204 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
206 LOG_ERROR("failed executing JTAG queue");
213 static int arm920t_read_cp15_interpreted(struct target
*target
,
214 uint32_t cp15_opcode
, uint32_t address
, uint32_t *value
)
216 struct arm
*armv4_5
= target_to_arm(target
);
219 uint32_t cp15c15
= 0x0;
220 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
222 /* load address into R1 */
224 arm9tdmi_write_core_regs(target
, 0x2, regs
);
226 /* read-modify-write CP15 test state register
227 * to enable interpreted access mode */
228 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
229 jtag_execute_queue();
230 cp15c15
|= 1; /* set interpret mode */
231 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
233 /* execute CP15 instruction and ARM load (reading from coprocessor) */
234 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
236 /* disable interpreted access mode */
237 cp15c15
&= ~1U; /* clear interpret mode */
238 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
240 /* retrieve value from R0 */
242 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
243 jtag_execute_queue();
245 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
246 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
249 if (!is_arm_mode(armv4_5
->core_mode
))
259 int arm920t_write_cp15_interpreted(struct target
*target
,
260 uint32_t cp15_opcode
, uint32_t value
, uint32_t address
)
262 uint32_t cp15c15
= 0x0;
263 struct arm
*armv4_5
= target_to_arm(target
);
265 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
267 /* load value, address into R0, R1 */
270 arm9tdmi_write_core_regs(target
, 0x3, regs
);
272 /* read-modify-write CP15 test state register
273 * to enable interpreted access mode */
274 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
275 jtag_execute_queue();
276 cp15c15
|= 1; /* set interpret mode */
277 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
279 /* execute CP15 instruction and ARM store (writing to coprocessor) */
280 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
282 /* disable interpreted access mode */
283 cp15c15
&= ~1U; /* set interpret mode */
284 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
290 if (!is_arm_mode(armv4_5
->core_mode
))
300 uint32_t arm920t_get_ttb(struct target
*target
)
305 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
312 void arm920t_disable_mmu_caches(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
)
314 uint32_t cp15_control
;
316 /* read cp15 control register */
317 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
318 jtag_execute_queue();
321 cp15_control
&= ~0x1U
;
324 cp15_control
&= ~0x4U
;
327 cp15_control
&= ~0x1000U
;
329 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
333 void arm920t_enable_mmu_caches(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
)
335 uint32_t cp15_control
;
337 /* read cp15 control register */
338 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
339 jtag_execute_queue();
342 cp15_control
|= 0x1U
;
345 cp15_control
|= 0x4U
;
348 cp15_control
|= 0x1000U
;
350 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
354 void arm920t_post_debug_entry(struct target
*target
)
357 struct arm920t_common
*arm920t
= target_to_arm920(target
);
359 /* examine cp15 control reg */
360 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
361 jtag_execute_queue();
362 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm920t
->cp15_control_reg
);
364 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
366 uint32_t cache_type_reg
;
367 /* identify caches */
368 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
369 jtag_execute_queue();
370 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
373 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
374 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
375 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
377 /* save i/d fault status and address register */
378 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
379 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
380 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
381 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
383 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
", I FAR: 0x%8.8" PRIx32
"",
384 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
386 if (arm920t
->preserve_cache
)
388 /* read-modify-write CP15 test state register
389 * to disable I/D-cache linefills */
390 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
391 jtag_execute_queue();
393 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
398 void arm920t_pre_restore_context(struct target
*target
)
401 struct arm920t_common
*arm920t
= target_to_arm920(target
);
403 /* restore i/d fault status and address register */
404 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
405 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
406 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
407 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
409 /* read-modify-write CP15 test state register
410 * to reenable I/D-cache linefills */
411 if (arm920t
->preserve_cache
)
413 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
414 jtag_execute_queue();
416 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
420 static const char arm920_not
[] = "target is not an ARM920";
422 static int arm920t_verify_pointer(struct command_context
*cmd_ctx
,
423 struct arm920t_common
*arm920t
)
425 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
) {
426 command_print(cmd_ctx
, arm920_not
);
427 return ERROR_TARGET_INVALID
;
433 /** Logs summary of ARM920 state for a halted target. */
434 int arm920t_arch_state(struct target
*target
)
436 static const char *state
[] =
438 "disabled", "enabled"
441 struct arm920t_common
*arm920t
= target_to_arm920(target
);
444 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
446 LOG_ERROR("BUG: %s", arm920_not
);
447 return ERROR_TARGET_INVALID
;
450 armv4_5
= &arm920t
->arm7_9_common
.armv4_5_common
;
452 arm_arch_state(target
);
453 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
454 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
455 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
456 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
461 static int arm920_mmu(struct target
*target
, int *enabled
)
463 if (target
->state
!= TARGET_HALTED
) {
464 LOG_ERROR("%s: target not halted", __func__
);
465 return ERROR_TARGET_INVALID
;
468 *enabled
= target_to_arm920(target
)->armv4_5_mmu
.mmu_enabled
;
472 static int arm920_virt2phys(struct target
*target
,
473 uint32_t virt
, uint32_t *phys
)
475 /** @todo Implement this! */
476 LOG_ERROR("%s: not implemented", __func__
);
480 /** Reads a buffer, in the specified word size, with current MMU settings. */
481 int arm920t_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
485 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
491 static int arm920t_read_phys_memory(struct target
*target
,
492 uint32_t address
, uint32_t size
,
493 uint32_t count
, uint8_t *buffer
)
495 struct arm920t_common
*arm920t
= target_to_arm920(target
);
497 return armv4_5_mmu_read_physical(target
, &arm920t
->armv4_5_mmu
,
498 address
, size
, count
, buffer
);
501 static int arm920t_write_phys_memory(struct target
*target
,
502 uint32_t address
, uint32_t size
,
503 uint32_t count
, uint8_t *buffer
)
505 struct arm920t_common
*arm920t
= target_to_arm920(target
);
507 return armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
,
508 address
, size
, count
, buffer
);
512 /** Writes a buffer, in the specified word size, with current MMU settings. */
513 int arm920t_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
517 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
520 /* This fn is used to write breakpoints, so we need to make sure
521 * that the data cache is flushed and the instruction cache is
524 if (((size
== 4) || (size
== 2)) && (count
== 1))
526 struct arm920t_common
*arm920t
= target_to_arm920(target
);
528 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
530 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
531 /* MCR p15,0,Rd,c7,c10,2 */
532 retval
= arm920t_write_cp15_interpreted(target
, 0xee070f5e, 0x0, address
);
533 if (retval
!= ERROR_OK
)
537 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
539 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
540 retval
= arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
541 if (retval
!= ERROR_OK
)
550 int arm920t_soft_reset_halt(struct target
*target
)
552 int retval
= ERROR_OK
;
553 struct arm920t_common
*arm920t
= target_to_arm920(target
);
554 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
555 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
556 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
558 if ((retval
= target_halt(target
)) != ERROR_OK
)
563 long long then
= timeval_ms();
565 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
567 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
569 embeddedice_read_reg(dbg_stat
);
570 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
578 if (debug_level
>= 3)
580 /* do not eat all CPU, time out after 1 se*/
589 LOG_ERROR("Failed to halt CPU after 1 sec");
590 return ERROR_TARGET_TIMEOUT
;
593 target
->state
= TARGET_HALTED
;
595 /* SVC, ARM state, IRQ and FIQ disabled */
598 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
601 arm_set_cpsr(armv4_5
, cpsr
);
602 armv4_5
->cpsr
->dirty
= 1;
604 /* start fetching from 0x0 */
605 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
606 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
607 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
609 arm920t_disable_mmu_caches(target
, 1, 1, 1);
610 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
611 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
612 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
614 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
622 /* FIXME remove forward decls */
623 static int arm920t_mrc(struct target
*target
, int cpnum
,
624 uint32_t op1
, uint32_t op2
,
625 uint32_t CRn
, uint32_t CRm
,
627 static int arm920t_mcr(struct target
*target
, int cpnum
,
628 uint32_t op1
, uint32_t op2
,
629 uint32_t CRn
, uint32_t CRm
,
632 int arm920t_init_arch_info(struct target
*target
, struct arm920t_common
*arm920t
, struct jtag_tap
*tap
)
634 struct arm7_9_common
*arm7_9
= &arm920t
->arm7_9_common
;
636 arm7_9
->armv4_5_common
.mrc
= arm920t_mrc
;
637 arm7_9
->armv4_5_common
.mcr
= arm920t_mcr
;
639 /* initialize arm7/arm9 specific info (including armv4_5) */
640 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
642 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
644 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
645 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
647 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
648 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
649 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
650 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
651 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
652 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
653 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
654 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
656 /* disabling linefills leads to lockups, so keep them enabled for now
657 * this doesn't affect correctness, but might affect timing issues, if
658 * important data is evicted from the cache during the debug session
660 arm920t
->preserve_cache
= 0;
662 /* override hw single-step capability from ARM9TDMI */
663 arm7_9
->has_single_step
= 1;
668 static int arm920t_target_create(struct target
*target
, Jim_Interp
*interp
)
670 struct arm920t_common
*arm920t
= calloc(1,sizeof(struct arm920t_common
));
672 return arm920t_init_arch_info(target
, arm920t
, target
->tap
);
675 COMMAND_HANDLER(arm920t_handle_read_cache_command
)
677 int retval
= ERROR_OK
;
678 struct target
*target
= get_current_target(CMD_CTX
);
679 struct arm920t_common
*arm920t
= target_to_arm920(target
);
680 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
681 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
683 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
685 uint32_t *regs_p
[16];
686 uint32_t C15_C_D_Ind
, C15_C_I_Ind
;
689 struct arm920t_cache_line d_cache
[8][64], i_cache
[8][64];
693 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
694 if (retval
!= ERROR_OK
)
699 command_print(CMD_CTX
, "usage: arm920t read_cache <filename>");
703 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
705 LOG_DEBUG("error opening cache content file");
709 for (i
= 0; i
< 16; i
++)
710 regs_p
[i
] = ®s
[i
];
712 /* disable MMU and Caches */
713 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
714 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
718 cp15_ctrl_saved
= cp15_ctrl
;
719 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
720 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
722 /* read CP15 test state register */
723 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
724 jtag_execute_queue();
726 /* read DCache content */
727 fprintf(output
, "DCache:\n");
729 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
730 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
732 fprintf(output
, "\nsegment: %i\n----------", segment
);
734 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
735 regs
[0] = 0x0 | (segment
<< 5);
736 arm9tdmi_write_core_regs(target
, 0x1, regs
);
738 /* set interpret mode */
740 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
742 /* D CAM Read, loads current victim into C15.C.D.Ind */
743 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
745 /* read current victim */
746 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
748 /* clear interpret mode */
750 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
752 for (index
= 0; index
< 64; index
++)
754 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
755 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
756 arm9tdmi_write_core_regs(target
, 0x1, regs
);
758 /* set interpret mode */
760 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
762 /* Write DCache victim */
763 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
766 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
769 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
771 /* clear interpret mode */
773 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
775 /* read D RAM and CAM content */
776 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
777 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
782 d_cache
[segment
][index
].cam
= regs
[9];
785 regs
[9] &= 0xfffffffe;
786 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
788 for (i
= 1; i
< 9; i
++)
790 d_cache
[segment
][index
].data
[i
] = regs
[i
];
791 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
796 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
797 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
798 arm9tdmi_write_core_regs(target
, 0x1, regs
);
800 /* set interpret mode */
802 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
804 /* Write DCache victim */
805 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
807 /* clear interpret mode */
809 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
812 /* read ICache content */
813 fprintf(output
, "ICache:\n");
815 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
816 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
818 fprintf(output
, "segment: %i\n----------", segment
);
820 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
821 regs
[0] = 0x0 | (segment
<< 5);
822 arm9tdmi_write_core_regs(target
, 0x1, regs
);
824 /* set interpret mode */
826 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
828 /* I CAM Read, loads current victim into C15.C.I.Ind */
829 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
831 /* read current victim */
832 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
834 /* clear interpret mode */
836 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
838 for (index
= 0; index
< 64; index
++)
840 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
841 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
842 arm9tdmi_write_core_regs(target
, 0x1, regs
);
844 /* set interpret mode */
846 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
848 /* Write ICache victim */
849 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
852 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
855 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
857 /* clear interpret mode */
859 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
861 /* read I RAM and CAM content */
862 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
863 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
868 i_cache
[segment
][index
].cam
= regs
[9];
871 regs
[9] &= 0xfffffffe;
872 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
874 for (i
= 1; i
< 9; i
++)
876 i_cache
[segment
][index
].data
[i
] = regs
[i
];
877 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
881 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
882 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
883 arm9tdmi_write_core_regs(target
, 0x1, regs
);
885 /* set interpret mode */
887 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
889 /* Write ICache victim */
890 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
892 /* clear interpret mode */
894 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
897 /* restore CP15 MMU and Cache settings */
898 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
900 command_print(CMD_CTX
, "cache content successfully output to %s", CMD_ARGV
[0]);
904 if (!is_arm_mode(armv4_5
->core_mode
))
907 /* force writeback of the valid data */
908 r
= armv4_5
->core_cache
->reg_list
;
909 r
[0].dirty
= r
[0].valid
;
910 r
[1].dirty
= r
[1].valid
;
911 r
[2].dirty
= r
[2].valid
;
912 r
[3].dirty
= r
[3].valid
;
913 r
[4].dirty
= r
[4].valid
;
914 r
[5].dirty
= r
[5].valid
;
915 r
[6].dirty
= r
[6].valid
;
916 r
[7].dirty
= r
[7].valid
;
918 r
= arm_reg_current(armv4_5
, 8);
921 r
= arm_reg_current(armv4_5
, 9);
927 COMMAND_HANDLER(arm920t_handle_read_mmu_command
)
929 int retval
= ERROR_OK
;
930 struct target
*target
= get_current_target(CMD_CTX
);
931 struct arm920t_common
*arm920t
= target_to_arm920(target
);
932 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
933 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
935 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
937 uint32_t *regs_p
[16];
940 uint32_t Dlockdown
, Ilockdown
;
941 struct arm920t_tlb_entry d_tlb
[64], i_tlb
[64];
945 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
946 if (retval
!= ERROR_OK
)
951 command_print(CMD_CTX
, "usage: arm920t read_mmu <filename>");
955 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
957 LOG_DEBUG("error opening mmu content file");
961 for (i
= 0; i
< 16; i
++)
962 regs_p
[i
] = ®s
[i
];
964 /* disable MMU and Caches */
965 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
966 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
970 cp15_ctrl_saved
= cp15_ctrl
;
971 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
972 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
974 /* read CP15 test state register */
975 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
976 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
981 /* prepare reading D TLB content
984 /* set interpret mode */
986 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
988 /* Read D TLB lockdown */
989 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
991 /* clear interpret mode */
993 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
995 /* read D TLB lockdown stored to r1 */
996 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
997 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1001 Dlockdown
= regs
[1];
1003 for (victim
= 0; victim
< 64; victim
+= 8)
1005 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1006 * base remains unchanged, victim goes through entries 0 to 63 */
1007 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1008 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1010 /* set interpret mode */
1012 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1014 /* Write D TLB lockdown */
1015 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1017 /* Read D TLB CAM */
1018 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1020 /* clear interpret mode */
1022 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1024 /* read D TLB CAM content stored to r2-r9 */
1025 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1026 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1031 for (i
= 0; i
< 8; i
++)
1032 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1035 for (victim
= 0; victim
< 64; victim
++)
1037 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1038 * base remains unchanged, victim goes through entries 0 to 63 */
1039 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1040 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1042 /* set interpret mode */
1044 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1046 /* Write D TLB lockdown */
1047 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1049 /* Read D TLB RAM1 */
1050 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1052 /* Read D TLB RAM2 */
1053 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1055 /* clear interpret mode */
1057 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1059 /* read D TLB RAM content stored to r2 and r3 */
1060 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1061 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1066 d_tlb
[victim
].ram1
= regs
[2];
1067 d_tlb
[victim
].ram2
= regs
[3];
1070 /* restore D TLB lockdown */
1071 regs
[1] = Dlockdown
;
1072 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1074 /* Write D TLB lockdown */
1075 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1077 /* prepare reading I TLB content
1080 /* set interpret mode */
1082 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1084 /* Read I TLB lockdown */
1085 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1087 /* clear interpret mode */
1089 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1091 /* read I TLB lockdown stored to r1 */
1092 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1093 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1097 Ilockdown
= regs
[1];
1099 for (victim
= 0; victim
< 64; victim
+= 8)
1101 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1102 * base remains unchanged, victim goes through entries 0 to 63 */
1103 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1104 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1106 /* set interpret mode */
1108 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1110 /* Write I TLB lockdown */
1111 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1113 /* Read I TLB CAM */
1114 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1116 /* clear interpret mode */
1118 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1120 /* read I TLB CAM content stored to r2-r9 */
1121 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1122 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1127 for (i
= 0; i
< 8; i
++)
1128 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1131 for (victim
= 0; victim
< 64; victim
++)
1133 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1134 * base remains unchanged, victim goes through entries 0 to 63 */
1135 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1136 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1138 /* set interpret mode */
1140 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1142 /* Write I TLB lockdown */
1143 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1145 /* Read I TLB RAM1 */
1146 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1148 /* Read I TLB RAM2 */
1149 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1151 /* clear interpret mode */
1153 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1155 /* read I TLB RAM content stored to r2 and r3 */
1156 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1157 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1162 i_tlb
[victim
].ram1
= regs
[2];
1163 i_tlb
[victim
].ram2
= regs
[3];
1166 /* restore I TLB lockdown */
1167 regs
[1] = Ilockdown
;
1168 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1170 /* Write I TLB lockdown */
1171 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1173 /* restore CP15 MMU and Cache settings */
1174 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1176 /* output data to file */
1177 fprintf(output
, "D TLB content:\n");
1178 for (i
= 0; i
< 64; i
++)
1180 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1183 fprintf(output
, "\n\nI TLB content:\n");
1184 for (i
= 0; i
< 64; i
++)
1186 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1189 command_print(CMD_CTX
, "mmu content successfully output to %s", CMD_ARGV
[0]);
1193 if (!is_arm_mode(armv4_5
->core_mode
))
1196 /* force writeback of the valid data */
1197 r
= armv4_5
->core_cache
->reg_list
;
1198 r
[0].dirty
= r
[0].valid
;
1199 r
[1].dirty
= r
[1].valid
;
1200 r
[2].dirty
= r
[2].valid
;
1201 r
[3].dirty
= r
[3].valid
;
1202 r
[4].dirty
= r
[4].valid
;
1203 r
[5].dirty
= r
[5].valid
;
1204 r
[6].dirty
= r
[6].valid
;
1205 r
[7].dirty
= r
[7].valid
;
1207 r
= arm_reg_current(armv4_5
, 8);
1208 r
->dirty
= r
->valid
;
1210 r
= arm_reg_current(armv4_5
, 9);
1211 r
->dirty
= r
->valid
;
1216 COMMAND_HANDLER(arm920t_handle_cp15_command
)
1219 struct target
*target
= get_current_target(CMD_CTX
);
1220 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1222 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1223 if (retval
!= ERROR_OK
)
1226 if (target
->state
!= TARGET_HALTED
)
1228 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1232 /* one or more argument, access a single register (write if second argument is given */
1236 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], address
);
1241 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1243 command_print(CMD_CTX
, "couldn't access reg %i", address
);
1246 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1251 command_print(CMD_CTX
, "%i: %8.8" PRIx32
"", address
, value
);
1253 else if (CMD_ARGC
== 2)
1256 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1257 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1259 command_print(CMD_CTX
, "couldn't access reg %i", address
);
1262 command_print(CMD_CTX
, "%i: %8.8" PRIx32
"", address
, value
);
1269 COMMAND_HANDLER(arm920t_handle_cp15i_command
)
1272 struct target
*target
= get_current_target(CMD_CTX
);
1273 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1275 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1276 if (retval
!= ERROR_OK
)
1280 if (target
->state
!= TARGET_HALTED
)
1282 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1286 /* one or more argument, access a single register (write if second argument is given */
1290 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
1295 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1297 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1301 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1303 else if (CMD_ARGC
== 2)
1306 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1307 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1309 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1312 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1314 else if (CMD_ARGC
== 3)
1317 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1319 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
1320 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1322 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1325 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
" %8.8" PRIx32
"", opcode
, value
, address
);
1330 command_print(CMD_CTX
, "usage: arm920t cp15i <opcode> [value] [address]");
1336 COMMAND_HANDLER(arm920t_handle_cache_info_command
)
1339 struct target
*target
= get_current_target(CMD_CTX
);
1340 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1342 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1343 if (retval
!= ERROR_OK
)
1346 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1350 static int arm920t_mrc(struct target
*target
, int cpnum
,
1351 uint32_t op1
, uint32_t op2
,
1352 uint32_t CRn
, uint32_t CRm
,
1357 LOG_ERROR("Only cp15 is supported");
1362 return arm920t_read_cp15_interpreted(target
,
1363 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1367 static int arm920t_mcr(struct target
*target
, int cpnum
,
1368 uint32_t op1
, uint32_t op2
,
1369 uint32_t CRn
, uint32_t CRm
,
1374 LOG_ERROR("Only cp15 is supported");
1378 /* write "from" r0 */
1379 return arm920t_write_cp15_interpreted(target
,
1380 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1384 static const struct command_registration arm920t_exec_command_handlers
[] = {
1387 .handler
= arm920t_handle_cp15_command
,
1388 .mode
= COMMAND_EXEC
,
1389 .help
= "display/modify cp15 register",
1390 .usage
= "regnum [value]",
1394 .handler
= arm920t_handle_cp15i_command
,
1395 .mode
= COMMAND_EXEC
,
1396 /* prefer using less error-prone "arm mcr" or "arm mrc" */
1397 .help
= "display/modify cp15 register using ARM opcode"
1399 .usage
= "instruction [value [address]]",
1402 .name
= "cache_info",
1403 .handler
= arm920t_handle_cache_info_command
,
1404 .mode
= COMMAND_EXEC
,
1405 .help
= "display information about target caches",
1408 .name
= "read_cache",
1409 .handler
= arm920t_handle_read_cache_command
,
1410 .mode
= COMMAND_EXEC
,
1411 .help
= "dump I/D cache content to file",
1412 .usage
= "filename",
1416 .handler
= arm920t_handle_read_mmu_command
,
1417 .mode
= COMMAND_EXEC
,
1418 .help
= "dump I/D mmu content to file",
1419 .usage
= "filename",
1421 COMMAND_REGISTRATION_DONE
1423 const struct command_registration arm920t_command_handlers
[] = {
1425 .chain
= arm9tdmi_command_handlers
,
1429 .mode
= COMMAND_ANY
,
1430 .help
= "arm920t command group",
1431 .chain
= arm920t_exec_command_handlers
,
1433 COMMAND_REGISTRATION_DONE
1436 /** Holds methods for ARM920 targets. */
1437 struct target_type arm920t_target
=
1441 .poll
= arm7_9_poll
,
1442 .arch_state
= arm920t_arch_state
,
1444 .target_request_data
= arm7_9_target_request_data
,
1446 .halt
= arm7_9_halt
,
1447 .resume
= arm7_9_resume
,
1448 .step
= arm7_9_step
,
1450 .assert_reset
= arm7_9_assert_reset
,
1451 .deassert_reset
= arm7_9_deassert_reset
,
1452 .soft_reset_halt
= arm920t_soft_reset_halt
,
1454 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
1456 .read_memory
= arm920t_read_memory
,
1457 .write_memory
= arm920t_write_memory
,
1458 .read_phys_memory
= arm920t_read_phys_memory
,
1459 .write_phys_memory
= arm920t_write_phys_memory
,
1461 .virt2phys
= arm920_virt2phys
,
1463 .bulk_write_memory
= arm7_9_bulk_write_memory
,
1465 .checksum_memory
= arm_checksum_memory
,
1466 .blank_check_memory
= arm_blank_check_memory
,
1468 .run_algorithm
= armv4_5_run_algorithm
,
1470 .add_breakpoint
= arm7_9_add_breakpoint
,
1471 .remove_breakpoint
= arm7_9_remove_breakpoint
,
1472 .add_watchpoint
= arm7_9_add_watchpoint
,
1473 .remove_watchpoint
= arm7_9_remove_watchpoint
,
1475 .commands
= arm920t_command_handlers
,
1476 .target_create
= arm920t_target_create
,
1477 .init_target
= arm9tdmi_init_target
,
1478 .examine
= arm7_9_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)