1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 /* forward declarations */
46 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
47 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
49 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
50 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
51 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
52 int arm920t_soft_reset_halt(struct target_s
*target
);
54 target_type_t arm920t_target
=
59 .arch_state
= arm920t_arch_state
,
62 .resume
= arm7_9_resume
,
65 .assert_reset
= arm7_9_assert_reset
,
66 .deassert_reset
= arm7_9_deassert_reset
,
67 .soft_reset_halt
= arm920t_soft_reset_halt
,
69 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
71 .read_memory
= arm920t_read_memory
,
72 .write_memory
= arm920t_write_memory
,
73 .bulk_write_memory
= arm7_9_bulk_write_memory
,
75 .run_algorithm
= armv4_5_run_algorithm
,
77 .add_breakpoint
= arm7_9_add_breakpoint
,
78 .remove_breakpoint
= arm7_9_remove_breakpoint
,
79 .add_watchpoint
= arm7_9_add_watchpoint
,
80 .remove_watchpoint
= arm7_9_remove_watchpoint
,
82 .register_commands
= arm920t_register_commands
,
83 .target_command
= arm920t_target_command
,
84 .init_target
= arm920t_init_target
,
88 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
90 armv4_5_common_t
*armv4_5
= target
->arch_info
;
91 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
92 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
93 scan_field_t fields
[4];
94 u8 access_type_buf
= 1;
95 u8 reg_addr_buf
= reg_addr
& 0x3f;
98 jtag_add_end_state(TAP_RTI
);
99 arm_jtag_scann(jtag_info
, 0xf);
100 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
102 fields
[0].device
= jtag_info
->chain_pos
;
103 fields
[0].num_bits
= 1;
104 fields
[0].out_value
= &access_type_buf
;
105 fields
[0].out_mask
= NULL
;
106 fields
[0].in_value
= NULL
;
107 fields
[0].in_check_value
= NULL
;
108 fields
[0].in_check_mask
= NULL
;
109 fields
[0].in_handler
= NULL
;
110 fields
[0].in_handler_priv
= NULL
;
112 fields
[1].device
= jtag_info
->chain_pos
;
113 fields
[1].num_bits
= 32;
114 fields
[1].out_value
= NULL
;
115 fields
[1].out_mask
= NULL
;
116 fields
[1].in_value
= NULL
;
117 fields
[1].in_check_value
= NULL
;
118 fields
[1].in_check_mask
= NULL
;
119 fields
[1].in_handler
= NULL
;
120 fields
[1].in_handler_priv
= NULL
;
122 fields
[2].device
= jtag_info
->chain_pos
;
123 fields
[2].num_bits
= 6;
124 fields
[2].out_value
= ®_addr_buf
;
125 fields
[2].out_mask
= NULL
;
126 fields
[2].in_value
= NULL
;
127 fields
[2].in_check_value
= NULL
;
128 fields
[2].in_check_mask
= NULL
;
129 fields
[2].in_handler
= NULL
;
130 fields
[2].in_handler_priv
= NULL
;
132 fields
[3].device
= jtag_info
->chain_pos
;
133 fields
[3].num_bits
= 1;
134 fields
[3].out_value
= &nr_w_buf
;
135 fields
[3].out_mask
= NULL
;
136 fields
[3].in_value
= NULL
;
137 fields
[3].in_check_value
= NULL
;
138 fields
[3].in_check_mask
= NULL
;
139 fields
[3].in_handler
= NULL
;
140 fields
[3].in_handler_priv
= NULL
;
142 jtag_add_dr_scan(4, fields
, -1);
144 fields
[1].in_value
= (u8
*)value
;
146 jtag_add_dr_scan(4, fields
, -1);
151 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
153 armv4_5_common_t
*armv4_5
= target
->arch_info
;
154 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
155 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
156 scan_field_t fields
[4];
157 u8 access_type_buf
= 1;
158 u8 reg_addr_buf
= reg_addr
& 0x3f;
161 jtag_add_end_state(TAP_RTI
);
162 arm_jtag_scann(jtag_info
, 0xf);
163 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
165 fields
[0].device
= jtag_info
->chain_pos
;
166 fields
[0].num_bits
= 1;
167 fields
[0].out_value
= &access_type_buf
;
168 fields
[0].out_mask
= NULL
;
169 fields
[0].in_value
= NULL
;
170 fields
[0].in_check_value
= NULL
;
171 fields
[0].in_check_mask
= NULL
;
172 fields
[0].in_handler
= NULL
;
173 fields
[0].in_handler_priv
= NULL
;
175 fields
[1].device
= jtag_info
->chain_pos
;
176 fields
[1].num_bits
= 32;
177 fields
[1].out_value
= (u8
*)&value
;
178 fields
[1].out_mask
= NULL
;
179 fields
[1].in_value
= NULL
;
180 fields
[1].in_check_value
= NULL
;
181 fields
[1].in_check_mask
= NULL
;
182 fields
[1].in_handler
= NULL
;
183 fields
[1].in_handler_priv
= NULL
;
185 fields
[2].device
= jtag_info
->chain_pos
;
186 fields
[2].num_bits
= 6;
187 fields
[2].out_value
= ®_addr_buf
;
188 fields
[2].out_mask
= NULL
;
189 fields
[2].in_value
= NULL
;
190 fields
[2].in_check_value
= NULL
;
191 fields
[2].in_check_mask
= NULL
;
192 fields
[2].in_handler
= NULL
;
193 fields
[2].in_handler_priv
= NULL
;
195 fields
[3].device
= jtag_info
->chain_pos
;
196 fields
[3].num_bits
= 1;
197 fields
[3].out_value
= &nr_w_buf
;
198 fields
[3].out_mask
= NULL
;
199 fields
[3].in_value
= NULL
;
200 fields
[3].in_check_value
= NULL
;
201 fields
[3].in_check_mask
= NULL
;
202 fields
[3].in_handler
= NULL
;
203 fields
[3].in_handler_priv
= NULL
;
205 jtag_add_dr_scan(4, fields
, -1);
210 int arm920t_read_cp15_interpreted(target_t
*target
, u32 opcode
, u32
*value
)
213 scan_field_t fields
[4];
214 u8 access_type_buf
= 0; /* interpreted access */
215 u8 reg_addr_buf
= 0x0;
217 armv4_5_common_t
*armv4_5
= target
->arch_info
;
218 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
219 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
222 /* read-modify-write CP15 test state register
223 * to enable interpreted access mode */
224 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
225 jtag_execute_queue();
226 cp15c15
|= 1; /* set interpret mode */
227 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
229 jtag_add_end_state(TAP_RTI
);
230 arm_jtag_scann(jtag_info
, 0xf);
231 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
233 fields
[0].device
= jtag_info
->chain_pos
;
234 fields
[0].num_bits
= 1;
235 fields
[0].out_value
= &access_type_buf
;
236 fields
[0].out_mask
= NULL
;
237 fields
[0].in_value
= NULL
;
238 fields
[0].in_check_value
= NULL
;
239 fields
[0].in_check_mask
= NULL
;
240 fields
[0].in_handler
= NULL
;
241 fields
[0].in_handler_priv
= NULL
;
243 fields
[1].device
= jtag_info
->chain_pos
;
244 fields
[1].num_bits
= 32;
245 fields
[1].out_value
= (u8
*)&opcode
;
246 fields
[1].out_mask
= NULL
;
247 fields
[1].in_value
= NULL
;
248 fields
[1].in_check_value
= NULL
;
249 fields
[1].in_check_mask
= NULL
;
250 fields
[1].in_handler
= NULL
;
251 fields
[1].in_handler_priv
= NULL
;
253 fields
[2].device
= jtag_info
->chain_pos
;
254 fields
[2].num_bits
= 6;
255 fields
[2].out_value
= ®_addr_buf
;
256 fields
[2].out_mask
= NULL
;
257 fields
[2].in_value
= NULL
;
258 fields
[2].in_check_value
= NULL
;
259 fields
[2].in_check_mask
= NULL
;
260 fields
[2].in_handler
= NULL
;
261 fields
[2].in_handler_priv
= NULL
;
263 fields
[3].device
= jtag_info
->chain_pos
;
264 fields
[3].num_bits
= 1;
265 fields
[3].out_value
= &nr_w_buf
;
266 fields
[3].out_mask
= NULL
;
267 fields
[3].in_value
= NULL
;
268 fields
[3].in_check_value
= NULL
;
269 fields
[3].in_check_mask
= NULL
;
270 fields
[3].in_handler
= NULL
;
271 fields
[3].in_handler_priv
= NULL
;
273 jtag_add_dr_scan(4, fields
, -1);
275 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDR(0, 15), 0, NULL
, 0);
276 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
277 arm7_9_execute_sys_speed(target
);
278 jtag_execute_queue();
280 /* read-modify-write CP15 test state register
281 * to disable interpreted access mode */
282 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
283 jtag_execute_queue();
284 cp15c15
&= ~1U; /* clear interpret mode */
285 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
287 context_p
[0] = value
;
288 arm9tdmi_read_core_regs(target
, 0x1, context_p
);
289 jtag_execute_queue();
291 DEBUG("opcode: %8.8x, value: %8.8x", opcode
, *value
);
293 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
294 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= 1;
299 int arm920t_write_cp15_interpreted(target_t
*target
, u32 opcode
, u32 value
, u32 address
)
302 scan_field_t fields
[4];
303 u8 access_type_buf
= 0; /* interpreted access */
304 u8 reg_addr_buf
= 0x0;
306 armv4_5_common_t
*armv4_5
= target
->arch_info
;
307 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
308 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
314 arm9tdmi_write_core_regs(target
, 0x3, regs
);
316 /* read-modify-write CP15 test state register
317 * to enable interpreted access mode */
318 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
319 jtag_execute_queue();
320 cp15c15
|= 1; /* set interpret mode */
321 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
323 jtag_add_end_state(TAP_RTI
);
324 arm_jtag_scann(jtag_info
, 0xf);
325 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
327 fields
[0].device
= jtag_info
->chain_pos
;
328 fields
[0].num_bits
= 1;
329 fields
[0].out_value
= &access_type_buf
;
330 fields
[0].out_mask
= NULL
;
331 fields
[0].in_value
= NULL
;
332 fields
[0].in_check_value
= NULL
;
333 fields
[0].in_check_mask
= NULL
;
334 fields
[0].in_handler
= NULL
;
335 fields
[0].in_handler_priv
= NULL
;
337 fields
[1].device
= jtag_info
->chain_pos
;
338 fields
[1].num_bits
= 32;
339 fields
[1].out_value
= (u8
*)&opcode
;
340 fields
[1].out_mask
= NULL
;
341 fields
[1].in_value
= NULL
;
342 fields
[1].in_check_value
= NULL
;
343 fields
[1].in_check_mask
= NULL
;
344 fields
[1].in_handler
= NULL
;
345 fields
[1].in_handler_priv
= NULL
;
347 fields
[2].device
= jtag_info
->chain_pos
;
348 fields
[2].num_bits
= 6;
349 fields
[2].out_value
= ®_addr_buf
;
350 fields
[2].out_mask
= NULL
;
351 fields
[2].in_value
= NULL
;
352 fields
[2].in_check_value
= NULL
;
353 fields
[2].in_check_mask
= NULL
;
354 fields
[2].in_handler
= NULL
;
355 fields
[2].in_handler_priv
= NULL
;
357 fields
[3].device
= jtag_info
->chain_pos
;
358 fields
[3].num_bits
= 1;
359 fields
[3].out_value
= &nr_w_buf
;
360 fields
[3].out_mask
= NULL
;
361 fields
[3].in_value
= NULL
;
362 fields
[3].in_check_value
= NULL
;
363 fields
[3].in_check_mask
= NULL
;
364 fields
[3].in_handler
= NULL
;
365 fields
[3].in_handler_priv
= NULL
;
367 jtag_add_dr_scan(4, fields
, -1);
369 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 1), 0, NULL
, 0);
370 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
371 arm7_9_execute_sys_speed(target
);
372 jtag_execute_queue();
374 /* read-modify-write CP15 test state register
375 * to disable interpreted access mode */
376 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
377 jtag_execute_queue();
378 cp15c15
&= ~1U; /* set interpret mode */
379 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
381 DEBUG("opcode: %8.8x, value: %8.8x, address: %8.8x", opcode
, value
, address
);
386 u32
arm920t_get_ttb(target_t
*target
)
391 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, &ttb
)) != ERROR_OK
)
397 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
401 /* read cp15 control register */
402 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
403 jtag_execute_queue();
406 cp15_control
&= ~0x1U
;
409 cp15_control
&= ~0x4U
;
412 cp15_control
&= ~0x1000U
;
414 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
417 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
421 /* read cp15 control register */
422 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
423 jtag_execute_queue();
426 cp15_control
|= 0x1U
;
429 cp15_control
|= 0x4U
;
432 cp15_control
|= 0x1000U
;
434 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
437 void arm920t_post_debug_entry(target_t
*target
)
440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
441 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
442 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
443 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
445 /* examine cp15 control reg */
446 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
447 jtag_execute_queue();
448 DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
450 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
453 /* identify caches */
454 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
455 jtag_execute_queue();
456 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
459 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
460 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
461 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
463 /* save i/d fault status and address register */
464 arm920t_read_cp15_interpreted(target
, 0xee150f10, &arm920t
->d_fsr
);
465 arm920t_read_cp15_interpreted(target
, 0xee150f30, &arm920t
->i_fsr
);
466 arm920t_read_cp15_interpreted(target
, 0xee160f10, &arm920t
->d_far
);
467 arm920t_read_cp15_interpreted(target
, 0xee160f30, &arm920t
->i_far
);
469 /* read-modify-write CP15 test state register
470 * to disable I/D-cache linefills */
471 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
472 jtag_execute_queue();
474 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
478 void arm920t_pre_restore_context(target_t
*target
)
481 armv4_5_common_t
*armv4_5
= target
->arch_info
;
482 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
483 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
484 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
486 /* restore i/d fault status and address register */
487 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
488 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
489 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
490 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
492 /* read-modify-write CP15 test state register
493 * to reenable I/D-cache linefills */
494 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
495 jtag_execute_queue();
497 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
501 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
503 armv4_5_common_t
*armv4_5
= target
->arch_info
;
504 arm7_9_common_t
*arm7_9
;
505 arm9tdmi_common_t
*arm9tdmi
;
506 arm920t_common_t
*arm920t
;
508 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
513 arm7_9
= armv4_5
->arch_info
;
514 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
519 arm9tdmi
= arm7_9
->arch_info
;
520 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
525 arm920t
= arm9tdmi
->arch_info
;
526 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
531 *armv4_5_p
= armv4_5
;
533 *arm9tdmi_p
= arm9tdmi
;
534 *arm920t_p
= arm920t
;
539 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
542 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
543 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
544 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
548 "disabled", "enabled"
551 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
553 ERROR("BUG: called for a non-ARMv4/5 target");
557 snprintf(buf
, buf_size
,
558 "target halted in %s state due to %s, current mode: %s\n"
559 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
560 "MMU: %s, D-Cache: %s, I-Cache: %s",
561 armv4_5_state_strings
[armv4_5
->core_state
],
562 target_debug_reason_strings
[target
->debug_reason
],
563 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
564 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
565 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
566 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
567 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
568 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
573 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
577 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
582 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
585 armv4_5_common_t
*armv4_5
= target
->arch_info
;
586 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
587 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
588 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
590 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
593 if (((size
== 4) || (size
== 2)) && (count
== 1))
595 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
597 DEBUG("D-Cache enabled, writing through to main memory");
601 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
604 /* cacheable & bufferable means write-back region */
606 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
609 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
611 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
612 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
619 int arm920t_soft_reset_halt(struct target_s
*target
)
621 armv4_5_common_t
*armv4_5
= target
->arch_info
;
622 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
623 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
624 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
625 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
627 if (target
->state
== TARGET_RUNNING
)
629 target
->type
->halt(target
);
632 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
634 embeddedice_read_reg(dbg_stat
);
635 jtag_execute_queue();
638 target
->state
= TARGET_HALTED
;
640 /* SVC, ARM state, IRQ and FIQ disabled */
641 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
642 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
643 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
645 /* start fetching from 0x0 */
646 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
647 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
648 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
650 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
651 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
653 arm920t_disable_mmu_caches(target
, 1, 1, 1);
654 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
655 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
656 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
658 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
663 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
665 arm9tdmi_init_target(cmd_ctx
, target
);
677 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
679 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
680 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
682 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
684 arm9tdmi
->arch_info
= arm920t
;
685 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
687 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
688 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
690 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
691 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
692 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
693 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
694 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
695 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
696 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
697 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
699 arm9tdmi
->has_single_step
= 1;
704 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
707 char *variant
= NULL
;
708 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
712 ERROR("'target arm920t' requires at least one additional argument");
716 chain_pos
= strtoul(args
[3], NULL
, 0);
721 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
723 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
728 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
731 command_t
*arm920t_cmd
;
734 retval
= arm9tdmi_register_commands(cmd_ctx
);
736 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
738 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
739 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
740 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
741 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
743 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
744 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
745 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
747 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
748 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
749 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
754 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
757 target_t
*target
= get_current_target(cmd_ctx
);
758 armv4_5_common_t
*armv4_5
;
759 arm7_9_common_t
*arm7_9
;
760 arm9tdmi_common_t
*arm9tdmi
;
761 arm920t_common_t
*arm920t
;
762 arm_jtag_t
*jtag_info
;
764 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
766 command_print(cmd_ctx
, "current target isn't an ARM920t target");
770 jtag_info
= &arm7_9
->jtag_info
;
772 if (target
->state
!= TARGET_HALTED
)
774 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
778 /* one or more argument, access a single register (write if second argument is given */
781 int address
= strtoul(args
[0], NULL
, 0);
786 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
788 command_print(cmd_ctx
, "couldn't access reg %i", address
);
791 jtag_execute_queue();
793 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
797 u32 value
= strtoul(args
[1], NULL
, 0);
798 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
800 command_print(cmd_ctx
, "couldn't access reg %i", address
);
803 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
810 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
813 target_t
*target
= get_current_target(cmd_ctx
);
814 armv4_5_common_t
*armv4_5
;
815 arm7_9_common_t
*arm7_9
;
816 arm9tdmi_common_t
*arm9tdmi
;
817 arm920t_common_t
*arm920t
;
818 arm_jtag_t
*jtag_info
;
820 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
822 command_print(cmd_ctx
, "current target isn't an ARM920t target");
826 jtag_info
= &arm7_9
->jtag_info
;
828 if (target
->state
!= TARGET_HALTED
)
830 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
834 /* one or more argument, access a single register (write if second argument is given */
837 u32 opcode
= strtoul(args
[0], NULL
, 0);
842 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, &value
)) != ERROR_OK
)
844 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
848 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
852 u32 value
= strtoul(args
[1], NULL
, 0);
853 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
855 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
858 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
862 u32 value
= strtoul(args
[1], NULL
, 0);
863 u32 address
= strtoul(args
[2], NULL
, 0);
864 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
866 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
869 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
876 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
878 target_t
*target
= get_current_target(cmd_ctx
);
879 armv4_5_common_t
*armv4_5
;
880 arm7_9_common_t
*arm7_9
;
881 arm9tdmi_common_t
*arm9tdmi
;
882 arm920t_common_t
*arm920t
;
884 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
886 command_print(cmd_ctx
, "current target isn't an ARM920t target");
890 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
893 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
895 target_t
*target
= get_current_target(cmd_ctx
);
896 armv4_5_common_t
*armv4_5
;
897 arm7_9_common_t
*arm7_9
;
898 arm9tdmi_common_t
*arm9tdmi
;
899 arm920t_common_t
*arm920t
;
900 arm_jtag_t
*jtag_info
;
902 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
904 command_print(cmd_ctx
, "current target isn't an ARM920t target");
908 jtag_info
= &arm7_9
->jtag_info
;
910 if (target
->state
!= TARGET_HALTED
)
912 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
916 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
919 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
921 target_t
*target
= get_current_target(cmd_ctx
);
922 armv4_5_common_t
*armv4_5
;
923 arm7_9_common_t
*arm7_9
;
924 arm9tdmi_common_t
*arm9tdmi
;
925 arm920t_common_t
*arm920t
;
926 arm_jtag_t
*jtag_info
;
928 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
930 command_print(cmd_ctx
, "current target isn't an ARM920t target");
934 jtag_info
= &arm7_9
->jtag_info
;
936 if (target
->state
!= TARGET_HALTED
)
938 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
942 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
945 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
947 target_t
*target
= get_current_target(cmd_ctx
);
948 armv4_5_common_t
*armv4_5
;
949 arm7_9_common_t
*arm7_9
;
950 arm9tdmi_common_t
*arm9tdmi
;
951 arm920t_common_t
*arm920t
;
952 arm_jtag_t
*jtag_info
;
954 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
956 command_print(cmd_ctx
, "current target isn't an ARM920t target");
960 jtag_info
= &arm7_9
->jtag_info
;
962 if (target
->state
!= TARGET_HALTED
)
964 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
968 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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