1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
53 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_soft_reset_halt(struct target_s
*target
);
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59 target_type_t arm920t_target
=
64 .arch_state
= arm920t_arch_state
,
67 .resume
= arm7_9_resume
,
70 .assert_reset
= arm7_9_assert_reset
,
71 .deassert_reset
= arm7_9_deassert_reset
,
72 .soft_reset_halt
= arm920t_soft_reset_halt
,
74 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
76 .read_memory
= arm920t_read_memory
,
77 .write_memory
= arm920t_write_memory
,
78 .bulk_write_memory
= arm7_9_bulk_write_memory
,
80 .run_algorithm
= armv4_5_run_algorithm
,
82 .add_breakpoint
= arm7_9_add_breakpoint
,
83 .remove_breakpoint
= arm7_9_remove_breakpoint
,
84 .add_watchpoint
= arm7_9_add_watchpoint
,
85 .remove_watchpoint
= arm7_9_remove_watchpoint
,
87 .register_commands
= arm920t_register_commands
,
88 .target_command
= arm920t_target_command
,
89 .init_target
= arm920t_init_target
,
93 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
95 armv4_5_common_t
*armv4_5
= target
->arch_info
;
96 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
97 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
98 scan_field_t fields
[4];
99 u8 access_type_buf
= 1;
100 u8 reg_addr_buf
= reg_addr
& 0x3f;
103 jtag_add_end_state(TAP_RTI
);
104 arm_jtag_scann(jtag_info
, 0xf);
105 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
107 fields
[0].device
= jtag_info
->chain_pos
;
108 fields
[0].num_bits
= 1;
109 fields
[0].out_value
= &access_type_buf
;
110 fields
[0].out_mask
= NULL
;
111 fields
[0].in_value
= NULL
;
112 fields
[0].in_check_value
= NULL
;
113 fields
[0].in_check_mask
= NULL
;
114 fields
[0].in_handler
= NULL
;
115 fields
[0].in_handler_priv
= NULL
;
117 fields
[1].device
= jtag_info
->chain_pos
;
118 fields
[1].num_bits
= 32;
119 fields
[1].out_value
= NULL
;
120 fields
[1].out_mask
= NULL
;
121 fields
[1].in_value
= NULL
;
122 fields
[1].in_check_value
= NULL
;
123 fields
[1].in_check_mask
= NULL
;
124 fields
[1].in_handler
= NULL
;
125 fields
[1].in_handler_priv
= NULL
;
127 fields
[2].device
= jtag_info
->chain_pos
;
128 fields
[2].num_bits
= 6;
129 fields
[2].out_value
= ®_addr_buf
;
130 fields
[2].out_mask
= NULL
;
131 fields
[2].in_value
= NULL
;
132 fields
[2].in_check_value
= NULL
;
133 fields
[2].in_check_mask
= NULL
;
134 fields
[2].in_handler
= NULL
;
135 fields
[2].in_handler_priv
= NULL
;
137 fields
[3].device
= jtag_info
->chain_pos
;
138 fields
[3].num_bits
= 1;
139 fields
[3].out_value
= &nr_w_buf
;
140 fields
[3].out_mask
= NULL
;
141 fields
[3].in_value
= NULL
;
142 fields
[3].in_check_value
= NULL
;
143 fields
[3].in_check_mask
= NULL
;
144 fields
[3].in_handler
= NULL
;
145 fields
[3].in_handler_priv
= NULL
;
147 jtag_add_dr_scan(4, fields
, -1);
149 fields
[1].in_handler_priv
= value
;
150 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
152 jtag_add_dr_scan(4, fields
, -1);
154 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
155 jtag_execute_queue();
156 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
162 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
164 armv4_5_common_t
*armv4_5
= target
->arch_info
;
165 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
166 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
167 scan_field_t fields
[4];
168 u8 access_type_buf
= 1;
169 u8 reg_addr_buf
= reg_addr
& 0x3f;
173 buf_set_u32(value_buf
, 0, 32, value
);
175 jtag_add_end_state(TAP_RTI
);
176 arm_jtag_scann(jtag_info
, 0xf);
177 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
179 fields
[0].device
= jtag_info
->chain_pos
;
180 fields
[0].num_bits
= 1;
181 fields
[0].out_value
= &access_type_buf
;
182 fields
[0].out_mask
= NULL
;
183 fields
[0].in_value
= NULL
;
184 fields
[0].in_check_value
= NULL
;
185 fields
[0].in_check_mask
= NULL
;
186 fields
[0].in_handler
= NULL
;
187 fields
[0].in_handler_priv
= NULL
;
189 fields
[1].device
= jtag_info
->chain_pos
;
190 fields
[1].num_bits
= 32;
191 fields
[1].out_value
= value_buf
;
192 fields
[1].out_mask
= NULL
;
193 fields
[1].in_value
= NULL
;
194 fields
[1].in_check_value
= NULL
;
195 fields
[1].in_check_mask
= NULL
;
196 fields
[1].in_handler
= NULL
;
197 fields
[1].in_handler_priv
= NULL
;
199 fields
[2].device
= jtag_info
->chain_pos
;
200 fields
[2].num_bits
= 6;
201 fields
[2].out_value
= ®_addr_buf
;
202 fields
[2].out_mask
= NULL
;
203 fields
[2].in_value
= NULL
;
204 fields
[2].in_check_value
= NULL
;
205 fields
[2].in_check_mask
= NULL
;
206 fields
[2].in_handler
= NULL
;
207 fields
[2].in_handler_priv
= NULL
;
209 fields
[3].device
= jtag_info
->chain_pos
;
210 fields
[3].num_bits
= 1;
211 fields
[3].out_value
= &nr_w_buf
;
212 fields
[3].out_mask
= NULL
;
213 fields
[3].in_value
= NULL
;
214 fields
[3].in_check_value
= NULL
;
215 fields
[3].in_check_mask
= NULL
;
216 fields
[3].in_handler
= NULL
;
217 fields
[3].in_handler_priv
= NULL
;
219 jtag_add_dr_scan(4, fields
, -1);
221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
222 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
228 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
230 armv4_5_common_t
*armv4_5
= target
->arch_info
;
231 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
232 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
233 scan_field_t fields
[4];
234 u8 access_type_buf
= 0; /* interpreted access */
235 u8 reg_addr_buf
= 0x0;
237 u8 cp15_opcode_buf
[4];
239 jtag_add_end_state(TAP_RTI
);
240 arm_jtag_scann(jtag_info
, 0xf);
241 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
243 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
245 fields
[0].device
= jtag_info
->chain_pos
;
246 fields
[0].num_bits
= 1;
247 fields
[0].out_value
= &access_type_buf
;
248 fields
[0].out_mask
= NULL
;
249 fields
[0].in_value
= NULL
;
250 fields
[0].in_check_value
= NULL
;
251 fields
[0].in_check_mask
= NULL
;
252 fields
[0].in_handler
= NULL
;
253 fields
[0].in_handler_priv
= NULL
;
255 fields
[1].device
= jtag_info
->chain_pos
;
256 fields
[1].num_bits
= 32;
257 fields
[1].out_value
= cp15_opcode_buf
;
258 fields
[1].out_mask
= NULL
;
259 fields
[1].in_value
= NULL
;
260 fields
[1].in_check_value
= NULL
;
261 fields
[1].in_check_mask
= NULL
;
262 fields
[1].in_handler
= NULL
;
263 fields
[1].in_handler_priv
= NULL
;
265 fields
[2].device
= jtag_info
->chain_pos
;
266 fields
[2].num_bits
= 6;
267 fields
[2].out_value
= ®_addr_buf
;
268 fields
[2].out_mask
= NULL
;
269 fields
[2].in_value
= NULL
;
270 fields
[2].in_check_value
= NULL
;
271 fields
[2].in_check_mask
= NULL
;
272 fields
[2].in_handler
= NULL
;
273 fields
[2].in_handler_priv
= NULL
;
275 fields
[3].device
= jtag_info
->chain_pos
;
276 fields
[3].num_bits
= 1;
277 fields
[3].out_value
= &nr_w_buf
;
278 fields
[3].out_mask
= NULL
;
279 fields
[3].in_value
= NULL
;
280 fields
[3].in_check_value
= NULL
;
281 fields
[3].in_check_mask
= NULL
;
282 fields
[3].in_handler
= NULL
;
283 fields
[3].in_handler_priv
= NULL
;
285 jtag_add_dr_scan(4, fields
, -1);
287 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
288 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
289 arm7_9_execute_sys_speed(target
);
291 if (jtag_execute_queue() != ERROR_OK
)
293 ERROR("failed executing JTAG queue, exiting");
300 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
302 armv4_5_common_t
*armv4_5
= target
->arch_info
;
307 /* load address into R1 */
309 arm9tdmi_write_core_regs(target
, 0x2, regs
);
311 /* read-modify-write CP15 test state register
312 * to enable interpreted access mode */
313 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
314 jtag_execute_queue();
315 cp15c15
|= 1; /* set interpret mode */
316 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
318 /* execute CP15 instruction and ARM load (reading from coprocessor) */
319 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
321 /* disable interpreted access mode */
322 cp15c15
&= ~1U; /* clear interpret mode */
323 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
325 /* retrieve value from R0 */
327 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
328 jtag_execute_queue();
330 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
331 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
334 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
335 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
340 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
343 armv4_5_common_t
*armv4_5
= target
->arch_info
;
346 /* load value, address into R0, R1 */
349 arm9tdmi_write_core_regs(target
, 0x3, regs
);
351 /* read-modify-write CP15 test state register
352 * to enable interpreted access mode */
353 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
354 jtag_execute_queue();
355 cp15c15
|= 1; /* set interpret mode */
356 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
358 /* execute CP15 instruction and ARM store (writing to coprocessor) */
359 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
361 /* disable interpreted access mode */
362 cp15c15
&= ~1U; /* set interpret mode */
363 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
365 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
366 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
369 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
370 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
375 u32
arm920t_get_ttb(target_t
*target
)
380 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
386 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
390 /* read cp15 control register */
391 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
392 jtag_execute_queue();
395 cp15_control
&= ~0x1U
;
398 cp15_control
&= ~0x4U
;
401 cp15_control
&= ~0x1000U
;
403 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
406 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
410 /* read cp15 control register */
411 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
412 jtag_execute_queue();
415 cp15_control
|= 0x1U
;
418 cp15_control
|= 0x4U
;
421 cp15_control
|= 0x1000U
;
423 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
426 void arm920t_post_debug_entry(target_t
*target
)
429 armv4_5_common_t
*armv4_5
= target
->arch_info
;
430 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
431 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
432 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
434 /* examine cp15 control reg */
435 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
436 jtag_execute_queue();
437 DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
439 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
442 /* identify caches */
443 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
444 jtag_execute_queue();
445 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
448 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
449 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
450 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
452 /* save i/d fault status and address register */
453 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
454 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
455 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
456 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
458 if (arm920t
->preserve_cache
)
460 /* read-modify-write CP15 test state register
461 * to disable I/D-cache linefills */
462 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
463 jtag_execute_queue();
465 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
469 void arm920t_pre_restore_context(target_t
*target
)
472 armv4_5_common_t
*armv4_5
= target
->arch_info
;
473 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
474 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
475 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
477 /* restore i/d fault status and address register */
478 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
479 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
480 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
481 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
483 /* read-modify-write CP15 test state register
484 * to reenable I/D-cache linefills */
485 if (arm920t
->preserve_cache
)
487 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
488 jtag_execute_queue();
490 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
494 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
496 armv4_5_common_t
*armv4_5
= target
->arch_info
;
497 arm7_9_common_t
*arm7_9
;
498 arm9tdmi_common_t
*arm9tdmi
;
499 arm920t_common_t
*arm920t
;
501 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
506 arm7_9
= armv4_5
->arch_info
;
507 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
512 arm9tdmi
= arm7_9
->arch_info
;
513 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
518 arm920t
= arm9tdmi
->arch_info
;
519 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
524 *armv4_5_p
= armv4_5
;
526 *arm9tdmi_p
= arm9tdmi
;
527 *arm920t_p
= arm920t
;
532 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
534 armv4_5_common_t
*armv4_5
= target
->arch_info
;
535 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
536 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
537 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
541 "disabled", "enabled"
544 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
546 ERROR("BUG: called for a non-ARMv4/5 target");
550 snprintf(buf
, buf_size
,
551 "target halted in %s state due to %s, current mode: %s\n"
552 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
553 "MMU: %s, D-Cache: %s, I-Cache: %s",
554 armv4_5_state_strings
[armv4_5
->core_state
],
555 target_debug_reason_strings
[target
->debug_reason
],
556 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
557 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
558 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
559 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
560 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
561 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
566 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
570 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
575 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
578 armv4_5_common_t
*armv4_5
= target
->arch_info
;
579 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
580 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
581 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
583 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
586 if (((size
== 4) || (size
== 2)) && (count
== 1))
588 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
590 DEBUG("D-Cache enabled, writing through to main memory");
594 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
597 /* cacheable & bufferable means write-back region */
599 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
602 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
604 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
605 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
612 int arm920t_soft_reset_halt(struct target_s
*target
)
614 armv4_5_common_t
*armv4_5
= target
->arch_info
;
615 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
616 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
617 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
618 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
620 if (target
->state
== TARGET_RUNNING
)
622 target
->type
->halt(target
);
625 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
627 embeddedice_read_reg(dbg_stat
);
628 jtag_execute_queue();
631 target
->state
= TARGET_HALTED
;
633 /* SVC, ARM state, IRQ and FIQ disabled */
634 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
635 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
636 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
638 /* start fetching from 0x0 */
639 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
640 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
641 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
643 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
644 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
646 arm920t_disable_mmu_caches(target
, 1, 1, 1);
647 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
648 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
649 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
651 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
656 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
658 arm9tdmi_init_target(cmd_ctx
, target
);
670 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
672 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
673 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
675 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
677 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
679 arm9tdmi
->arch_info
= arm920t
;
680 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
682 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
683 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
685 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
686 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
687 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
688 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
689 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
690 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
691 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
692 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
694 /* disabling linefills leads to lockups, so keep them enabled for now
695 * this doesn't affect correctness, but might affect timing issues, if
696 * important data is evicted from the cache during the debug session
698 arm920t
->preserve_cache
= 0;
700 /* override hw single-step capability from ARM9TDMI */
701 arm9tdmi
->has_single_step
= 1;
706 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
709 char *variant
= NULL
;
710 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
714 ERROR("'target arm920t' requires at least one additional argument");
718 chain_pos
= strtoul(args
[3], NULL
, 0);
723 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
725 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
730 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
733 command_t
*arm920t_cmd
;
736 retval
= arm9tdmi_register_commands(cmd_ctx
);
738 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
740 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
741 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
742 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
743 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
745 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
746 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
747 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
749 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
750 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
751 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
753 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
754 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
759 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
761 target_t
*target
= get_current_target(cmd_ctx
);
762 armv4_5_common_t
*armv4_5
;
763 arm7_9_common_t
*arm7_9
;
764 arm9tdmi_common_t
*arm9tdmi
;
765 arm920t_common_t
*arm920t
;
766 arm_jtag_t
*jtag_info
;
768 u32 cp15_ctrl
, cp15_ctrl_saved
;
771 u32 C15_C_D_Ind
, C15_C_I_Ind
;
774 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
779 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
783 if ((output
= fopen(args
[0], "w")) == NULL
)
785 DEBUG("error opening cache content file");
789 for (i
= 0; i
< 16; i
++)
790 regs_p
[i
] = ®s
[i
];
792 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
794 command_print(cmd_ctx
, "current target isn't an ARM920t target");
798 jtag_info
= &arm7_9
->jtag_info
;
800 /* disable MMU and Caches */
801 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
802 jtag_execute_queue();
803 cp15_ctrl_saved
= cp15_ctrl
;
804 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
805 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
807 /* read CP15 test state register */
808 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
809 jtag_execute_queue();
811 /* read DCache content */
812 fprintf(output
, "DCache:\n");
814 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
815 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
817 fprintf(output
, "\nsegment: %i\n----------", segment
);
819 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
820 regs
[0] = 0x0 | (segment
<< 5);
821 arm9tdmi_write_core_regs(target
, 0x1, regs
);
823 /* set interpret mode */
825 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
827 /* D CAM Read, loads current victim into C15.C.D.Ind */
828 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
830 /* read current victim */
831 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
833 /* clear interpret mode */
835 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
837 for (index
= 0; index
< 64; index
++)
839 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
840 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
841 arm9tdmi_write_core_regs(target
, 0x1, regs
);
843 /* set interpret mode */
845 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
847 /* Write DCache victim */
848 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
851 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
854 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
856 /* clear interpret mode */
858 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
860 /* read D RAM and CAM content */
861 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
862 jtag_execute_queue();
864 d_cache
[segment
][index
].cam
= regs
[9];
867 regs
[9] &= 0xfffffffe;
868 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
870 for (i
= 1; i
< 9; i
++)
872 d_cache
[segment
][index
].data
[i
] = regs
[i
];
873 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
878 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
879 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
880 arm9tdmi_write_core_regs(target
, 0x1, regs
);
882 /* set interpret mode */
884 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
886 /* Write DCache victim */
887 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
889 /* clear interpret mode */
891 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
894 /* read ICache content */
895 fprintf(output
, "ICache:\n");
897 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
898 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
900 fprintf(output
, "segment: %i\n----------", segment
);
902 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
903 regs
[0] = 0x0 | (segment
<< 5);
904 arm9tdmi_write_core_regs(target
, 0x1, regs
);
906 /* set interpret mode */
908 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
910 /* I CAM Read, loads current victim into C15.C.I.Ind */
911 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
913 /* read current victim */
914 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
916 /* clear interpret mode */
918 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
920 for (index
= 0; index
< 64; index
++)
922 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
923 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
924 arm9tdmi_write_core_regs(target
, 0x1, regs
);
926 /* set interpret mode */
928 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
930 /* Write ICache victim */
931 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
934 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
937 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
939 /* clear interpret mode */
941 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
943 /* read I RAM and CAM content */
944 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
945 jtag_execute_queue();
947 i_cache
[segment
][index
].cam
= regs
[9];
950 regs
[9] &= 0xfffffffe;
951 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
953 for (i
= 1; i
< 9; i
++)
955 i_cache
[segment
][index
].data
[i
] = regs
[i
];
956 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
962 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
963 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
964 arm9tdmi_write_core_regs(target
, 0x1, regs
);
966 /* set interpret mode */
968 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
970 /* Write ICache victim */
971 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
973 /* clear interpret mode */
975 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
978 /* restore CP15 MMU and Cache settings */
979 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
981 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
985 /* mark registers dirty */
986 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
987 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
988 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= 1;
989 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= 1;
990 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= 1;
991 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= 1;
992 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= 1;
993 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= 1;
994 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= 1;
995 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= 1;
1000 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1002 target_t
*target
= get_current_target(cmd_ctx
);
1003 armv4_5_common_t
*armv4_5
;
1004 arm7_9_common_t
*arm7_9
;
1005 arm9tdmi_common_t
*arm9tdmi
;
1006 arm920t_common_t
*arm920t
;
1007 arm_jtag_t
*jtag_info
;
1009 u32 cp15_ctrl
, cp15_ctrl_saved
;
1014 u32 Dlockdown
, Ilockdown
;
1015 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1020 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1024 if ((output
= fopen(args
[0], "w")) == NULL
)
1026 DEBUG("error opening mmu content file");
1030 for (i
= 0; i
< 16; i
++)
1031 regs_p
[i
] = ®s
[i
];
1033 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1035 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1039 jtag_info
= &arm7_9
->jtag_info
;
1041 /* disable MMU and Caches */
1042 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1043 jtag_execute_queue();
1044 cp15_ctrl_saved
= cp15_ctrl
;
1045 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1046 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1048 /* read CP15 test state register */
1049 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1050 jtag_execute_queue();
1052 /* prepare reading D TLB content
1055 /* set interpret mode */
1057 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1059 /* Read D TLB lockdown */
1060 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1062 /* clear interpret mode */
1064 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1066 /* read D TLB lockdown stored to r1 */
1067 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1068 jtag_execute_queue();
1069 Dlockdown
= regs
[1];
1071 for (victim
= 0; victim
< 64; victim
+= 8)
1073 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1074 * base remains unchanged, victim goes through entries 0 to 63 */
1075 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1076 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1078 /* set interpret mode */
1080 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1082 /* Write D TLB lockdown */
1083 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1085 /* Read D TLB CAM */
1086 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1088 /* clear interpret mode */
1090 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1092 /* read D TLB CAM content stored to r2-r9 */
1093 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1094 jtag_execute_queue();
1096 for (i
= 0; i
< 8; i
++)
1097 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1100 for (victim
= 0; victim
< 64; victim
++)
1102 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1103 * base remains unchanged, victim goes through entries 0 to 63 */
1104 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1105 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1107 /* set interpret mode */
1109 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1111 /* Write D TLB lockdown */
1112 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1114 /* Read D TLB RAM1 */
1115 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1117 /* Read D TLB RAM2 */
1118 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1120 /* clear interpret mode */
1122 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1124 /* read D TLB RAM content stored to r2 and r3 */
1125 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1126 jtag_execute_queue();
1128 d_tlb
[victim
].ram1
= regs
[2];
1129 d_tlb
[victim
].ram2
= regs
[3];
1132 /* restore D TLB lockdown */
1133 regs
[1] = Dlockdown
;
1134 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1136 /* Write D TLB lockdown */
1137 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1139 /* prepare reading I TLB content
1142 /* set interpret mode */
1144 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1146 /* Read I TLB lockdown */
1147 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1149 /* clear interpret mode */
1151 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1153 /* read I TLB lockdown stored to r1 */
1154 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1155 jtag_execute_queue();
1156 Ilockdown
= regs
[1];
1158 for (victim
= 0; victim
< 64; victim
+= 8)
1160 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1161 * base remains unchanged, victim goes through entries 0 to 63 */
1162 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1163 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1165 /* set interpret mode */
1167 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1169 /* Write I TLB lockdown */
1170 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1172 /* Read I TLB CAM */
1173 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1175 /* clear interpret mode */
1177 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1179 /* read I TLB CAM content stored to r2-r9 */
1180 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1181 jtag_execute_queue();
1183 for (i
= 0; i
< 8; i
++)
1184 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1187 for (victim
= 0; victim
< 64; victim
++)
1189 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1190 * base remains unchanged, victim goes through entries 0 to 63 */
1191 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1192 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1194 /* set interpret mode */
1196 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1198 /* Write I TLB lockdown */
1199 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1201 /* Read I TLB RAM1 */
1202 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1204 /* Read I TLB RAM2 */
1205 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1207 /* clear interpret mode */
1209 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1211 /* read I TLB RAM content stored to r2 and r3 */
1212 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1213 jtag_execute_queue();
1215 i_tlb
[victim
].ram1
= regs
[2];
1216 i_tlb
[victim
].ram2
= regs
[3];
1219 /* restore I TLB lockdown */
1220 regs
[1] = Ilockdown
;
1221 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1223 /* Write I TLB lockdown */
1224 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1226 /* restore CP15 MMU and Cache settings */
1227 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1229 /* output data to file */
1230 fprintf(output
, "D TLB content:\n");
1231 for (i
= 0; i
< 64; i
++)
1233 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1236 fprintf(output
, "\n\nI TLB content:\n");
1237 for (i
= 0; i
< 64; i
++)
1239 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1242 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1246 /* mark registers dirty */
1247 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
1248 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
1249 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= 1;
1250 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= 1;
1251 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= 1;
1252 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= 1;
1253 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= 1;
1254 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= 1;
1255 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= 1;
1256 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= 1;
1260 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1263 target_t
*target
= get_current_target(cmd_ctx
);
1264 armv4_5_common_t
*armv4_5
;
1265 arm7_9_common_t
*arm7_9
;
1266 arm9tdmi_common_t
*arm9tdmi
;
1267 arm920t_common_t
*arm920t
;
1268 arm_jtag_t
*jtag_info
;
1270 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1272 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1276 jtag_info
= &arm7_9
->jtag_info
;
1278 if (target
->state
!= TARGET_HALTED
)
1280 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1284 /* one or more argument, access a single register (write if second argument is given */
1287 int address
= strtoul(args
[0], NULL
, 0);
1292 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1294 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1297 jtag_execute_queue();
1299 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1303 u32 value
= strtoul(args
[1], NULL
, 0);
1304 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1306 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1309 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1316 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1319 target_t
*target
= get_current_target(cmd_ctx
);
1320 armv4_5_common_t
*armv4_5
;
1321 arm7_9_common_t
*arm7_9
;
1322 arm9tdmi_common_t
*arm9tdmi
;
1323 arm920t_common_t
*arm920t
;
1324 arm_jtag_t
*jtag_info
;
1326 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1328 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1332 jtag_info
= &arm7_9
->jtag_info
;
1334 if (target
->state
!= TARGET_HALTED
)
1336 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1340 /* one or more argument, access a single register (write if second argument is given */
1343 u32 opcode
= strtoul(args
[0], NULL
, 0);
1348 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1350 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1354 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1358 u32 value
= strtoul(args
[1], NULL
, 0);
1359 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1361 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1364 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1368 u32 value
= strtoul(args
[1], NULL
, 0);
1369 u32 address
= strtoul(args
[2], NULL
, 0);
1370 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1372 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1375 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1380 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1386 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1388 target_t
*target
= get_current_target(cmd_ctx
);
1389 armv4_5_common_t
*armv4_5
;
1390 arm7_9_common_t
*arm7_9
;
1391 arm9tdmi_common_t
*arm9tdmi
;
1392 arm920t_common_t
*arm920t
;
1394 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1396 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1400 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1403 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1405 target_t
*target
= get_current_target(cmd_ctx
);
1406 armv4_5_common_t
*armv4_5
;
1407 arm7_9_common_t
*arm7_9
;
1408 arm9tdmi_common_t
*arm9tdmi
;
1409 arm920t_common_t
*arm920t
;
1410 arm_jtag_t
*jtag_info
;
1412 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1414 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1418 jtag_info
= &arm7_9
->jtag_info
;
1420 if (target
->state
!= TARGET_HALTED
)
1422 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1426 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1429 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1431 target_t
*target
= get_current_target(cmd_ctx
);
1432 armv4_5_common_t
*armv4_5
;
1433 arm7_9_common_t
*arm7_9
;
1434 arm9tdmi_common_t
*arm9tdmi
;
1435 arm920t_common_t
*arm920t
;
1436 arm_jtag_t
*jtag_info
;
1438 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1440 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1444 jtag_info
= &arm7_9
->jtag_info
;
1446 if (target
->state
!= TARGET_HALTED
)
1448 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1452 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1455 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1457 target_t
*target
= get_current_target(cmd_ctx
);
1458 armv4_5_common_t
*armv4_5
;
1459 arm7_9_common_t
*arm7_9
;
1460 arm9tdmi_common_t
*arm9tdmi
;
1461 arm920t_common_t
*arm920t
;
1462 arm_jtag_t
*jtag_info
;
1464 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1466 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1470 jtag_info
= &arm7_9
->jtag_info
;
1472 if (target
->state
!= TARGET_HALTED
)
1474 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1478 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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