1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 /* forward declarations */
50 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
);
51 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_quit(void);
53 int arm920t_arch_state(struct target_s
*target
);
54 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
56 int arm920t_soft_reset_halt(struct target_s
*target
);
58 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
60 target_type_t arm920t_target
=
65 .arch_state
= arm920t_arch_state
,
67 .target_request_data
= arm7_9_target_request_data
,
70 .resume
= arm7_9_resume
,
73 .assert_reset
= arm7_9_assert_reset
,
74 .deassert_reset
= arm7_9_deassert_reset
,
75 .soft_reset_halt
= arm920t_soft_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm920t_read_memory
,
80 .write_memory
= arm920t_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
83 .blank_check_memory
= arm7_9_blank_check_memory
,
85 .run_algorithm
= armv4_5_run_algorithm
,
87 .add_breakpoint
= arm7_9_add_breakpoint
,
88 .remove_breakpoint
= arm7_9_remove_breakpoint
,
89 .add_watchpoint
= arm7_9_add_watchpoint
,
90 .remove_watchpoint
= arm7_9_remove_watchpoint
,
92 .register_commands
= arm920t_register_commands
,
93 .target_create
= arm920t_target_create
,
94 .init_target
= arm920t_init_target
,
95 .examine
= arm9tdmi_examine
,
99 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
101 armv4_5_common_t
*armv4_5
= target
->arch_info
;
102 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
103 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
104 scan_field_t fields
[4];
105 u8 access_type_buf
= 1;
106 u8 reg_addr_buf
= reg_addr
& 0x3f;
109 jtag_add_end_state(TAP_RTI
);
110 arm_jtag_scann(jtag_info
, 0xf);
111 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
113 fields
[0].tap
= jtag_info
->tap
;
114 fields
[0].num_bits
= 1;
115 fields
[0].out_value
= &access_type_buf
;
116 fields
[0].out_mask
= NULL
;
117 fields
[0].in_value
= NULL
;
118 fields
[0].in_check_value
= NULL
;
119 fields
[0].in_check_mask
= NULL
;
120 fields
[0].in_handler
= NULL
;
121 fields
[0].in_handler_priv
= NULL
;
123 fields
[1].tap
= jtag_info
->tap
;
124 fields
[1].num_bits
= 32;
125 fields
[1].out_value
= NULL
;
126 fields
[1].out_mask
= NULL
;
127 fields
[1].in_value
= NULL
;
128 fields
[1].in_check_value
= NULL
;
129 fields
[1].in_check_mask
= NULL
;
130 fields
[1].in_handler
= NULL
;
131 fields
[1].in_handler_priv
= NULL
;
133 fields
[2].tap
= jtag_info
->tap
;
134 fields
[2].num_bits
= 6;
135 fields
[2].out_value
= ®_addr_buf
;
136 fields
[2].out_mask
= NULL
;
137 fields
[2].in_value
= NULL
;
138 fields
[2].in_check_value
= NULL
;
139 fields
[2].in_check_mask
= NULL
;
140 fields
[2].in_handler
= NULL
;
141 fields
[2].in_handler_priv
= NULL
;
143 fields
[3].tap
= jtag_info
->tap
;
144 fields
[3].num_bits
= 1;
145 fields
[3].out_value
= &nr_w_buf
;
146 fields
[3].out_mask
= NULL
;
147 fields
[3].in_value
= NULL
;
148 fields
[3].in_check_value
= NULL
;
149 fields
[3].in_check_mask
= NULL
;
150 fields
[3].in_handler
= NULL
;
151 fields
[3].in_handler_priv
= NULL
;
153 jtag_add_dr_scan(4, fields
, -1);
155 fields
[1].in_handler_priv
= value
;
156 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
158 jtag_add_dr_scan(4, fields
, -1);
160 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
161 jtag_execute_queue();
162 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
168 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
170 armv4_5_common_t
*armv4_5
= target
->arch_info
;
171 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
172 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
173 scan_field_t fields
[4];
174 u8 access_type_buf
= 1;
175 u8 reg_addr_buf
= reg_addr
& 0x3f;
179 buf_set_u32(value_buf
, 0, 32, value
);
181 jtag_add_end_state(TAP_RTI
);
182 arm_jtag_scann(jtag_info
, 0xf);
183 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
185 fields
[0].tap
= jtag_info
->tap
;
186 fields
[0].num_bits
= 1;
187 fields
[0].out_value
= &access_type_buf
;
188 fields
[0].out_mask
= NULL
;
189 fields
[0].in_value
= NULL
;
190 fields
[0].in_check_value
= NULL
;
191 fields
[0].in_check_mask
= NULL
;
192 fields
[0].in_handler
= NULL
;
193 fields
[0].in_handler_priv
= NULL
;
195 fields
[1].tap
= jtag_info
->tap
;
196 fields
[1].num_bits
= 32;
197 fields
[1].out_value
= value_buf
;
198 fields
[1].out_mask
= NULL
;
199 fields
[1].in_value
= NULL
;
200 fields
[1].in_check_value
= NULL
;
201 fields
[1].in_check_mask
= NULL
;
202 fields
[1].in_handler
= NULL
;
203 fields
[1].in_handler_priv
= NULL
;
205 fields
[2].tap
= jtag_info
->tap
;
206 fields
[2].num_bits
= 6;
207 fields
[2].out_value
= ®_addr_buf
;
208 fields
[2].out_mask
= NULL
;
209 fields
[2].in_value
= NULL
;
210 fields
[2].in_check_value
= NULL
;
211 fields
[2].in_check_mask
= NULL
;
212 fields
[2].in_handler
= NULL
;
213 fields
[2].in_handler_priv
= NULL
;
215 fields
[3].tap
= jtag_info
->tap
;
216 fields
[3].num_bits
= 1;
217 fields
[3].out_value
= &nr_w_buf
;
218 fields
[3].out_mask
= NULL
;
219 fields
[3].in_value
= NULL
;
220 fields
[3].in_check_value
= NULL
;
221 fields
[3].in_check_mask
= NULL
;
222 fields
[3].in_handler
= NULL
;
223 fields
[3].in_handler_priv
= NULL
;
225 jtag_add_dr_scan(4, fields
, -1);
227 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
228 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
234 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
237 armv4_5_common_t
*armv4_5
= target
->arch_info
;
238 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
239 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
240 scan_field_t fields
[4];
241 u8 access_type_buf
= 0; /* interpreted access */
242 u8 reg_addr_buf
= 0x0;
244 u8 cp15_opcode_buf
[4];
246 jtag_add_end_state(TAP_RTI
);
247 arm_jtag_scann(jtag_info
, 0xf);
248 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
250 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
252 fields
[0].tap
= jtag_info
->tap
;
253 fields
[0].num_bits
= 1;
254 fields
[0].out_value
= &access_type_buf
;
255 fields
[0].out_mask
= NULL
;
256 fields
[0].in_value
= NULL
;
257 fields
[0].in_check_value
= NULL
;
258 fields
[0].in_check_mask
= NULL
;
259 fields
[0].in_handler
= NULL
;
260 fields
[0].in_handler_priv
= NULL
;
262 fields
[1].tap
= jtag_info
->tap
;
263 fields
[1].num_bits
= 32;
264 fields
[1].out_value
= cp15_opcode_buf
;
265 fields
[1].out_mask
= NULL
;
266 fields
[1].in_value
= NULL
;
267 fields
[1].in_check_value
= NULL
;
268 fields
[1].in_check_mask
= NULL
;
269 fields
[1].in_handler
= NULL
;
270 fields
[1].in_handler_priv
= NULL
;
272 fields
[2].tap
= jtag_info
->tap
;
273 fields
[2].num_bits
= 6;
274 fields
[2].out_value
= ®_addr_buf
;
275 fields
[2].out_mask
= NULL
;
276 fields
[2].in_value
= NULL
;
277 fields
[2].in_check_value
= NULL
;
278 fields
[2].in_check_mask
= NULL
;
279 fields
[2].in_handler
= NULL
;
280 fields
[2].in_handler_priv
= NULL
;
282 fields
[3].tap
= jtag_info
->tap
;
283 fields
[3].num_bits
= 1;
284 fields
[3].out_value
= &nr_w_buf
;
285 fields
[3].out_mask
= NULL
;
286 fields
[3].in_value
= NULL
;
287 fields
[3].in_check_value
= NULL
;
288 fields
[3].in_check_mask
= NULL
;
289 fields
[3].in_handler
= NULL
;
290 fields
[3].in_handler_priv
= NULL
;
292 jtag_add_dr_scan(4, fields
, -1);
294 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
295 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
296 retval
= arm7_9_execute_sys_speed(target
);
297 if (retval
!= ERROR_OK
)
300 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
302 LOG_ERROR("failed executing JTAG queue, exiting");
309 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
311 armv4_5_common_t
*armv4_5
= target
->arch_info
;
316 /* load address into R1 */
318 arm9tdmi_write_core_regs(target
, 0x2, regs
);
320 /* read-modify-write CP15 test state register
321 * to enable interpreted access mode */
322 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
323 jtag_execute_queue();
324 cp15c15
|= 1; /* set interpret mode */
325 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
327 /* execute CP15 instruction and ARM load (reading from coprocessor) */
328 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
330 /* disable interpreted access mode */
331 cp15c15
&= ~1U; /* clear interpret mode */
332 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
334 /* retrieve value from R0 */
336 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
337 jtag_execute_queue();
339 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
340 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
343 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
346 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
347 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
352 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
355 armv4_5_common_t
*armv4_5
= target
->arch_info
;
358 /* load value, address into R0, R1 */
361 arm9tdmi_write_core_regs(target
, 0x3, regs
);
363 /* read-modify-write CP15 test state register
364 * to enable interpreted access mode */
365 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
366 jtag_execute_queue();
367 cp15c15
|= 1; /* set interpret mode */
368 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
370 /* execute CP15 instruction and ARM store (writing to coprocessor) */
371 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
373 /* disable interpreted access mode */
374 cp15c15
&= ~1U; /* set interpret mode */
375 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
377 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
378 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
381 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
384 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
385 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
390 u32
arm920t_get_ttb(target_t
*target
)
395 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
401 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
405 /* read cp15 control register */
406 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
407 jtag_execute_queue();
410 cp15_control
&= ~0x1U
;
413 cp15_control
&= ~0x4U
;
416 cp15_control
&= ~0x1000U
;
418 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
421 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
425 /* read cp15 control register */
426 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
427 jtag_execute_queue();
430 cp15_control
|= 0x1U
;
433 cp15_control
|= 0x4U
;
436 cp15_control
|= 0x1000U
;
438 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
441 void arm920t_post_debug_entry(target_t
*target
)
444 armv4_5_common_t
*armv4_5
= target
->arch_info
;
445 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
446 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
447 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
449 /* examine cp15 control reg */
450 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
451 jtag_execute_queue();
452 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
454 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
457 /* identify caches */
458 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
459 jtag_execute_queue();
460 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
463 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
464 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
465 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
467 /* save i/d fault status and address register */
468 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
469 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
470 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
471 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
473 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
474 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
476 if (arm920t
->preserve_cache
)
478 /* read-modify-write CP15 test state register
479 * to disable I/D-cache linefills */
480 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
481 jtag_execute_queue();
483 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
487 void arm920t_pre_restore_context(target_t
*target
)
490 armv4_5_common_t
*armv4_5
= target
->arch_info
;
491 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
492 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
493 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
495 /* restore i/d fault status and address register */
496 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
497 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
498 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
499 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
501 /* read-modify-write CP15 test state register
502 * to reenable I/D-cache linefills */
503 if (arm920t
->preserve_cache
)
505 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
506 jtag_execute_queue();
508 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
512 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
514 armv4_5_common_t
*armv4_5
= target
->arch_info
;
515 arm7_9_common_t
*arm7_9
;
516 arm9tdmi_common_t
*arm9tdmi
;
517 arm920t_common_t
*arm920t
;
519 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
524 arm7_9
= armv4_5
->arch_info
;
525 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
530 arm9tdmi
= arm7_9
->arch_info
;
531 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
536 arm920t
= arm9tdmi
->arch_info
;
537 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
542 *armv4_5_p
= armv4_5
;
544 *arm9tdmi_p
= arm9tdmi
;
545 *arm920t_p
= arm920t
;
550 int arm920t_arch_state(struct target_s
*target
)
552 armv4_5_common_t
*armv4_5
= target
->arch_info
;
553 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
554 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
555 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
559 "disabled", "enabled"
562 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
564 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
568 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
569 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
570 "MMU: %s, D-Cache: %s, I-Cache: %s",
571 armv4_5_state_strings
[armv4_5
->core_state
],
572 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
573 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
574 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
575 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
576 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
577 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
578 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
583 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
587 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
592 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
595 armv4_5_common_t
*armv4_5
= target
->arch_info
;
596 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
597 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
598 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
600 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
603 if (((size
== 4) || (size
== 2)) && (count
== 1))
605 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
607 LOG_DEBUG("D-Cache enabled, writing through to main memory");
611 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
614 /* cacheable & bufferable means write-back region */
616 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
619 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
621 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
622 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
629 int arm920t_soft_reset_halt(struct target_s
*target
)
631 int retval
= ERROR_OK
;
632 armv4_5_common_t
*armv4_5
= target
->arch_info
;
633 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
634 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
635 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
636 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
638 if((retval
= target_halt(target
)) != ERROR_OK
)
643 long long then
=timeval_ms();
645 while (!(timeout
=((timeval_ms()-then
)>1000)))
647 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
649 embeddedice_read_reg(dbg_stat
);
650 if((retval
= jtag_execute_queue()) != ERROR_OK
)
660 /* do not eat all CPU, time out after 1 se*/
669 LOG_ERROR("Failed to halt CPU after 1 sec");
670 return ERROR_TARGET_TIMEOUT
;
673 target
->state
= TARGET_HALTED
;
675 /* SVC, ARM state, IRQ and FIQ disabled */
676 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
677 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
678 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
680 /* start fetching from 0x0 */
681 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
682 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
683 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
685 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
686 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
688 arm920t_disable_mmu_caches(target
, 1, 1, 1);
689 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
690 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
691 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
693 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
701 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
703 arm9tdmi_init_target(cmd_ctx
, target
);
709 int arm920t_quit(void)
715 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, jtag_tap_t
*tap
, const char *variant
)
717 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
718 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
720 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
722 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
, variant
);
724 arm9tdmi
->arch_info
= arm920t
;
725 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
727 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
728 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
730 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
731 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
732 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
733 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
734 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
735 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
736 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
737 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
739 /* disabling linefills leads to lockups, so keep them enabled for now
740 * this doesn't affect correctness, but might affect timing issues, if
741 * important data is evicted from the cache during the debug session
743 arm920t
->preserve_cache
= 0;
745 /* override hw single-step capability from ARM9TDMI */
746 arm7_9
->has_single_step
= 1;
751 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
753 arm920t_common_t
*arm920t
= calloc(1,sizeof(arm920t_common_t
));
755 arm920t_init_arch_info(target
, arm920t
, target
->tap
, target
->variant
);
760 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
763 command_t
*arm920t_cmd
;
766 retval
= arm9tdmi_register_commands(cmd_ctx
);
768 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
770 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
771 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
772 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
773 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
775 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
776 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
777 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
779 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
780 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
781 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
783 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
784 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
789 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
791 int retval
= ERROR_OK
;
792 target_t
*target
= get_current_target(cmd_ctx
);
793 armv4_5_common_t
*armv4_5
;
794 arm7_9_common_t
*arm7_9
;
795 arm9tdmi_common_t
*arm9tdmi
;
796 arm920t_common_t
*arm920t
;
797 arm_jtag_t
*jtag_info
;
799 u32 cp15_ctrl
, cp15_ctrl_saved
;
802 u32 C15_C_D_Ind
, C15_C_I_Ind
;
805 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
810 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
814 if ((output
= fopen(args
[0], "w")) == NULL
)
816 LOG_DEBUG("error opening cache content file");
820 for (i
= 0; i
< 16; i
++)
821 regs_p
[i
] = ®s
[i
];
823 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
825 command_print(cmd_ctx
, "current target isn't an ARM920t target");
829 jtag_info
= &arm7_9
->jtag_info
;
831 /* disable MMU and Caches */
832 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
833 if((retval
= jtag_execute_queue()) != ERROR_OK
)
837 cp15_ctrl_saved
= cp15_ctrl
;
838 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
839 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
841 /* read CP15 test state register */
842 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
843 jtag_execute_queue();
845 /* read DCache content */
846 fprintf(output
, "DCache:\n");
848 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
849 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
851 fprintf(output
, "\nsegment: %i\n----------", segment
);
853 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
854 regs
[0] = 0x0 | (segment
<< 5);
855 arm9tdmi_write_core_regs(target
, 0x1, regs
);
857 /* set interpret mode */
859 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
861 /* D CAM Read, loads current victim into C15.C.D.Ind */
862 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
864 /* read current victim */
865 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
867 /* clear interpret mode */
869 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
871 for (index
= 0; index
< 64; index
++)
873 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
874 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
875 arm9tdmi_write_core_regs(target
, 0x1, regs
);
877 /* set interpret mode */
879 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
881 /* Write DCache victim */
882 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
885 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
888 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
890 /* clear interpret mode */
892 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
894 /* read D RAM and CAM content */
895 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
896 if((retval
= jtag_execute_queue()) != ERROR_OK
)
901 d_cache
[segment
][index
].cam
= regs
[9];
904 regs
[9] &= 0xfffffffe;
905 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
907 for (i
= 1; i
< 9; i
++)
909 d_cache
[segment
][index
].data
[i
] = regs
[i
];
910 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
915 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
916 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
917 arm9tdmi_write_core_regs(target
, 0x1, regs
);
919 /* set interpret mode */
921 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
923 /* Write DCache victim */
924 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
926 /* clear interpret mode */
928 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
931 /* read ICache content */
932 fprintf(output
, "ICache:\n");
934 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
935 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
937 fprintf(output
, "segment: %i\n----------", segment
);
939 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
940 regs
[0] = 0x0 | (segment
<< 5);
941 arm9tdmi_write_core_regs(target
, 0x1, regs
);
943 /* set interpret mode */
945 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
947 /* I CAM Read, loads current victim into C15.C.I.Ind */
948 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
950 /* read current victim */
951 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
953 /* clear interpret mode */
955 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
957 for (index
= 0; index
< 64; index
++)
959 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
960 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
961 arm9tdmi_write_core_regs(target
, 0x1, regs
);
963 /* set interpret mode */
965 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
967 /* Write ICache victim */
968 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
971 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
974 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
976 /* clear interpret mode */
978 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
980 /* read I RAM and CAM content */
981 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
982 if((retval
= jtag_execute_queue()) != ERROR_OK
)
987 i_cache
[segment
][index
].cam
= regs
[9];
990 regs
[9] &= 0xfffffffe;
991 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
993 for (i
= 1; i
< 9; i
++)
995 i_cache
[segment
][index
].data
[i
] = regs
[i
];
996 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
1002 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
1003 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
1004 arm9tdmi_write_core_regs(target
, 0x1, regs
);
1006 /* set interpret mode */
1008 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1010 /* Write ICache victim */
1011 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
1013 /* clear interpret mode */
1015 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1018 /* restore CP15 MMU and Cache settings */
1019 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1021 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
1025 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1028 /* mark registers dirty. */
1029 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1030 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1031 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1032 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1033 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1034 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1035 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1036 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1037 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1038 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1043 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1045 int retval
= ERROR_OK
;
1046 target_t
*target
= get_current_target(cmd_ctx
);
1047 armv4_5_common_t
*armv4_5
;
1048 arm7_9_common_t
*arm7_9
;
1049 arm9tdmi_common_t
*arm9tdmi
;
1050 arm920t_common_t
*arm920t
;
1051 arm_jtag_t
*jtag_info
;
1053 u32 cp15_ctrl
, cp15_ctrl_saved
;
1058 u32 Dlockdown
, Ilockdown
;
1059 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1064 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1068 if ((output
= fopen(args
[0], "w")) == NULL
)
1070 LOG_DEBUG("error opening mmu content file");
1074 for (i
= 0; i
< 16; i
++)
1075 regs_p
[i
] = ®s
[i
];
1077 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1079 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1083 jtag_info
= &arm7_9
->jtag_info
;
1085 /* disable MMU and Caches */
1086 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1087 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1091 cp15_ctrl_saved
= cp15_ctrl
;
1092 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1093 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1095 /* read CP15 test state register */
1096 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1097 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1102 /* prepare reading D TLB content
1105 /* set interpret mode */
1107 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1109 /* Read D TLB lockdown */
1110 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1112 /* clear interpret mode */
1114 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1116 /* read D TLB lockdown stored to r1 */
1117 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1118 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1122 Dlockdown
= regs
[1];
1124 for (victim
= 0; victim
< 64; victim
+= 8)
1126 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1127 * base remains unchanged, victim goes through entries 0 to 63 */
1128 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1129 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1131 /* set interpret mode */
1133 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1135 /* Write D TLB lockdown */
1136 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1138 /* Read D TLB CAM */
1139 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1141 /* clear interpret mode */
1143 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1145 /* read D TLB CAM content stored to r2-r9 */
1146 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1147 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1152 for (i
= 0; i
< 8; i
++)
1153 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1156 for (victim
= 0; victim
< 64; victim
++)
1158 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1159 * base remains unchanged, victim goes through entries 0 to 63 */
1160 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1161 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1163 /* set interpret mode */
1165 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1167 /* Write D TLB lockdown */
1168 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1170 /* Read D TLB RAM1 */
1171 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1173 /* Read D TLB RAM2 */
1174 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1176 /* clear interpret mode */
1178 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1180 /* read D TLB RAM content stored to r2 and r3 */
1181 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1182 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1187 d_tlb
[victim
].ram1
= regs
[2];
1188 d_tlb
[victim
].ram2
= regs
[3];
1191 /* restore D TLB lockdown */
1192 regs
[1] = Dlockdown
;
1193 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1195 /* Write D TLB lockdown */
1196 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1198 /* prepare reading I TLB content
1201 /* set interpret mode */
1203 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1205 /* Read I TLB lockdown */
1206 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1208 /* clear interpret mode */
1210 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1212 /* read I TLB lockdown stored to r1 */
1213 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1214 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1218 Ilockdown
= regs
[1];
1220 for (victim
= 0; victim
< 64; victim
+= 8)
1222 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1223 * base remains unchanged, victim goes through entries 0 to 63 */
1224 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1225 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1227 /* set interpret mode */
1229 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1231 /* Write I TLB lockdown */
1232 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1234 /* Read I TLB CAM */
1235 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1237 /* clear interpret mode */
1239 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1241 /* read I TLB CAM content stored to r2-r9 */
1242 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1243 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1248 for (i
= 0; i
< 8; i
++)
1249 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1252 for (victim
= 0; victim
< 64; victim
++)
1254 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1255 * base remains unchanged, victim goes through entries 0 to 63 */
1256 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1257 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1259 /* set interpret mode */
1261 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1263 /* Write I TLB lockdown */
1264 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1266 /* Read I TLB RAM1 */
1267 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1269 /* Read I TLB RAM2 */
1270 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1272 /* clear interpret mode */
1274 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1276 /* read I TLB RAM content stored to r2 and r3 */
1277 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1278 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1283 i_tlb
[victim
].ram1
= regs
[2];
1284 i_tlb
[victim
].ram2
= regs
[3];
1287 /* restore I TLB lockdown */
1288 regs
[1] = Ilockdown
;
1289 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1291 /* Write I TLB lockdown */
1292 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1294 /* restore CP15 MMU and Cache settings */
1295 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1297 /* output data to file */
1298 fprintf(output
, "D TLB content:\n");
1299 for (i
= 0; i
< 64; i
++)
1301 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1304 fprintf(output
, "\n\nI TLB content:\n");
1305 for (i
= 0; i
< 64; i
++)
1307 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1310 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1314 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1317 /* mark registers dirty */
1318 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1319 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1320 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1321 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1322 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1323 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1324 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1325 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1326 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1327 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1331 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1334 target_t
*target
= get_current_target(cmd_ctx
);
1335 armv4_5_common_t
*armv4_5
;
1336 arm7_9_common_t
*arm7_9
;
1337 arm9tdmi_common_t
*arm9tdmi
;
1338 arm920t_common_t
*arm920t
;
1339 arm_jtag_t
*jtag_info
;
1341 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1343 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1347 jtag_info
= &arm7_9
->jtag_info
;
1349 if (target
->state
!= TARGET_HALTED
)
1351 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1355 /* one or more argument, access a single register (write if second argument is given */
1358 int address
= strtoul(args
[0], NULL
, 0);
1363 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1365 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1368 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1373 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1377 u32 value
= strtoul(args
[1], NULL
, 0);
1378 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1380 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1383 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1390 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1393 target_t
*target
= get_current_target(cmd_ctx
);
1394 armv4_5_common_t
*armv4_5
;
1395 arm7_9_common_t
*arm7_9
;
1396 arm9tdmi_common_t
*arm9tdmi
;
1397 arm920t_common_t
*arm920t
;
1398 arm_jtag_t
*jtag_info
;
1400 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1402 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1406 jtag_info
= &arm7_9
->jtag_info
;
1408 if (target
->state
!= TARGET_HALTED
)
1410 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1414 /* one or more argument, access a single register (write if second argument is given */
1417 u32 opcode
= strtoul(args
[0], NULL
, 0);
1422 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1424 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1428 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1432 u32 value
= strtoul(args
[1], NULL
, 0);
1433 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1435 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1438 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1442 u32 value
= strtoul(args
[1], NULL
, 0);
1443 u32 address
= strtoul(args
[2], NULL
, 0);
1444 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1446 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1449 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1454 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1460 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1462 target_t
*target
= get_current_target(cmd_ctx
);
1463 armv4_5_common_t
*armv4_5
;
1464 arm7_9_common_t
*arm7_9
;
1465 arm9tdmi_common_t
*arm9tdmi
;
1466 arm920t_common_t
*arm920t
;
1468 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1470 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1474 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1477 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1479 target_t
*target
= get_current_target(cmd_ctx
);
1480 armv4_5_common_t
*armv4_5
;
1481 arm7_9_common_t
*arm7_9
;
1482 arm9tdmi_common_t
*arm9tdmi
;
1483 arm920t_common_t
*arm920t
;
1484 arm_jtag_t
*jtag_info
;
1486 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1488 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1492 jtag_info
= &arm7_9
->jtag_info
;
1494 if (target
->state
!= TARGET_HALTED
)
1496 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1500 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1503 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1505 target_t
*target
= get_current_target(cmd_ctx
);
1506 armv4_5_common_t
*armv4_5
;
1507 arm7_9_common_t
*arm7_9
;
1508 arm9tdmi_common_t
*arm9tdmi
;
1509 arm920t_common_t
*arm920t
;
1510 arm_jtag_t
*jtag_info
;
1512 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1514 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1518 jtag_info
= &arm7_9
->jtag_info
;
1520 if (target
->state
!= TARGET_HALTED
)
1522 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1526 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1529 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1531 target_t
*target
= get_current_target(cmd_ctx
);
1532 armv4_5_common_t
*armv4_5
;
1533 arm7_9_common_t
*arm7_9
;
1534 arm9tdmi_common_t
*arm9tdmi
;
1535 arm920t_common_t
*arm920t
;
1536 arm_jtag_t
*jtag_info
;
1538 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1540 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1544 jtag_info
= &arm7_9
->jtag_info
;
1546 if (target
->state
!= TARGET_HALTED
)
1548 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1552 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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