1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include <helper/time_support.h>
26 #include "target_type.h"
28 #include "arm_opcodes.h"
32 * For information about the ARM920T, see ARM DDI 0151C especially
33 * Chapter 9 about debug support, which shows how to manipulate each
34 * of the different scan chains:
36 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
37 * 1 ... debugging; watchpoint and breakpoint status, etc; also
38 * MMU and cache access in conjunction with scan chain 15
40 * 3 ... external boundary scan (SoC-specific, unused here)
41 * 4 ... access to cache tag RAM
43 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
44 * "interpreted" works with a few actual MRC/MCR instructions
45 * "physical" provides register-like behaviors. Section 9.6.7
46 * covers these details.
48 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
52 #define _DEBUG_INSTRUCTION_EXECUTION_
55 /* Table 9-8 shows scan chain 15 format during physical access mode, using a
56 * dedicated 6-bit address space (encoded in bits 33:38). Writes use one
57 * JTAG scan, while reads use two.
59 * Table 9-9 lists the thirteen registers which support physical access.
60 * ARM920T_CP15_PHYS_ADDR() constructs the 6-bit reg_addr parameter passed
61 * to arm920t_read_cp15_physical() and arm920t_write_cp15_physical().
67 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
69 /* Registers supporting physical Read access (from table 9-9) */
70 #define CP15PHYS_CACHETYPE ARM920T_CP15_PHYS_ADDR(0, 0x0, 1)
71 #define CP15PHYS_ICACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xd, 1)
72 #define CP15PHYS_DCACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xe, 1)
73 /* NOTE: several more registers support only physical read access */
75 /* Registers supporting physical Read/Write access (from table 9-9) */
76 #define CP15PHYS_CTRL ARM920T_CP15_PHYS_ADDR(0, 0x1, 0)
77 #define CP15PHYS_PID ARM920T_CP15_PHYS_ADDR(0, 0xd, 0)
78 #define CP15PHYS_TESTSTATE ARM920T_CP15_PHYS_ADDR(0, 0xf, 0)
79 #define CP15PHYS_ICACHE ARM920T_CP15_PHYS_ADDR(1, 0x1, 1)
80 #define CP15PHYS_DCACHE ARM920T_CP15_PHYS_ADDR(1, 0x2, 1)
82 static int arm920t_read_cp15_physical(struct target
*target
,
83 int reg_addr
, uint32_t *value
)
85 struct arm920t_common
*arm920t
= target_to_arm920(target
);
86 struct arm_jtag
*jtag_info
;
87 struct scan_field fields
[4];
88 uint8_t access_type_buf
= 1;
89 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
92 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
94 jtag_set_end_state(TAP_IDLE
);
95 arm_jtag_scann(jtag_info
, 0xf);
96 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
98 fields
[0].num_bits
= 1;
99 fields
[0].out_value
= &access_type_buf
;
100 fields
[0].in_value
= NULL
;
102 fields
[1].num_bits
= 32;
103 fields
[1].out_value
= NULL
;
104 fields
[1].in_value
= NULL
;
106 fields
[2].num_bits
= 6;
107 fields
[2].out_value
= ®_addr_buf
;
108 fields
[2].in_value
= NULL
;
110 fields
[3].num_bits
= 1;
111 fields
[3].out_value
= &nr_w_buf
;
112 fields
[3].in_value
= NULL
;
114 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, jtag_get_end_state());
116 fields
[1].in_value
= (uint8_t *)value
;
118 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, jtag_get_end_state());
120 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
122 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
123 jtag_execute_queue();
124 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
130 static int arm920t_write_cp15_physical(struct target
*target
,
131 int reg_addr
, uint32_t value
)
133 struct arm920t_common
*arm920t
= target_to_arm920(target
);
134 struct arm_jtag
*jtag_info
;
135 struct scan_field fields
[4];
136 uint8_t access_type_buf
= 1;
137 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
138 uint8_t nr_w_buf
= 1;
139 uint8_t value_buf
[4];
141 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
143 buf_set_u32(value_buf
, 0, 32, value
);
145 jtag_set_end_state(TAP_IDLE
);
146 arm_jtag_scann(jtag_info
, 0xf);
147 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
149 fields
[0].num_bits
= 1;
150 fields
[0].out_value
= &access_type_buf
;
151 fields
[0].in_value
= NULL
;
153 fields
[1].num_bits
= 32;
154 fields
[1].out_value
= value_buf
;
155 fields
[1].in_value
= NULL
;
157 fields
[2].num_bits
= 6;
158 fields
[2].out_value
= ®_addr_buf
;
159 fields
[2].in_value
= NULL
;
161 fields
[3].num_bits
= 1;
162 fields
[3].out_value
= &nr_w_buf
;
163 fields
[3].in_value
= NULL
;
165 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, jtag_get_end_state());
167 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
168 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
174 /* See table 9-10 for scan chain 15 format during interpreted access mode.
175 * If the TESTSTATE register is set for interpreted access, certain CP15
176 * MRC and MCR instructions may be executed through scan chain 15.
178 * Tables 9-11, 9-12, and 9-13 show which MRC and MCR instructions can be
179 * executed using scan chain 15 interpreted mode.
181 static int arm920t_execute_cp15(struct target
*target
, uint32_t cp15_opcode
,
185 struct arm920t_common
*arm920t
= target_to_arm920(target
);
186 struct arm_jtag
*jtag_info
;
187 struct scan_field fields
[4];
188 uint8_t access_type_buf
= 0; /* interpreted access */
189 uint8_t reg_addr_buf
= 0x0;
190 uint8_t nr_w_buf
= 0;
191 uint8_t cp15_opcode_buf
[4];
193 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
195 jtag_set_end_state(TAP_IDLE
);
196 arm_jtag_scann(jtag_info
, 0xf);
197 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
199 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
201 fields
[0].num_bits
= 1;
202 fields
[0].out_value
= &access_type_buf
;
203 fields
[0].in_value
= NULL
;
205 fields
[1].num_bits
= 32;
206 fields
[1].out_value
= cp15_opcode_buf
;
207 fields
[1].in_value
= NULL
;
209 fields
[2].num_bits
= 6;
210 fields
[2].out_value
= ®_addr_buf
;
211 fields
[2].in_value
= NULL
;
213 fields
[3].num_bits
= 1;
214 fields
[3].out_value
= &nr_w_buf
;
215 fields
[3].in_value
= NULL
;
217 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, jtag_get_end_state());
219 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
220 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
221 retval
= arm7_9_execute_sys_speed(target
);
222 if (retval
!= ERROR_OK
)
225 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
227 LOG_ERROR("failed executing JTAG queue");
234 static int arm920t_read_cp15_interpreted(struct target
*target
,
235 uint32_t cp15_opcode
, uint32_t address
, uint32_t *value
)
237 struct arm
*armv4_5
= target_to_arm(target
);
240 uint32_t cp15c15
= 0x0;
241 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
243 /* load address into R1 */
245 arm9tdmi_write_core_regs(target
, 0x2, regs
);
247 /* read-modify-write CP15 test state register
248 * to enable interpreted access mode */
249 arm920t_read_cp15_physical(target
, CP15PHYS_TESTSTATE
, &cp15c15
);
250 jtag_execute_queue();
251 cp15c15
|= 1; /* set interpret mode */
252 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
254 /* execute CP15 instruction and ARM load (reading from coprocessor) */
255 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
257 /* disable interpreted access mode */
258 cp15c15
&= ~1U; /* clear interpret mode */
259 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
261 /* retrieve value from R0 */
263 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
264 jtag_execute_queue();
266 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
267 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x",
268 cp15_opcode
, address
, *value
);
271 if (!is_arm_mode(armv4_5
->core_mode
))
281 int arm920t_write_cp15_interpreted(struct target
*target
,
282 uint32_t cp15_opcode
, uint32_t value
, uint32_t address
)
284 uint32_t cp15c15
= 0x0;
285 struct arm
*armv4_5
= target_to_arm(target
);
287 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
289 /* load value, address into R0, R1 */
292 arm9tdmi_write_core_regs(target
, 0x3, regs
);
294 /* read-modify-write CP15 test state register
295 * to enable interpreted access mode */
296 arm920t_read_cp15_physical(target
, CP15PHYS_TESTSTATE
, &cp15c15
);
297 jtag_execute_queue();
298 cp15c15
|= 1; /* set interpret mode */
299 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
301 /* execute CP15 instruction and ARM store (writing to coprocessor) */
302 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
304 /* disable interpreted access mode */
305 cp15c15
&= ~1U; /* set interpret mode */
306 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
308 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
309 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x",
310 cp15_opcode
, value
, address
);
313 if (!is_arm_mode(armv4_5
->core_mode
))
323 uint32_t arm920t_get_ttb(struct target
*target
)
328 if ((retval
= arm920t_read_cp15_interpreted(target
,
329 /* FIXME use opcode macro */
330 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
337 void arm920t_disable_mmu_caches(struct target
*target
, int mmu
,
338 int d_u_cache
, int i_cache
)
340 uint32_t cp15_control
;
342 /* read cp15 control register */
343 arm920t_read_cp15_physical(target
, CP15PHYS_CTRL
, &cp15_control
);
344 jtag_execute_queue();
347 cp15_control
&= ~0x1U
;
350 cp15_control
&= ~0x4U
;
353 cp15_control
&= ~0x1000U
;
355 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_control
);
359 void arm920t_enable_mmu_caches(struct target
*target
, int mmu
,
360 int d_u_cache
, int i_cache
)
362 uint32_t cp15_control
;
364 /* read cp15 control register */
365 arm920t_read_cp15_physical(target
, CP15PHYS_CTRL
, &cp15_control
);
366 jtag_execute_queue();
369 cp15_control
|= 0x1U
;
372 cp15_control
|= 0x4U
;
375 cp15_control
|= 0x1000U
;
377 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_control
);
381 void arm920t_post_debug_entry(struct target
*target
)
384 struct arm920t_common
*arm920t
= target_to_arm920(target
);
386 /* examine cp15 control reg */
387 arm920t_read_cp15_physical(target
,
388 CP15PHYS_CTRL
, &arm920t
->cp15_control_reg
);
389 jtag_execute_queue();
390 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, arm920t
->cp15_control_reg
);
392 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
394 uint32_t cache_type_reg
;
395 /* identify caches */
396 arm920t_read_cp15_physical(target
,
397 CP15PHYS_CACHETYPE
, &cache_type_reg
);
398 jtag_execute_queue();
399 armv4_5_identify_cache(cache_type_reg
,
400 &arm920t
->armv4_5_mmu
.armv4_5_cache
);
403 arm920t
->armv4_5_mmu
.mmu_enabled
=
404 (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
405 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
=
406 (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
407 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
=
408 (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
410 /* save i/d fault status and address register */
411 /* FIXME use opcode macros */
412 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
413 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
414 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
415 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
417 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
418 ", I FSR: 0x%8.8" PRIx32
", I FAR: 0x%8.8" PRIx32
,
419 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
421 if (arm920t
->preserve_cache
)
423 /* read-modify-write CP15 test state register
424 * to disable I/D-cache linefills */
425 arm920t_read_cp15_physical(target
,
426 CP15PHYS_TESTSTATE
, &cp15c15
);
427 jtag_execute_queue();
429 arm920t_write_cp15_physical(target
,
430 CP15PHYS_TESTSTATE
, cp15c15
);
435 void arm920t_pre_restore_context(struct target
*target
)
438 struct arm920t_common
*arm920t
= target_to_arm920(target
);
440 /* restore i/d fault status and address register */
441 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
442 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
443 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
444 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
446 /* read-modify-write CP15 test state register
447 * to reenable I/D-cache linefills */
448 if (arm920t
->preserve_cache
)
450 arm920t_read_cp15_physical(target
,
451 CP15PHYS_TESTSTATE
, &cp15c15
);
452 jtag_execute_queue();
454 arm920t_write_cp15_physical(target
,
455 CP15PHYS_TESTSTATE
, cp15c15
);
459 static const char arm920_not
[] = "target is not an ARM920";
461 static int arm920t_verify_pointer(struct command_context
*cmd_ctx
,
462 struct arm920t_common
*arm920t
)
464 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
) {
465 command_print(cmd_ctx
, arm920_not
);
466 return ERROR_TARGET_INVALID
;
472 /** Logs summary of ARM920 state for a halted target. */
473 int arm920t_arch_state(struct target
*target
)
475 static const char *state
[] =
477 "disabled", "enabled"
480 struct arm920t_common
*arm920t
= target_to_arm920(target
);
483 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
485 LOG_ERROR("BUG: %s", arm920_not
);
486 return ERROR_TARGET_INVALID
;
489 armv4_5
= &arm920t
->arm7_9_common
.armv4_5_common
;
491 arm_arch_state(target
);
492 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
493 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
494 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
495 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
500 static int arm920_mmu(struct target
*target
, int *enabled
)
502 if (target
->state
!= TARGET_HALTED
) {
503 LOG_ERROR("%s: target not halted", __func__
);
504 return ERROR_TARGET_INVALID
;
507 *enabled
= target_to_arm920(target
)->armv4_5_mmu
.mmu_enabled
;
511 static int arm920_virt2phys(struct target
*target
,
512 uint32_t virt
, uint32_t *phys
)
518 struct arm920t_common
*arm920t
= target_to_arm920(target
);
520 uint32_t ret
= armv4_5_mmu_translate_va(target
,
521 &arm920t
->armv4_5_mmu
, virt
, &type
, &cb
, &domain
, &ap
);
530 /** Reads a buffer, in the specified word size, with current MMU settings. */
531 int arm920t_read_memory(struct target
*target
, uint32_t address
,
532 uint32_t size
, uint32_t count
, uint8_t *buffer
)
536 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
542 static int arm920t_read_phys_memory(struct target
*target
,
543 uint32_t address
, uint32_t size
,
544 uint32_t count
, uint8_t *buffer
)
546 struct arm920t_common
*arm920t
= target_to_arm920(target
);
548 return armv4_5_mmu_read_physical(target
, &arm920t
->armv4_5_mmu
,
549 address
, size
, count
, buffer
);
552 static int arm920t_write_phys_memory(struct target
*target
,
553 uint32_t address
, uint32_t size
,
554 uint32_t count
, uint8_t *buffer
)
556 struct arm920t_common
*arm920t
= target_to_arm920(target
);
558 return armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
,
559 address
, size
, count
, buffer
);
563 /** Writes a buffer, in the specified word size, with current MMU settings. */
564 int arm920t_write_memory(struct target
*target
, uint32_t address
,
565 uint32_t size
, uint32_t count
, uint8_t *buffer
)
568 const uint32_t cache_mask
= ~0x1f; /* cache line size : 32 byte */
569 struct arm920t_common
*arm920t
= target_to_arm920(target
);
571 /* FIX!!!! this should be cleaned up and made much more general. The
572 * plan is to write up and test on arm920t specifically and
573 * then generalize and clean up afterwards. */
574 if (arm920t
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) &&
575 ((size
==2) || (size
==4)))
577 /* special case the handling of single word writes to
578 * bypass MMU, to allow implementation of breakpoints
579 * in memory marked read only
589 * We need physical address and cb
591 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
,
592 address
, &type
, &cb
, &domain
, &ap
);
596 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
600 LOG_DEBUG("D-Cache buffered, "
601 "drain write buffer");
604 * Drain write buffer - MCR p15,0,Rd,c7,c10,4
607 retval
= arm920t_write_cp15_interpreted(target
,
608 ARMV4_5_MCR(15, 0, 0, 7, 10, 4),
610 if (retval
!= ERROR_OK
)
617 * Write back memory ? -> clean cache
619 * There is no way to clean cache lines using
620 * cp15 scan chain, so copy the full cache
621 * line from cache to physical memory.
625 LOG_DEBUG("D-Cache in 'write back' mode, "
628 retval
= target_read_memory(target
,
629 address
& cache_mask
, 1,
630 sizeof(data
), &data
[0]);
631 if (retval
!= ERROR_OK
)
634 retval
= armv4_5_mmu_write_physical(target
,
635 &arm920t
->armv4_5_mmu
,
637 sizeof(data
), &data
[0]);
638 if (retval
!= ERROR_OK
)
646 * Cached ? -> Invalidate data cache using MVA
648 * MCR p15,0,Rd,c7,c6,1
650 LOG_DEBUG("D-Cache enabled, "
651 "invalidate cache line");
653 retval
= arm920t_write_cp15_interpreted(target
,
654 ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0,
655 address
& cache_mask
);
656 if (retval
!= ERROR_OK
)
661 /* write directly to physical memory,
662 * bypassing any read only MMU bits, etc.
664 retval
= armv4_5_mmu_write_physical(target
,
665 &arm920t
->armv4_5_mmu
, pa
, size
,
667 if (retval
!= ERROR_OK
)
671 if ((retval
= arm7_9_write_memory(target
, address
,
672 size
, count
, buffer
)) != ERROR_OK
)
676 /* If ICache is enabled, we have to invalidate affected ICache lines
677 * the DCache is forced to write-through,
678 * so we don't have to clean it here
680 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
684 /* invalidate ICache single entry with MVA
685 * mcr 15, 0, r0, cr7, cr5, {1}
687 LOG_DEBUG("I-Cache enabled, "
688 "invalidating affected I-Cache line");
689 retval
= arm920t_write_cp15_interpreted(target
,
690 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
691 0x0, address
& cache_mask
);
692 if (retval
!= ERROR_OK
)
698 * mcr 15, 0, r0, cr7, cr5, {0}
700 retval
= arm920t_write_cp15_interpreted(target
,
701 ARMV4_5_MCR(15, 0, 0, 7, 5, 0),
703 if (retval
!= ERROR_OK
)
712 int arm920t_soft_reset_halt(struct target
*target
)
714 int retval
= ERROR_OK
;
715 struct arm920t_common
*arm920t
= target_to_arm920(target
);
716 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
717 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
718 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
720 if ((retval
= target_halt(target
)) != ERROR_OK
)
725 long long then
= timeval_ms();
727 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
729 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1)
732 embeddedice_read_reg(dbg_stat
);
733 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
741 if (debug_level
>= 3)
743 /* do not eat all CPU, time out after 1 se*/
752 LOG_ERROR("Failed to halt CPU after 1 sec");
753 return ERROR_TARGET_TIMEOUT
;
756 target
->state
= TARGET_HALTED
;
758 /* SVC, ARM state, IRQ and FIQ disabled */
761 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
764 arm_set_cpsr(armv4_5
, cpsr
);
765 armv4_5
->cpsr
->dirty
= 1;
767 /* start fetching from 0x0 */
768 buf_set_u32(armv4_5
->pc
->value
, 0, 32, 0x0);
769 armv4_5
->pc
->dirty
= 1;
770 armv4_5
->pc
->valid
= 1;
772 arm920t_disable_mmu_caches(target
, 1, 1, 1);
773 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
774 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
775 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
777 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
780 /* FIXME remove forward decls */
781 static int arm920t_mrc(struct target
*target
, int cpnum
,
782 uint32_t op1
, uint32_t op2
,
783 uint32_t CRn
, uint32_t CRm
,
785 static int arm920t_mcr(struct target
*target
, int cpnum
,
786 uint32_t op1
, uint32_t op2
,
787 uint32_t CRn
, uint32_t CRm
,
790 int arm920t_init_arch_info(struct target
*target
,
791 struct arm920t_common
*arm920t
, struct jtag_tap
*tap
)
793 struct arm7_9_common
*arm7_9
= &arm920t
->arm7_9_common
;
795 arm7_9
->armv4_5_common
.mrc
= arm920t_mrc
;
796 arm7_9
->armv4_5_common
.mcr
= arm920t_mcr
;
798 /* initialize arm7/arm9 specific info (including armv4_5) */
799 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
801 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
803 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
804 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
806 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
807 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
808 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
809 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
810 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
811 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
812 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
813 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
815 /* disabling linefills leads to lockups, so keep them enabled for now
816 * this doesn't affect correctness, but might affect timing issues, if
817 * important data is evicted from the cache during the debug session
819 arm920t
->preserve_cache
= 0;
821 /* override hw single-step capability from ARM9TDMI */
822 arm7_9
->has_single_step
= 1;
827 static int arm920t_target_create(struct target
*target
, Jim_Interp
*interp
)
829 struct arm920t_common
*arm920t
;
831 arm920t
= calloc(1,sizeof(struct arm920t_common
));
832 return arm920t_init_arch_info(target
, arm920t
, target
->tap
);
835 COMMAND_HANDLER(arm920t_handle_read_cache_command
)
837 int retval
= ERROR_OK
;
838 struct target
*target
= get_current_target(CMD_CTX
);
839 struct arm920t_common
*arm920t
= target_to_arm920(target
);
840 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
841 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
843 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
845 uint32_t *regs_p
[16];
846 uint32_t C15_C_D_Ind
, C15_C_I_Ind
;
849 struct arm920t_cache_line d_cache
[8][64], i_cache
[8][64];
853 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
854 if (retval
!= ERROR_OK
)
859 command_print(CMD_CTX
, "usage: arm920t read_cache <filename>");
863 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
865 LOG_DEBUG("error opening cache content file");
869 for (i
= 0; i
< 16; i
++)
870 regs_p
[i
] = ®s
[i
];
872 /* disable MMU and Caches */
873 arm920t_read_cp15_physical(target
, CP15PHYS_CTRL
, &cp15_ctrl
);
874 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
878 cp15_ctrl_saved
= cp15_ctrl
;
879 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
880 | ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
881 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_ctrl
);
883 /* read CP15 test state register */
884 arm920t_read_cp15_physical(target
, CP15PHYS_TESTSTATE
, &cp15c15
);
885 jtag_execute_queue();
887 /* read DCache content */
888 fprintf(output
, "DCache:\n");
890 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
892 segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
;
895 fprintf(output
, "\nsegment: %i\n----------", segment
);
897 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
898 regs
[0] = 0x0 | (segment
<< 5);
899 arm9tdmi_write_core_regs(target
, 0x1, regs
);
901 /* set interpret mode */
903 arm920t_write_cp15_physical(target
,
904 CP15PHYS_TESTSTATE
, cp15c15
);
906 /* D CAM Read, loads current victim into C15.C.D.Ind */
907 arm920t_execute_cp15(target
,
908 ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
910 /* read current victim */
911 arm920t_read_cp15_physical(target
,
912 CP15PHYS_DCACHE_IDX
, &C15_C_D_Ind
);
914 /* clear interpret mode */
916 arm920t_write_cp15_physical(target
,
917 CP15PHYS_TESTSTATE
, cp15c15
);
919 for (index
= 0; index
< 64; index
++)
922 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
924 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
925 arm9tdmi_write_core_regs(target
, 0x1, regs
);
927 /* set interpret mode */
929 arm920t_write_cp15_physical(target
,
930 CP15PHYS_TESTSTATE
, cp15c15
);
932 /* Write DCache victim */
933 arm920t_execute_cp15(target
,
934 ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
937 arm920t_execute_cp15(target
,
938 ARMV4_5_MCR(15,2,0,15,10,2),
939 ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
942 arm920t_execute_cp15(target
,
943 ARMV4_5_MCR(15,2,0,15,6,2),
946 /* clear interpret mode */
948 arm920t_write_cp15_physical(target
,
949 CP15PHYS_TESTSTATE
, cp15c15
);
951 /* read D RAM and CAM content */
952 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
953 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
958 d_cache
[segment
][index
].cam
= regs
[9];
961 regs
[9] &= 0xfffffffe;
962 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8"
963 PRIx32
", content (%s):\n",
964 segment
, index
, regs
[9],
965 (regs
[9] & 0x10) ? "valid" : "invalid");
967 for (i
= 1; i
< 9; i
++)
969 d_cache
[segment
][index
].data
[i
] = regs
[i
];
970 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n",
976 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
977 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
978 arm9tdmi_write_core_regs(target
, 0x1, regs
);
980 /* set interpret mode */
982 arm920t_write_cp15_physical(target
,
983 CP15PHYS_TESTSTATE
, cp15c15
);
985 /* Write DCache victim */
986 arm920t_execute_cp15(target
,
987 ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
989 /* clear interpret mode */
991 arm920t_write_cp15_physical(target
,
992 CP15PHYS_TESTSTATE
, cp15c15
);
995 /* read ICache content */
996 fprintf(output
, "ICache:\n");
998 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
1000 segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
;
1003 fprintf(output
, "segment: %i\n----------", segment
);
1005 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
1006 regs
[0] = 0x0 | (segment
<< 5);
1007 arm9tdmi_write_core_regs(target
, 0x1, regs
);
1009 /* set interpret mode */
1011 arm920t_write_cp15_physical(target
,
1012 CP15PHYS_TESTSTATE
, cp15c15
);
1014 /* I CAM Read, loads current victim into C15.C.I.Ind */
1015 arm920t_execute_cp15(target
,
1016 ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
1018 /* read current victim */
1019 arm920t_read_cp15_physical(target
, CP15PHYS_ICACHE_IDX
,
1022 /* clear interpret mode */
1024 arm920t_write_cp15_physical(target
,
1025 CP15PHYS_TESTSTATE
, cp15c15
);
1027 for (index
= 0; index
< 64; index
++)
1030 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
1032 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
1033 arm9tdmi_write_core_regs(target
, 0x1, regs
);
1035 /* set interpret mode */
1037 arm920t_write_cp15_physical(target
,
1038 CP15PHYS_TESTSTATE
, cp15c15
);
1040 /* Write ICache victim */
1041 arm920t_execute_cp15(target
,
1042 ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
1045 arm920t_execute_cp15(target
,
1046 ARMV4_5_MCR(15,2,0,15,9,2),
1047 ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
1050 arm920t_execute_cp15(target
,
1051 ARMV4_5_MCR(15,2,0,15,5,2),
1054 /* clear interpret mode */
1056 arm920t_write_cp15_physical(target
,
1057 CP15PHYS_TESTSTATE
, cp15c15
);
1059 /* read I RAM and CAM content */
1060 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
1061 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1066 i_cache
[segment
][index
].cam
= regs
[9];
1069 regs
[9] &= 0xfffffffe;
1070 fprintf(output
, "\nsegment: %i, index: %i, "
1071 "CAM: 0x%8.8" PRIx32
", content (%s):\n",
1072 segment
, index
, regs
[9],
1073 (regs
[9] & 0x10) ? "valid" : "invalid");
1075 for (i
= 1; i
< 9; i
++)
1077 i_cache
[segment
][index
].data
[i
] = regs
[i
];
1078 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n",
1083 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
1084 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
1085 arm9tdmi_write_core_regs(target
, 0x1, regs
);
1087 /* set interpret mode */
1089 arm920t_write_cp15_physical(target
,
1090 CP15PHYS_TESTSTATE
, cp15c15
);
1092 /* Write ICache victim */
1093 arm920t_execute_cp15(target
,
1094 ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
1096 /* clear interpret mode */
1098 arm920t_write_cp15_physical(target
,
1099 CP15PHYS_TESTSTATE
, cp15c15
);
1102 /* restore CP15 MMU and Cache settings */
1103 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_ctrl_saved
);
1105 command_print(CMD_CTX
, "cache content successfully output to %s",
1110 if (!is_arm_mode(armv4_5
->core_mode
))
1113 /* force writeback of the valid data */
1114 r
= armv4_5
->core_cache
->reg_list
;
1115 r
[0].dirty
= r
[0].valid
;
1116 r
[1].dirty
= r
[1].valid
;
1117 r
[2].dirty
= r
[2].valid
;
1118 r
[3].dirty
= r
[3].valid
;
1119 r
[4].dirty
= r
[4].valid
;
1120 r
[5].dirty
= r
[5].valid
;
1121 r
[6].dirty
= r
[6].valid
;
1122 r
[7].dirty
= r
[7].valid
;
1124 r
= arm_reg_current(armv4_5
, 8);
1125 r
->dirty
= r
->valid
;
1127 r
= arm_reg_current(armv4_5
, 9);
1128 r
->dirty
= r
->valid
;
1133 COMMAND_HANDLER(arm920t_handle_read_mmu_command
)
1135 int retval
= ERROR_OK
;
1136 struct target
*target
= get_current_target(CMD_CTX
);
1137 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1138 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1139 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
1141 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
1143 uint32_t *regs_p
[16];
1146 uint32_t Dlockdown
, Ilockdown
;
1147 struct arm920t_tlb_entry d_tlb
[64], i_tlb
[64];
1151 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1152 if (retval
!= ERROR_OK
)
1157 command_print(CMD_CTX
, "usage: arm920t read_mmu <filename>");
1161 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
1163 LOG_DEBUG("error opening mmu content file");
1167 for (i
= 0; i
< 16; i
++)
1168 regs_p
[i
] = ®s
[i
];
1170 /* disable MMU and Caches */
1171 arm920t_read_cp15_physical(target
, CP15PHYS_CTRL
, &cp15_ctrl
);
1172 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1176 cp15_ctrl_saved
= cp15_ctrl
;
1177 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
1178 | ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1179 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_ctrl
);
1181 /* read CP15 test state register */
1182 arm920t_read_cp15_physical(target
, CP15PHYS_TESTSTATE
, &cp15c15
);
1183 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1188 /* prepare reading D TLB content
1191 /* set interpret mode */
1193 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
1195 /* Read D TLB lockdown */
1196 arm920t_execute_cp15(target
,
1197 ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1199 /* clear interpret mode */
1201 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
1203 /* read D TLB lockdown stored to r1 */
1204 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1205 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1209 Dlockdown
= regs
[1];
1211 for (victim
= 0; victim
< 64; victim
+= 8)
1213 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1214 * base remains unchanged, victim goes through entries 0 to 63
1216 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1217 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1219 /* set interpret mode */
1221 arm920t_write_cp15_physical(target
,
1222 CP15PHYS_TESTSTATE
, cp15c15
);
1224 /* Write D TLB lockdown */
1225 arm920t_execute_cp15(target
,
1226 ARMV4_5_MCR(15,0,0,10,0,0),
1229 /* Read D TLB CAM */
1230 arm920t_execute_cp15(target
,
1231 ARMV4_5_MCR(15,4,0,15,6,4),
1232 ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1234 /* clear interpret mode */
1236 arm920t_write_cp15_physical(target
,
1237 CP15PHYS_TESTSTATE
, cp15c15
);
1239 /* read D TLB CAM content stored to r2-r9 */
1240 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1241 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1246 for (i
= 0; i
< 8; i
++)
1247 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1250 for (victim
= 0; victim
< 64; victim
++)
1252 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1253 * base remains unchanged, victim goes through entries 0 to 63
1255 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1256 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1258 /* set interpret mode */
1260 arm920t_write_cp15_physical(target
,
1261 CP15PHYS_TESTSTATE
, cp15c15
);
1263 /* Write D TLB lockdown */
1264 arm920t_execute_cp15(target
,
1265 ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1267 /* Read D TLB RAM1 */
1268 arm920t_execute_cp15(target
,
1269 ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1271 /* Read D TLB RAM2 */
1272 arm920t_execute_cp15(target
,
1273 ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1275 /* clear interpret mode */
1277 arm920t_write_cp15_physical(target
,
1278 CP15PHYS_TESTSTATE
, cp15c15
);
1280 /* read D TLB RAM content stored to r2 and r3 */
1281 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1282 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1287 d_tlb
[victim
].ram1
= regs
[2];
1288 d_tlb
[victim
].ram2
= regs
[3];
1291 /* restore D TLB lockdown */
1292 regs
[1] = Dlockdown
;
1293 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1295 /* Write D TLB lockdown */
1296 arm920t_execute_cp15(target
,
1297 ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1299 /* prepare reading I TLB content
1302 /* set interpret mode */
1304 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
1306 /* Read I TLB lockdown */
1307 arm920t_execute_cp15(target
,
1308 ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1310 /* clear interpret mode */
1312 arm920t_write_cp15_physical(target
, CP15PHYS_TESTSTATE
, cp15c15
);
1314 /* read I TLB lockdown stored to r1 */
1315 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1316 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1320 Ilockdown
= regs
[1];
1322 for (victim
= 0; victim
< 64; victim
+= 8)
1324 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1325 * base remains unchanged, victim goes through entries 0 to 63
1327 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1328 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1330 /* set interpret mode */
1332 arm920t_write_cp15_physical(target
,
1333 CP15PHYS_TESTSTATE
, cp15c15
);
1335 /* Write I TLB lockdown */
1336 arm920t_execute_cp15(target
,
1337 ARMV4_5_MCR(15,0,0,10,0,1),
1340 /* Read I TLB CAM */
1341 arm920t_execute_cp15(target
,
1342 ARMV4_5_MCR(15,4,0,15,5,4),
1343 ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1345 /* clear interpret mode */
1347 arm920t_write_cp15_physical(target
,
1348 CP15PHYS_TESTSTATE
, cp15c15
);
1350 /* read I TLB CAM content stored to r2-r9 */
1351 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1352 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1357 for (i
= 0; i
< 8; i
++)
1358 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1361 for (victim
= 0; victim
< 64; victim
++)
1363 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1364 * base remains unchanged, victim goes through entries 0 to 63
1366 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1367 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1369 /* set interpret mode */
1371 arm920t_write_cp15_physical(target
,
1372 CP15PHYS_TESTSTATE
, cp15c15
);
1374 /* Write I TLB lockdown */
1375 arm920t_execute_cp15(target
,
1376 ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1378 /* Read I TLB RAM1 */
1379 arm920t_execute_cp15(target
,
1380 ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1382 /* Read I TLB RAM2 */
1383 arm920t_execute_cp15(target
,
1384 ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1386 /* clear interpret mode */
1388 arm920t_write_cp15_physical(target
,
1389 CP15PHYS_TESTSTATE
, cp15c15
);
1391 /* read I TLB RAM content stored to r2 and r3 */
1392 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1393 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1398 i_tlb
[victim
].ram1
= regs
[2];
1399 i_tlb
[victim
].ram2
= regs
[3];
1402 /* restore I TLB lockdown */
1403 regs
[1] = Ilockdown
;
1404 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1406 /* Write I TLB lockdown */
1407 arm920t_execute_cp15(target
,
1408 ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1410 /* restore CP15 MMU and Cache settings */
1411 arm920t_write_cp15_physical(target
, CP15PHYS_CTRL
, cp15_ctrl_saved
);
1413 /* output data to file */
1414 fprintf(output
, "D TLB content:\n");
1415 for (i
= 0; i
< 64; i
++)
1417 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
1418 " 0x%8.8" PRIx32
" %s\n",
1419 i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
,
1420 (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1423 fprintf(output
, "\n\nI TLB content:\n");
1424 for (i
= 0; i
< 64; i
++)
1426 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
1427 " 0x%8.8" PRIx32
" %s\n",
1428 i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
,
1429 (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1432 command_print(CMD_CTX
, "mmu content successfully output to %s",
1437 if (!is_arm_mode(armv4_5
->core_mode
))
1440 /* force writeback of the valid data */
1441 r
= armv4_5
->core_cache
->reg_list
;
1442 r
[0].dirty
= r
[0].valid
;
1443 r
[1].dirty
= r
[1].valid
;
1444 r
[2].dirty
= r
[2].valid
;
1445 r
[3].dirty
= r
[3].valid
;
1446 r
[4].dirty
= r
[4].valid
;
1447 r
[5].dirty
= r
[5].valid
;
1448 r
[6].dirty
= r
[6].valid
;
1449 r
[7].dirty
= r
[7].valid
;
1451 r
= arm_reg_current(armv4_5
, 8);
1452 r
->dirty
= r
->valid
;
1454 r
= arm_reg_current(armv4_5
, 9);
1455 r
->dirty
= r
->valid
;
1460 COMMAND_HANDLER(arm920t_handle_cp15_command
)
1463 struct target
*target
= get_current_target(CMD_CTX
);
1464 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1466 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1467 if (retval
!= ERROR_OK
)
1470 if (target
->state
!= TARGET_HALTED
)
1472 command_print(CMD_CTX
, "target must be stopped for "
1473 "\"%s\" command", CMD_NAME
);
1477 /* one argument, read a register.
1478 * two arguments, write it.
1483 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], address
);
1488 if ((retval
= arm920t_read_cp15_physical(target
,
1489 address
, &value
)) != ERROR_OK
)
1491 command_print(CMD_CTX
,
1492 "couldn't access reg %i", address
);
1495 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1500 command_print(CMD_CTX
, "%i: %8.8" PRIx32
,
1503 else if (CMD_ARGC
== 2)
1506 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1507 retval
= arm920t_write_cp15_physical(target
,
1509 if (retval
!= ERROR_OK
)
1511 command_print(CMD_CTX
,
1512 "couldn't access reg %i", address
);
1513 /* REVISIT why lie? "return retval"? */
1516 command_print(CMD_CTX
, "%i: %8.8" PRIx32
,
1524 COMMAND_HANDLER(arm920t_handle_cp15i_command
)
1527 struct target
*target
= get_current_target(CMD_CTX
);
1528 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1530 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1531 if (retval
!= ERROR_OK
)
1535 if (target
->state
!= TARGET_HALTED
)
1537 command_print(CMD_CTX
, "target must be stopped for "
1538 "\"%s\" command", CMD_NAME
);
1542 /* one argument, read a register.
1543 * two arguments, write it.
1548 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
1553 retval
= arm920t_read_cp15_interpreted(target
,
1554 opcode
, 0x0, &value
);
1555 if (retval
!= ERROR_OK
)
1557 command_print(CMD_CTX
,
1558 "couldn't execute %8.8" PRIx32
,
1560 /* REVISIT why lie? "return retval"? */
1564 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
,
1567 else if (CMD_ARGC
== 2)
1570 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1571 retval
= arm920t_write_cp15_interpreted(target
,
1573 if (retval
!= ERROR_OK
)
1575 command_print(CMD_CTX
,
1576 "couldn't execute %8.8" PRIx32
,
1578 /* REVISIT why lie? "return retval"? */
1581 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
,
1584 else if (CMD_ARGC
== 3)
1587 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1589 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
1590 retval
= arm920t_write_cp15_interpreted(target
,
1591 opcode
, value
, address
);
1592 if (retval
!= ERROR_OK
)
1594 command_print(CMD_CTX
,
1595 "couldn't execute %8.8" PRIx32
, opcode
);
1596 /* REVISIT why lie? "return retval"? */
1599 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
1600 " %8.8" PRIx32
, opcode
, value
, address
);
1605 command_print(CMD_CTX
,
1606 "usage: arm920t cp15i <opcode> [value] [address]");
1612 COMMAND_HANDLER(arm920t_handle_cache_info_command
)
1615 struct target
*target
= get_current_target(CMD_CTX
);
1616 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1618 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1619 if (retval
!= ERROR_OK
)
1622 return armv4_5_handle_cache_info_command(CMD_CTX
,
1623 &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1627 static int arm920t_mrc(struct target
*target
, int cpnum
,
1628 uint32_t op1
, uint32_t op2
,
1629 uint32_t CRn
, uint32_t CRm
,
1634 LOG_ERROR("Only cp15 is supported");
1639 return arm920t_read_cp15_interpreted(target
,
1640 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1644 static int arm920t_mcr(struct target
*target
, int cpnum
,
1645 uint32_t op1
, uint32_t op2
,
1646 uint32_t CRn
, uint32_t CRm
,
1651 LOG_ERROR("Only cp15 is supported");
1655 /* write "from" r0 */
1656 return arm920t_write_cp15_interpreted(target
,
1657 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1661 static const struct command_registration arm920t_exec_command_handlers
[] = {
1664 .handler
= arm920t_handle_cp15_command
,
1665 .mode
= COMMAND_EXEC
,
1666 .help
= "display/modify cp15 register",
1667 .usage
= "regnum [value]",
1671 .handler
= arm920t_handle_cp15i_command
,
1672 .mode
= COMMAND_EXEC
,
1673 /* prefer using less error-prone "arm mcr" or "arm mrc" */
1674 .help
= "display/modify cp15 register using ARM opcode"
1676 .usage
= "instruction [value [address]]",
1679 .name
= "cache_info",
1680 .handler
= arm920t_handle_cache_info_command
,
1681 .mode
= COMMAND_EXEC
,
1682 .help
= "display information about target caches",
1685 .name
= "read_cache",
1686 .handler
= arm920t_handle_read_cache_command
,
1687 .mode
= COMMAND_EXEC
,
1688 .help
= "dump I/D cache content to file",
1689 .usage
= "filename",
1693 .handler
= arm920t_handle_read_mmu_command
,
1694 .mode
= COMMAND_EXEC
,
1695 .help
= "dump I/D mmu content to file",
1696 .usage
= "filename",
1698 COMMAND_REGISTRATION_DONE
1700 const struct command_registration arm920t_command_handlers
[] = {
1702 .chain
= arm9tdmi_command_handlers
,
1706 .mode
= COMMAND_ANY
,
1707 .help
= "arm920t command group",
1708 .chain
= arm920t_exec_command_handlers
,
1710 COMMAND_REGISTRATION_DONE
1713 /** Holds methods for ARM920 targets. */
1714 struct target_type arm920t_target
=
1718 .poll
= arm7_9_poll
,
1719 .arch_state
= arm920t_arch_state
,
1721 .target_request_data
= arm7_9_target_request_data
,
1723 .halt
= arm7_9_halt
,
1724 .resume
= arm7_9_resume
,
1725 .step
= arm7_9_step
,
1727 .assert_reset
= arm7_9_assert_reset
,
1728 .deassert_reset
= arm7_9_deassert_reset
,
1729 .soft_reset_halt
= arm920t_soft_reset_halt
,
1731 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
1733 .read_memory
= arm920t_read_memory
,
1734 .write_memory
= arm920t_write_memory
,
1735 .read_phys_memory
= arm920t_read_phys_memory
,
1736 .write_phys_memory
= arm920t_write_phys_memory
,
1738 .virt2phys
= arm920_virt2phys
,
1740 .bulk_write_memory
= arm7_9_bulk_write_memory
,
1742 .checksum_memory
= arm_checksum_memory
,
1743 .blank_check_memory
= arm_blank_check_memory
,
1745 .run_algorithm
= armv4_5_run_algorithm
,
1747 .add_breakpoint
= arm7_9_add_breakpoint
,
1748 .remove_breakpoint
= arm7_9_remove_breakpoint
,
1749 .add_watchpoint
= arm7_9_add_watchpoint
,
1750 .remove_watchpoint
= arm7_9_remove_watchpoint
,
1752 .commands
= arm920t_command_handlers
,
1753 .target_create
= arm920t_target_create
,
1754 .init_target
= arm9tdmi_init_target
,
1755 .examine
= arm7_9_examine
,
1756 .check_reset
= arm7_9_check_reset
,
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