1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
26 #include "arm926ejs.h"
27 #include <helper/time_support.h>
28 #include "target_type.h"
30 #include "arm_opcodes.h"
34 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
35 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
36 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
38 * 1 ... core debugging
40 * 3 ... external boundary scan (SoC-specific, unused here)
42 * 15 ... coprocessor 15
46 #define _DEBUG_INSTRUCTION_EXECUTION_
49 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
51 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
52 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
54 int retval
= ERROR_OK
;
55 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
56 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
57 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
58 struct scan_field fields
[4];
59 uint8_t address_buf
[2] = {0, 0};
63 buf_set_u32(address_buf
, 0, 14, address
);
65 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
66 if (retval
!= ERROR_OK
)
68 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
69 if (retval
!= ERROR_OK
)
72 fields
[0].num_bits
= 32;
73 fields
[0].out_value
= NULL
;
74 fields
[0].in_value
= (uint8_t *)value
;
76 fields
[1].num_bits
= 1;
77 fields
[1].out_value
= &access_t
;
78 fields
[1].in_value
= &access_t
;
80 fields
[2].num_bits
= 14;
81 fields
[2].out_value
= address_buf
;
82 fields
[2].in_value
= NULL
;
84 fields
[3].num_bits
= 1;
85 fields
[3].out_value
= &nr_w_buf
;
86 fields
[3].in_value
= NULL
;
88 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
90 int64_t then
= timeval_ms();
93 /* rescan with NOP, to wait for the access to complete */
96 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
98 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
100 retval
= jtag_execute_queue();
101 if (retval
!= ERROR_OK
)
104 if (buf_get_u32(&access_t
, 0, 1) == 1)
108 if ((timeval_ms()-then
) > 10) {
109 LOG_ERROR("cp15 read operation timed out");
114 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
115 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
118 retval
= arm_jtag_set_instr(jtag_info
->tap
, 0xc, NULL
, TAP_IDLE
);
119 if (retval
!= ERROR_OK
)
125 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
126 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
129 LOG_ERROR("Only cp15 is supported");
132 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
135 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
136 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
138 int retval
= ERROR_OK
;
139 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
140 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
141 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
142 struct scan_field fields
[4];
143 uint8_t value_buf
[4];
144 uint8_t address_buf
[2] = {0, 0};
145 uint8_t nr_w_buf
= 1;
146 uint8_t access_t
= 1;
148 buf_set_u32(address_buf
, 0, 14, address
);
149 buf_set_u32(value_buf
, 0, 32, value
);
151 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
152 if (retval
!= ERROR_OK
)
154 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
155 if (retval
!= ERROR_OK
)
158 fields
[0].num_bits
= 32;
159 fields
[0].out_value
= value_buf
;
160 fields
[0].in_value
= NULL
;
162 fields
[1].num_bits
= 1;
163 fields
[1].out_value
= &access_t
;
164 fields
[1].in_value
= &access_t
;
166 fields
[2].num_bits
= 14;
167 fields
[2].out_value
= address_buf
;
168 fields
[2].in_value
= NULL
;
170 fields
[3].num_bits
= 1;
171 fields
[3].out_value
= &nr_w_buf
;
172 fields
[3].in_value
= NULL
;
174 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
176 int64_t then
= timeval_ms();
179 /* rescan with NOP, to wait for the access to complete */
182 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
183 retval
= jtag_execute_queue();
184 if (retval
!= ERROR_OK
)
187 if (buf_get_u32(&access_t
, 0, 1) == 1)
191 if ((timeval_ms()-then
) > 10) {
192 LOG_ERROR("cp15 write operation timed out");
197 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
198 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
201 retval
= arm_jtag_set_instr(jtag_info
->tap
, 0xf, NULL
, TAP_IDLE
);
202 if (retval
!= ERROR_OK
)
208 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
209 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
212 LOG_ERROR("Only cp15 is supported");
215 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
218 static int arm926ejs_examine_debug_reason(struct target
*target
)
220 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
221 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
225 embeddedice_read_reg(dbg_stat
);
226 retval
= jtag_execute_queue();
227 if (retval
!= ERROR_OK
)
230 /* Method-Of-Entry (MOE) field */
231 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
233 switch (debug_reason
) {
235 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
236 /* ... since last restart or debug reset ... */
237 target
->debug_reason
= DBG_REASON_DBGRQ
;
240 LOG_DEBUG("breakpoint from EICE unit 0");
241 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
244 LOG_DEBUG("breakpoint from EICE unit 1");
245 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
248 LOG_DEBUG("soft breakpoint (BKPT instruction)");
249 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
252 LOG_DEBUG("vector catch breakpoint");
253 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
256 LOG_DEBUG("external breakpoint");
257 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
260 LOG_DEBUG("watchpoint from EICE unit 0");
261 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
264 LOG_DEBUG("watchpoint from EICE unit 1");
265 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
268 LOG_DEBUG("external watchpoint");
269 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
272 LOG_DEBUG("internal debug request");
273 target
->debug_reason
= DBG_REASON_DBGRQ
;
276 LOG_DEBUG("external debug request");
277 target
->debug_reason
= DBG_REASON_DBGRQ
;
280 LOG_DEBUG("debug re-entry from system speed access");
281 /* This is normal when connecting to something that's
282 * already halted, or in some related code paths, but
283 * otherwise is surprising (and presumably wrong).
285 switch (target
->debug_reason
) {
286 case DBG_REASON_DBGRQ
:
289 LOG_ERROR("unexpected -- debug re-entry");
291 case DBG_REASON_UNDEFINED
:
292 target
->debug_reason
= DBG_REASON_DBGRQ
;
297 /* FIX!!!! here be dragons!!! We need to fail here so
298 * the target will interpreted as halted but we won't
299 * try to talk to it right now... a resume + halt seems
300 * to sync things up again. Please send an email to
301 * openocd development mailing list if you have hardware
302 * to donate to look into this problem....
304 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
305 target
->debug_reason
= DBG_REASON_DBGRQ
;
308 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
309 /* Oh agony! should we interpret this as a halt request or
310 * that the target stopped on it's own accord?
312 target
->debug_reason
= DBG_REASON_DBGRQ
;
313 /* if we fail here, we won't talk to the target and it will
314 * be reported to be in the halted state */
321 static int arm926ejs_get_ttb(struct target
*target
, uint32_t *result
)
323 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
327 retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
);
328 if (retval
!= ERROR_OK
)
336 static int arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
337 int d_u_cache
, int i_cache
)
339 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
340 uint32_t cp15_control
;
343 /* read cp15 control register */
344 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
345 if (retval
!= ERROR_OK
)
347 retval
= jtag_execute_queue();
348 if (retval
!= ERROR_OK
)
353 retval
= arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
354 if (retval
!= ERROR_OK
)
357 cp15_control
&= ~0x1U
;
361 uint32_t debug_override
;
362 /* read-modify-write CP15 debug override register
363 * to enable "test and clean all" */
364 retval
= arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
365 if (retval
!= ERROR_OK
)
367 debug_override
|= 0x80000;
368 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
369 if (retval
!= ERROR_OK
)
372 /* clean and invalidate DCache */
373 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
374 if (retval
!= ERROR_OK
)
377 /* write CP15 debug override register
378 * to disable "test and clean all" */
379 debug_override
&= ~0x80000;
380 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
381 if (retval
!= ERROR_OK
)
384 cp15_control
&= ~0x4U
;
388 /* invalidate ICache */
389 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
390 if (retval
!= ERROR_OK
)
393 cp15_control
&= ~0x1000U
;
396 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
400 static int arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
401 int d_u_cache
, int i_cache
)
403 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
404 uint32_t cp15_control
;
407 /* read cp15 control register */
408 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
409 if (retval
!= ERROR_OK
)
411 retval
= jtag_execute_queue();
412 if (retval
!= ERROR_OK
)
416 cp15_control
|= 0x1U
;
419 cp15_control
|= 0x4U
;
422 cp15_control
|= 0x1000U
;
424 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
428 static int arm926ejs_post_debug_entry(struct target
*target
)
430 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
433 /* examine cp15 control reg */
434 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
435 if (retval
!= ERROR_OK
)
437 retval
= jtag_execute_queue();
438 if (retval
!= ERROR_OK
)
440 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
442 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1) {
443 uint32_t cache_type_reg
;
444 /* identify caches */
445 retval
= arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
446 if (retval
!= ERROR_OK
)
448 retval
= jtag_execute_queue();
449 if (retval
!= ERROR_OK
)
451 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
454 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
455 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
456 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
458 /* save i/d fault status and address register */
459 retval
= arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
460 if (retval
!= ERROR_OK
)
462 retval
= arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
463 if (retval
!= ERROR_OK
)
465 retval
= arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
466 if (retval
!= ERROR_OK
)
469 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
470 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
472 uint32_t cache_dbg_ctrl
;
474 /* read-modify-write CP15 cache debug control register
475 * to disable I/D-cache linefills and force WT */
476 retval
= arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
477 if (retval
!= ERROR_OK
)
479 cache_dbg_ctrl
|= 0x7;
480 retval
= arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
484 static void arm926ejs_pre_restore_context(struct target
*target
)
486 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
488 /* restore i/d fault status and address register */
489 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
490 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
491 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
493 uint32_t cache_dbg_ctrl
;
495 /* read-modify-write CP15 cache debug control register
496 * to reenable I/D-cache linefills and disable WT */
497 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
498 cache_dbg_ctrl
&= ~0x7;
499 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
502 static const char arm926_not
[] = "target is not an ARM926";
504 static int arm926ejs_verify_pointer(struct command_invocation
*cmd
,
505 struct arm926ejs_common
*arm926
)
507 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
508 command_print(cmd
, arm926_not
);
509 return ERROR_TARGET_INVALID
;
514 /** Logs summary of ARM926 state for a halted target. */
515 int arm926ejs_arch_state(struct target
*target
)
517 static const char *state
[] = {
518 "disabled", "enabled"
521 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
523 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
524 LOG_ERROR("BUG: %s", arm926_not
);
525 return ERROR_TARGET_INVALID
;
528 arm_arch_state(target
);
529 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
530 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
531 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
532 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
537 int arm926ejs_soft_reset_halt(struct target
*target
)
539 int retval
= ERROR_OK
;
540 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
541 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
542 struct arm
*arm
= &arm7_9
->arm
;
543 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
545 retval
= target_halt(target
);
546 if (retval
!= ERROR_OK
)
549 int64_t then
= timeval_ms();
551 while (!(timeout
= ((timeval_ms()-then
) > 1000))) {
552 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0) {
553 embeddedice_read_reg(dbg_stat
);
554 retval
= jtag_execute_queue();
555 if (retval
!= ERROR_OK
)
559 if (debug_level
>= 1) {
560 /* do not eat all CPU, time out after 1 se*/
566 LOG_ERROR("Failed to halt CPU after 1 sec");
567 return ERROR_TARGET_TIMEOUT
;
570 target
->state
= TARGET_HALTED
;
572 /* SVC, ARM state, IRQ and FIQ disabled */
575 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
578 arm_set_cpsr(arm
, cpsr
);
579 arm
->cpsr
->dirty
= true;
581 /* start fetching from 0x0 */
582 buf_set_u32(arm
->pc
->value
, 0, 32, 0x0);
583 arm
->pc
->dirty
= true;
584 arm
->pc
->valid
= true;
586 retval
= arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
587 if (retval
!= ERROR_OK
)
589 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
590 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
591 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
593 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
596 /** Writes a buffer, in the specified word size, with current MMU settings. */
597 int arm926ejs_write_memory(struct target
*target
, target_addr_t address
,
598 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
601 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
603 /* FIX!!!! this should be cleaned up and made much more general. The
604 * plan is to write up and test on arm926ejs specifically and
605 * then generalize and clean up afterwards.
608 * Also it should be moved to the callbacks that handle breakpoints
609 * specifically and not the generic memory write fn's. See XScale code.
611 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
== 2) || (size
== 4))) {
612 /* special case the handling of single word writes to bypass MMU
613 * to allow implementation of breakpoints in memory marked read only
615 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
616 /* flush and invalidate data cache
618 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
621 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
622 if (retval
!= ERROR_OK
)
627 retval
= target
->type
->virt2phys(target
, address
, &pa
);
628 if (retval
!= ERROR_OK
)
631 /* write directly to physical memory bypassing any read only MMU bits, etc. */
632 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
633 if (retval
!= ERROR_OK
)
636 retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
);
637 if (retval
!= ERROR_OK
)
641 /* If ICache is enabled, we have to invalidate affected ICache lines
642 * the DCache is forced to write-through, so we don't have to clean it here
644 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) {
646 /* invalidate ICache single entry with MVA */
647 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
649 /* invalidate ICache */
650 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
657 static int arm926ejs_write_phys_memory(struct target
*target
,
658 target_addr_t address
, uint32_t size
,
659 uint32_t count
, const uint8_t *buffer
)
661 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
663 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
664 address
, size
, count
, buffer
);
667 static int arm926ejs_read_phys_memory(struct target
*target
,
668 target_addr_t address
, uint32_t size
,
669 uint32_t count
, uint8_t *buffer
)
671 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
673 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
674 address
, size
, count
, buffer
);
677 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
678 struct jtag_tap
*tap
)
680 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
682 arm7_9
->arm
.mrc
= arm926ejs_mrc
;
683 arm7_9
->arm
.mcr
= arm926ejs_mcr
;
685 /* initialize arm7/arm9 specific info (including armv4_5) */
686 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
688 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
690 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
691 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
692 arm7_9
->write_memory
= arm926ejs_write_memory
;
694 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
695 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
696 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
697 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
698 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
699 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
700 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
701 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
702 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
703 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
705 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
707 /* The ARM926EJ-S implements the ARMv5TE architecture which
708 * has the BKPT instruction, so we don't have to use a watchpoint comparator
710 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
711 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
716 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
718 struct arm926ejs_common
*arm926ejs
= calloc(1, sizeof(struct arm926ejs_common
));
720 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
721 target
->tap
->ir_capture_mask
= 0x0f;
723 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
726 static void arm926ejs_deinit_target(struct target
*target
)
728 struct arm
*arm
= target_to_arm(target
);
729 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
731 arm7_9_deinit(target
);
732 arm_free_reg_cache(arm
);
736 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
739 struct target
*target
= get_current_target(CMD_CTX
);
740 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
742 retval
= arm926ejs_verify_pointer(CMD
, arm926ejs
);
743 if (retval
!= ERROR_OK
)
746 return armv4_5_handle_cache_info_command(CMD
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
749 static int arm926ejs_virt2phys(struct target
*target
, target_addr_t
virtual, target_addr_t
*physical
)
752 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
755 int retval
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
,
757 if (retval
!= ERROR_OK
)
763 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
765 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
767 if (target
->state
!= TARGET_HALTED
) {
768 LOG_ERROR("Target not halted");
769 return ERROR_TARGET_INVALID
;
771 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
775 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
777 .name
= "cache_info",
778 .handler
= arm926ejs_handle_cache_info_command
,
779 .mode
= COMMAND_EXEC
,
781 .help
= "display information about target caches",
784 COMMAND_REGISTRATION_DONE
786 const struct command_registration arm926ejs_command_handlers
[] = {
788 .chain
= arm9tdmi_command_handlers
,
793 .help
= "arm926ejs command group",
795 .chain
= arm926ejs_exec_command_handlers
,
797 COMMAND_REGISTRATION_DONE
800 /** Holds methods for ARM926 targets. */
801 struct target_type arm926ejs_target
= {
805 .arch_state
= arm926ejs_arch_state
,
807 .target_request_data
= arm7_9_target_request_data
,
810 .resume
= arm7_9_resume
,
813 .assert_reset
= arm7_9_assert_reset
,
814 .deassert_reset
= arm7_9_deassert_reset
,
815 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
817 .get_gdb_arch
= arm_get_gdb_arch
,
818 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
820 .read_memory
= arm7_9_read_memory
,
821 .write_memory
= arm7_9_write_memory_opt
,
823 .checksum_memory
= arm_checksum_memory
,
824 .blank_check_memory
= arm_blank_check_memory
,
826 .run_algorithm
= armv4_5_run_algorithm
,
828 .add_breakpoint
= arm7_9_add_breakpoint
,
829 .remove_breakpoint
= arm7_9_remove_breakpoint
,
830 .add_watchpoint
= arm7_9_add_watchpoint
,
831 .remove_watchpoint
= arm7_9_remove_watchpoint
,
833 .commands
= arm926ejs_command_handlers
,
834 .target_create
= arm926ejs_target_create
,
835 .init_target
= arm9tdmi_init_target
,
836 .deinit_target
= arm926ejs_deinit_target
,
837 .examine
= arm7_9_examine
,
838 .check_reset
= arm7_9_check_reset
,
839 .virt2phys
= arm926ejs_virt2phys
,
840 .mmu
= arm926ejs_mmu
,
842 .read_phys_memory
= arm926ejs_read_phys_memory
,
843 .write_phys_memory
= arm926ejs_write_phys_memory
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)