1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
25 #include "time_support.h"
26 #include "target_type.h"
30 #define _DEBUG_INSTRUCTION_EXECUTION_
34 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
35 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
36 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
37 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
38 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 /* forward declarations */
45 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
);
46 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm926ejs_quit(void);
48 int arm926ejs_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
50 static int arm926ejs_virt2phys(struct target_s
*target
, uint32_t virtual, uint32_t *physical
);
51 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
);
53 target_type_t arm926ejs_target
=
58 .arch_state
= arm926ejs_arch_state
,
60 .target_request_data
= arm7_9_target_request_data
,
63 .resume
= arm7_9_resume
,
66 .assert_reset
= arm7_9_assert_reset
,
67 .deassert_reset
= arm7_9_deassert_reset
,
68 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
70 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
72 .read_memory
= arm7_9_read_memory
,
73 .write_memory
= arm926ejs_write_memory
,
74 .bulk_write_memory
= arm7_9_bulk_write_memory
,
75 .checksum_memory
= arm7_9_checksum_memory
,
76 .blank_check_memory
= arm7_9_blank_check_memory
,
78 .run_algorithm
= armv4_5_run_algorithm
,
80 .add_breakpoint
= arm7_9_add_breakpoint
,
81 .remove_breakpoint
= arm7_9_remove_breakpoint
,
82 .add_watchpoint
= arm7_9_add_watchpoint
,
83 .remove_watchpoint
= arm7_9_remove_watchpoint
,
85 .register_commands
= arm926ejs_register_commands
,
86 .target_create
= arm926ejs_target_create
,
87 .init_target
= arm926ejs_init_target
,
88 .examine
= arm9tdmi_examine
,
89 .quit
= arm926ejs_quit
,
90 .virt2phys
= arm926ejs_virt2phys
,
94 int arm926ejs_catch_broken_irscan(uint8_t *captured
, void *priv
, scan_field_t
*field
)
96 /* FIX!!!! this code should be reenabled. For now it does not check
100 /* The ARM926EJ-S' instruction register is 4 bits wide */
101 uint8_t t
= *captured
& 0xf;
102 uint8_t t2
= *field
->in_check_value
& 0xf;
107 else if ((t
== 0x0f) || (t
== 0x00))
109 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
112 return ERROR_JTAG_QUEUE_FAILED
;;
116 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
118 int arm926ejs_cp15_read(target_t
*target
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
120 int retval
= ERROR_OK
;
121 armv4_5_common_t
*armv4_5
= target
->arch_info
;
122 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
123 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
124 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
125 scan_field_t fields
[4];
126 uint8_t address_buf
[2];
127 uint8_t nr_w_buf
= 0;
130 buf_set_u32(address_buf
, 0, 14, address
);
132 jtag_set_end_state(TAP_IDLE
);
133 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
137 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
139 fields
[0].tap
= jtag_info
->tap
;
140 fields
[0].num_bits
= 32;
141 fields
[0].out_value
= NULL
;
142 fields
[0].in_value
= (uint8_t *)value
;
145 fields
[1].tap
= jtag_info
->tap
;
146 fields
[1].num_bits
= 1;
147 fields
[1].out_value
= &access
;
148 fields
[1].in_value
= &access
;
150 fields
[2].tap
= jtag_info
->tap
;
151 fields
[2].num_bits
= 14;
152 fields
[2].out_value
= address_buf
;
153 fields
[2].in_value
= NULL
;
155 fields
[3].tap
= jtag_info
->tap
;
156 fields
[3].num_bits
= 1;
157 fields
[3].out_value
= &nr_w_buf
;
158 fields
[3].in_value
= NULL
;
160 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
162 long long then
= timeval_ms();
166 /* rescan with NOP, to wait for the access to complete */
169 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
171 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
173 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
178 if (buf_get_u32(&access
, 0, 1) == 1)
184 if ((timeval_ms()-then
)>10)
186 LOG_ERROR("cp15 read operation timed out");
191 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
192 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
195 arm_jtag_set_instr(jtag_info
, 0xc, &arm926ejs_catch_broken_irscan
);
200 int arm926ejs_cp15_write(target_t
*target
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
202 int retval
= ERROR_OK
;
203 armv4_5_common_t
*armv4_5
= target
->arch_info
;
204 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
205 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
206 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
207 scan_field_t fields
[4];
208 uint8_t value_buf
[4];
209 uint8_t address_buf
[2];
210 uint8_t nr_w_buf
= 1;
213 buf_set_u32(address_buf
, 0, 14, address
);
214 buf_set_u32(value_buf
, 0, 32, value
);
216 jtag_set_end_state(TAP_IDLE
);
217 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
221 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
223 fields
[0].tap
= jtag_info
->tap
;
224 fields
[0].num_bits
= 32;
225 fields
[0].out_value
= value_buf
;
226 fields
[0].in_value
= NULL
;
228 fields
[1].tap
= jtag_info
->tap
;
229 fields
[1].num_bits
= 1;
230 fields
[1].out_value
= &access
;
231 fields
[1].in_value
= &access
;
233 fields
[2].tap
= jtag_info
->tap
;
234 fields
[2].num_bits
= 14;
235 fields
[2].out_value
= address_buf
;
236 fields
[2].in_value
= NULL
;
238 fields
[3].tap
= jtag_info
->tap
;
239 fields
[3].num_bits
= 1;
240 fields
[3].out_value
= &nr_w_buf
;
241 fields
[3].in_value
= NULL
;
243 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
245 long long then
= timeval_ms();
249 /* rescan with NOP, to wait for the access to complete */
252 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
253 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
258 if (buf_get_u32(&access
, 0, 1) == 1)
264 if ((timeval_ms()-then
)>10)
266 LOG_ERROR("cp15 write operation timed out");
271 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
272 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
275 arm_jtag_set_instr(jtag_info
, 0xf, &arm926ejs_catch_broken_irscan
);
280 static int arm926ejs_examine_debug_reason(target_t
*target
)
282 armv4_5_common_t
*armv4_5
= target
->arch_info
;
283 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
284 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
288 embeddedice_read_reg(dbg_stat
);
289 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
292 /* Method-Of-Entry (MOE) field */
293 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
295 switch (debug_reason
)
298 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
299 /* ... since last restart or debug reset ... */
300 target
->debug_reason
= DBG_REASON_DBGRQ
;
303 LOG_DEBUG("breakpoint from EICE unit 0");
304 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
307 LOG_DEBUG("breakpoint from EICE unit 1");
308 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
311 LOG_DEBUG("soft breakpoint (BKPT instruction)");
312 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
315 LOG_DEBUG("vector catch breakpoint");
316 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
319 LOG_DEBUG("external breakpoint");
320 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
323 LOG_DEBUG("watchpoint from EICE unit 0");
324 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
327 LOG_DEBUG("watchpoint from EICE unit 1");
328 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
331 LOG_DEBUG("external watchpoint");
332 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
335 LOG_DEBUG("internal debug request");
336 target
->debug_reason
= DBG_REASON_DBGRQ
;
339 LOG_DEBUG("external debug request");
340 target
->debug_reason
= DBG_REASON_DBGRQ
;
343 LOG_DEBUG("debug re-entry from system speed access");
344 /* This is normal when connecting to something that's
345 * already halted, or in some related code paths, but
346 * otherwise is surprising (and presumably wrong).
348 switch (target
->debug_reason
) {
349 case DBG_REASON_DBGRQ
:
352 LOG_ERROR("unexpected -- debug re-entry");
354 case DBG_REASON_UNDEFINED
:
355 target
->debug_reason
= DBG_REASON_DBGRQ
;
360 /* FIX!!!! here be dragons!!! We need to fail here so
361 * the target will interpreted as halted but we won't
362 * try to talk to it right now... a resume + halt seems
363 * to sync things up again. Please send an email to
364 * openocd development mailing list if you have hardware
365 * to donate to look into this problem....
367 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
368 target
->debug_reason
= DBG_REASON_DBGRQ
;
371 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
372 /* Oh agony! should we interpret this as a halt request or
373 * that the target stopped on it's own accord?
375 target
->debug_reason
= DBG_REASON_DBGRQ
;
376 /* if we fail here, we won't talk to the target and it will
377 * be reported to be in the halted state */
384 uint32_t arm926ejs_get_ttb(target_t
*target
)
386 armv4_5_common_t
*armv4_5
= target
->arch_info
;
387 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
388 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
389 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
393 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
399 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
401 armv4_5_common_t
*armv4_5
= target
->arch_info
;
402 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
403 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
404 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
405 uint32_t cp15_control
;
407 /* read cp15 control register */
408 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
409 jtag_execute_queue();
414 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
416 cp15_control
&= ~0x1U
;
421 uint32_t debug_override
;
422 /* read-modify-write CP15 debug override register
423 * to enable "test and clean all" */
424 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
425 debug_override
|= 0x80000;
426 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
428 /* clean and invalidate DCache */
429 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
431 /* write CP15 debug override register
432 * to disable "test and clean all" */
433 debug_override
&= ~0x80000;
434 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
436 cp15_control
&= ~0x4U
;
441 /* invalidate ICache */
442 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
444 cp15_control
&= ~0x1000U
;
447 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
450 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
452 armv4_5_common_t
*armv4_5
= target
->arch_info
;
453 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
454 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
455 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
456 uint32_t cp15_control
;
458 /* read cp15 control register */
459 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
460 jtag_execute_queue();
463 cp15_control
|= 0x1U
;
466 cp15_control
|= 0x4U
;
469 cp15_control
|= 0x1000U
;
471 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
474 void arm926ejs_post_debug_entry(target_t
*target
)
476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
477 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
478 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
479 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
481 /* examine cp15 control reg */
482 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
483 jtag_execute_queue();
484 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
486 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
488 uint32_t cache_type_reg
;
489 /* identify caches */
490 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
491 jtag_execute_queue();
492 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
495 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
496 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
497 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
499 /* save i/d fault status and address register */
500 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
501 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
502 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
504 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
505 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
507 uint32_t cache_dbg_ctrl
;
509 /* read-modify-write CP15 cache debug control register
510 * to disable I/D-cache linefills and force WT */
511 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
512 cache_dbg_ctrl
|= 0x7;
513 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
516 void arm926ejs_pre_restore_context(target_t
*target
)
518 armv4_5_common_t
*armv4_5
= target
->arch_info
;
519 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
520 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
521 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
523 /* restore i/d fault status and address register */
524 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
525 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
526 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
528 uint32_t cache_dbg_ctrl
;
530 /* read-modify-write CP15 cache debug control register
531 * to reenable I/D-cache linefills and disable WT */
532 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
533 cache_dbg_ctrl
&= ~0x7;
534 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
537 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
539 armv4_5_common_t
*armv4_5
= target
->arch_info
;
540 arm7_9_common_t
*arm7_9
;
541 arm9tdmi_common_t
*arm9tdmi
;
542 arm926ejs_common_t
*arm926ejs
;
544 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
549 arm7_9
= armv4_5
->arch_info
;
550 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
555 arm9tdmi
= arm7_9
->arch_info
;
556 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
561 arm926ejs
= arm9tdmi
->arch_info
;
562 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
567 *armv4_5_p
= armv4_5
;
569 *arm9tdmi_p
= arm9tdmi
;
570 *arm926ejs_p
= arm926ejs
;
575 int arm926ejs_arch_state(struct target_s
*target
)
577 armv4_5_common_t
*armv4_5
= target
->arch_info
;
578 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
579 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
580 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
584 "disabled", "enabled"
587 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
589 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
594 "target halted in %s state due to %s, current mode: %s\n"
595 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
596 "MMU: %s, D-Cache: %s, I-Cache: %s",
597 armv4_5_state_strings
[armv4_5
->core_state
],
598 Jim_Nvp_value2name_simple(nvp_target_debug_reason
,target
->debug_reason
)->name
,
599 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
600 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
601 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
602 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
603 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
604 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
609 int arm926ejs_soft_reset_halt(struct target_s
*target
)
611 int retval
= ERROR_OK
;
612 armv4_5_common_t
*armv4_5
= target
->arch_info
;
613 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
614 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
615 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
616 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
618 if ((retval
= target_halt(target
)) != ERROR_OK
)
623 long long then
= timeval_ms();
625 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
627 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
629 embeddedice_read_reg(dbg_stat
);
630 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
638 if (debug_level
>= 1)
640 /* do not eat all CPU, time out after 1 se*/
649 LOG_ERROR("Failed to halt CPU after 1 sec");
650 return ERROR_TARGET_TIMEOUT
;
653 target
->state
= TARGET_HALTED
;
655 /* SVC, ARM state, IRQ and FIQ disabled */
656 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
657 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
658 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
660 /* start fetching from 0x0 */
661 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
662 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
663 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
665 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
666 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
668 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
669 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
670 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
671 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
673 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
676 int arm926ejs_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
679 armv4_5_common_t
*armv4_5
= target
->arch_info
;
680 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
681 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
682 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
684 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
687 /* If ICache is enabled, we have to invalidate affected ICache lines
688 * the DCache is forced to write-through, so we don't have to clean it here
690 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
694 /* invalidate ICache single entry with MVA */
695 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
699 /* invalidate ICache */
700 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
707 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
709 arm9tdmi_init_target(cmd_ctx
, target
);
714 int arm926ejs_quit(void)
719 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, jtag_tap_t
*tap
)
721 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
722 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
724 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
726 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
728 arm9tdmi
->arch_info
= arm926ejs
;
729 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
731 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
732 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
734 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
735 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
736 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
737 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
738 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
739 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
740 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
741 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
742 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
743 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
745 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
747 /* The ARM926EJ-S implements the ARMv5TE architecture which
748 * has the BKPT instruction, so we don't have to use a watchpoint comparator
750 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
751 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
756 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
)
758 arm926ejs_common_t
*arm926ejs
= calloc(1,sizeof(arm926ejs_common_t
));
760 arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
765 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
768 command_t
*arm926ejs_cmd
;
771 retval
= arm9tdmi_register_commands(cmd_ctx
);
773 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
775 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
777 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
778 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
780 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
781 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
782 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
784 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
785 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
786 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
791 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
794 target_t
*target
= get_current_target(cmd_ctx
);
795 armv4_5_common_t
*armv4_5
;
796 arm7_9_common_t
*arm7_9
;
797 arm9tdmi_common_t
*arm9tdmi
;
798 arm926ejs_common_t
*arm926ejs
;
804 if ((argc
< 4) || (argc
> 5))
806 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
810 opcode_1
= strtoul(args
[0], NULL
, 0);
811 opcode_2
= strtoul(args
[1], NULL
, 0);
812 CRn
= strtoul(args
[2], NULL
, 0);
813 CRm
= strtoul(args
[3], NULL
, 0);
815 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
817 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
821 if (target
->state
!= TARGET_HALTED
)
823 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
830 if ((retval
= arm926ejs
->read_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, &value
)) != ERROR_OK
)
832 command_print(cmd_ctx
, "couldn't access register");
835 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
840 command_print(cmd_ctx
, "%i %i %i %i: %8.8" PRIx32
"", opcode_1
, opcode_2
, CRn
, CRm
, value
);
844 uint32_t value
= strtoul(args
[4], NULL
, 0);
845 if ((retval
= arm926ejs
->write_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, value
)) != ERROR_OK
)
847 command_print(cmd_ctx
, "couldn't access register");
850 command_print(cmd_ctx
, "%i %i %i %i: %8.8" PRIx32
"", opcode_1
, opcode_2
, CRn
, CRm
, value
);
856 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
858 target_t
*target
= get_current_target(cmd_ctx
);
859 armv4_5_common_t
*armv4_5
;
860 arm7_9_common_t
*arm7_9
;
861 arm9tdmi_common_t
*arm9tdmi
;
862 arm926ejs_common_t
*arm926ejs
;
864 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
866 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
870 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
873 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
875 target_t
*target
= get_current_target(cmd_ctx
);
876 armv4_5_common_t
*armv4_5
;
877 arm7_9_common_t
*arm7_9
;
878 arm9tdmi_common_t
*arm9tdmi
;
879 arm926ejs_common_t
*arm926ejs
;
880 arm_jtag_t
*jtag_info
;
882 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
884 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
888 jtag_info
= &arm7_9
->jtag_info
;
890 if (target
->state
!= TARGET_HALTED
)
892 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
896 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
899 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
901 target_t
*target
= get_current_target(cmd_ctx
);
902 armv4_5_common_t
*armv4_5
;
903 arm7_9_common_t
*arm7_9
;
904 arm9tdmi_common_t
*arm9tdmi
;
905 arm926ejs_common_t
*arm926ejs
;
906 arm_jtag_t
*jtag_info
;
908 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
910 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
914 jtag_info
= &arm7_9
->jtag_info
;
916 if (target
->state
!= TARGET_HALTED
)
918 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
922 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
925 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
927 target_t
*target
= get_current_target(cmd_ctx
);
928 armv4_5_common_t
*armv4_5
;
929 arm7_9_common_t
*arm7_9
;
930 arm9tdmi_common_t
*arm9tdmi
;
931 arm926ejs_common_t
*arm926ejs
;
932 arm_jtag_t
*jtag_info
;
934 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
936 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
940 jtag_info
= &arm7_9
->jtag_info
;
942 if (target
->state
!= TARGET_HALTED
)
944 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
948 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
951 static int arm926ejs_virt2phys(struct target_s
*target
, uint32_t virtual, uint32_t *physical
)
959 armv4_5_common_t
*armv4_5
;
960 arm7_9_common_t
*arm7_9
;
961 arm9tdmi_common_t
*arm9tdmi
;
962 arm926ejs_common_t
*arm926ejs
;
963 retval
= arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
);
964 if (retval
!= ERROR_OK
)
968 uint32_t ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
977 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
)
979 armv4_5_common_t
*armv4_5
= target
->arch_info
;
980 arm926ejs_common_t
*arm926ejs
= armv4_5
->arch_info
;
982 if (target
->state
!= TARGET_HALTED
)
984 LOG_ERROR("Target not halted");
985 return ERROR_TARGET_INVALID
;
987 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
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