1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
34 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
35 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
36 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
38 * 1 ... core debugging
40 * 3 ... external boundary scan (SoC-specific, unused here)
42 * 15 ... coprocessor 15
46 #define _DEBUG_INSTRUCTION_EXECUTION_
49 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
51 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
52 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
54 int retval
= ERROR_OK
;
55 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
56 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
57 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
58 struct scan_field fields
[4];
59 uint8_t address_buf
[2] = {0, 0};
63 buf_set_u32(address_buf
, 0, 14, address
);
65 jtag_set_end_state(TAP_IDLE
);
66 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
70 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
72 fields
[0].tap
= jtag_info
->tap
;
73 fields
[0].num_bits
= 32;
74 fields
[0].out_value
= NULL
;
75 fields
[0].in_value
= (uint8_t *)value
;
78 fields
[1].tap
= jtag_info
->tap
;
79 fields
[1].num_bits
= 1;
80 fields
[1].out_value
= &access
;
81 fields
[1].in_value
= &access
;
83 fields
[2].tap
= jtag_info
->tap
;
84 fields
[2].num_bits
= 14;
85 fields
[2].out_value
= address_buf
;
86 fields
[2].in_value
= NULL
;
88 fields
[3].tap
= jtag_info
->tap
;
89 fields
[3].num_bits
= 1;
90 fields
[3].out_value
= &nr_w_buf
;
91 fields
[3].in_value
= NULL
;
93 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
95 long long then
= timeval_ms();
99 /* rescan with NOP, to wait for the access to complete */
102 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
104 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
106 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
111 if (buf_get_u32(&access
, 0, 1) == 1)
117 if ((timeval_ms()-then
)>10)
119 LOG_ERROR("cp15 read operation timed out");
124 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
125 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
128 arm_jtag_set_instr(jtag_info
, 0xc, NULL
);
133 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
134 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
137 LOG_ERROR("Only cp15 is supported");
140 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
143 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
144 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
146 int retval
= ERROR_OK
;
147 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
148 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
149 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
150 struct scan_field fields
[4];
151 uint8_t value_buf
[4];
152 uint8_t address_buf
[2] = {0, 0};
153 uint8_t nr_w_buf
= 1;
156 buf_set_u32(address_buf
, 0, 14, address
);
157 buf_set_u32(value_buf
, 0, 32, value
);
159 jtag_set_end_state(TAP_IDLE
);
160 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
164 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
166 fields
[0].tap
= jtag_info
->tap
;
167 fields
[0].num_bits
= 32;
168 fields
[0].out_value
= value_buf
;
169 fields
[0].in_value
= NULL
;
171 fields
[1].tap
= jtag_info
->tap
;
172 fields
[1].num_bits
= 1;
173 fields
[1].out_value
= &access
;
174 fields
[1].in_value
= &access
;
176 fields
[2].tap
= jtag_info
->tap
;
177 fields
[2].num_bits
= 14;
178 fields
[2].out_value
= address_buf
;
179 fields
[2].in_value
= NULL
;
181 fields
[3].tap
= jtag_info
->tap
;
182 fields
[3].num_bits
= 1;
183 fields
[3].out_value
= &nr_w_buf
;
184 fields
[3].in_value
= NULL
;
186 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
188 long long then
= timeval_ms();
192 /* rescan with NOP, to wait for the access to complete */
195 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
196 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
201 if (buf_get_u32(&access
, 0, 1) == 1)
207 if ((timeval_ms()-then
)>10)
209 LOG_ERROR("cp15 write operation timed out");
214 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
215 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
218 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
223 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
224 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
227 LOG_ERROR("Only cp15 is supported");
230 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
233 static int arm926ejs_examine_debug_reason(struct target
*target
)
235 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
236 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
240 embeddedice_read_reg(dbg_stat
);
241 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
244 /* Method-Of-Entry (MOE) field */
245 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
247 switch (debug_reason
)
250 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
251 /* ... since last restart or debug reset ... */
252 target
->debug_reason
= DBG_REASON_DBGRQ
;
255 LOG_DEBUG("breakpoint from EICE unit 0");
256 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
259 LOG_DEBUG("breakpoint from EICE unit 1");
260 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
263 LOG_DEBUG("soft breakpoint (BKPT instruction)");
264 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
267 LOG_DEBUG("vector catch breakpoint");
268 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
271 LOG_DEBUG("external breakpoint");
272 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
275 LOG_DEBUG("watchpoint from EICE unit 0");
276 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
279 LOG_DEBUG("watchpoint from EICE unit 1");
280 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
283 LOG_DEBUG("external watchpoint");
284 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
287 LOG_DEBUG("internal debug request");
288 target
->debug_reason
= DBG_REASON_DBGRQ
;
291 LOG_DEBUG("external debug request");
292 target
->debug_reason
= DBG_REASON_DBGRQ
;
295 LOG_DEBUG("debug re-entry from system speed access");
296 /* This is normal when connecting to something that's
297 * already halted, or in some related code paths, but
298 * otherwise is surprising (and presumably wrong).
300 switch (target
->debug_reason
) {
301 case DBG_REASON_DBGRQ
:
304 LOG_ERROR("unexpected -- debug re-entry");
306 case DBG_REASON_UNDEFINED
:
307 target
->debug_reason
= DBG_REASON_DBGRQ
;
312 /* FIX!!!! here be dragons!!! We need to fail here so
313 * the target will interpreted as halted but we won't
314 * try to talk to it right now... a resume + halt seems
315 * to sync things up again. Please send an email to
316 * openocd development mailing list if you have hardware
317 * to donate to look into this problem....
319 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
320 target
->debug_reason
= DBG_REASON_DBGRQ
;
323 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
324 /* Oh agony! should we interpret this as a halt request or
325 * that the target stopped on it's own accord?
327 target
->debug_reason
= DBG_REASON_DBGRQ
;
328 /* if we fail here, we won't talk to the target and it will
329 * be reported to be in the halted state */
336 static uint32_t arm926ejs_get_ttb(struct target
*target
)
338 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
342 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
348 static void arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
349 int d_u_cache
, int i_cache
)
351 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
352 uint32_t cp15_control
;
354 /* read cp15 control register */
355 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
356 jtag_execute_queue();
361 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
363 cp15_control
&= ~0x1U
;
368 uint32_t debug_override
;
369 /* read-modify-write CP15 debug override register
370 * to enable "test and clean all" */
371 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
372 debug_override
|= 0x80000;
373 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
375 /* clean and invalidate DCache */
376 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
378 /* write CP15 debug override register
379 * to disable "test and clean all" */
380 debug_override
&= ~0x80000;
381 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
383 cp15_control
&= ~0x4U
;
388 /* invalidate ICache */
389 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
391 cp15_control
&= ~0x1000U
;
394 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
397 static void arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
398 int d_u_cache
, int i_cache
)
400 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
401 uint32_t cp15_control
;
403 /* read cp15 control register */
404 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
405 jtag_execute_queue();
408 cp15_control
|= 0x1U
;
411 cp15_control
|= 0x4U
;
414 cp15_control
|= 0x1000U
;
416 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
419 static void arm926ejs_post_debug_entry(struct target
*target
)
421 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
423 /* examine cp15 control reg */
424 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
425 jtag_execute_queue();
426 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
428 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
430 uint32_t cache_type_reg
;
431 /* identify caches */
432 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
433 jtag_execute_queue();
434 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
437 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
438 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
439 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
441 /* save i/d fault status and address register */
442 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
443 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
444 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
446 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
447 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
449 uint32_t cache_dbg_ctrl
;
451 /* read-modify-write CP15 cache debug control register
452 * to disable I/D-cache linefills and force WT */
453 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
454 cache_dbg_ctrl
|= 0x7;
455 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
458 static void arm926ejs_pre_restore_context(struct target
*target
)
460 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
462 /* restore i/d fault status and address register */
463 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
464 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
465 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
467 uint32_t cache_dbg_ctrl
;
469 /* read-modify-write CP15 cache debug control register
470 * to reenable I/D-cache linefills and disable WT */
471 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
472 cache_dbg_ctrl
&= ~0x7;
473 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
476 static const char arm926_not
[] = "target is not an ARM926";
478 static int arm926ejs_verify_pointer(struct command_context
*cmd_ctx
,
479 struct arm926ejs_common
*arm926
)
481 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
482 command_print(cmd_ctx
, arm926_not
);
483 return ERROR_TARGET_INVALID
;
488 /** Logs summary of ARM926 state for a halted target. */
489 int arm926ejs_arch_state(struct target
*target
)
491 static const char *state
[] =
493 "disabled", "enabled"
496 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
499 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
501 LOG_ERROR("BUG: %s", arm926_not
);
502 return ERROR_TARGET_INVALID
;
505 armv4_5
= &arm926ejs
->arm7_9_common
.armv4_5_common
;
507 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
508 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
509 "MMU: %s, D-Cache: %s, I-Cache: %s",
510 armv4_5_state_strings
[armv4_5
->core_state
],
511 Jim_Nvp_value2name_simple(nvp_target_debug_reason
,target
->debug_reason
)->name
,
512 arm_mode_name(armv4_5
->core_mode
),
513 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32),
514 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
515 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
516 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
517 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
522 int arm926ejs_soft_reset_halt(struct target
*target
)
524 int retval
= ERROR_OK
;
525 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
526 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
527 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
528 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
530 if ((retval
= target_halt(target
)) != ERROR_OK
)
535 long long then
= timeval_ms();
537 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
539 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
541 embeddedice_read_reg(dbg_stat
);
542 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
550 if (debug_level
>= 1)
552 /* do not eat all CPU, time out after 1 se*/
561 LOG_ERROR("Failed to halt CPU after 1 sec");
562 return ERROR_TARGET_TIMEOUT
;
565 target
->state
= TARGET_HALTED
;
567 /* SVC, ARM state, IRQ and FIQ disabled */
570 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
573 arm_set_cpsr(armv4_5
, cpsr
);
574 armv4_5
->cpsr
->dirty
= 1;
576 /* start fetching from 0x0 */
577 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
578 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
579 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
581 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
582 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
583 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
584 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
586 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
589 /** Writes a buffer, in the specified word size, with current MMU settings. */
590 int arm926ejs_write_memory(struct target
*target
, uint32_t address
,
591 uint32_t size
, uint32_t count
, uint8_t *buffer
)
594 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
596 /* FIX!!!! this should be cleaned up and made much more general. The
597 * plan is to write up and test on arm926ejs specifically and
598 * then generalize and clean up afterwards. */
599 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
==2) || (size
==4)))
601 /* special case the handling of single word writes to bypass MMU
602 * to allow implementation of breakpoints in memory marked read only
604 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
606 /* flush and invalidate data cache
608 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
611 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
612 if (retval
!= ERROR_OK
)
617 retval
= target
->type
->virt2phys(target
, address
, &pa
);
618 if (retval
!= ERROR_OK
)
621 /* write directly to physical memory bypassing any read only MMU bits, etc. */
622 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
623 if (retval
!= ERROR_OK
)
627 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
631 /* If ICache is enabled, we have to invalidate affected ICache lines
632 * the DCache is forced to write-through, so we don't have to clean it here
634 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
638 /* invalidate ICache single entry with MVA */
639 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
643 /* invalidate ICache */
644 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
651 static int arm926ejs_write_phys_memory(struct target
*target
,
652 uint32_t address
, uint32_t size
,
653 uint32_t count
, uint8_t *buffer
)
655 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
657 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
658 address
, size
, count
, buffer
);
661 static int arm926ejs_read_phys_memory(struct target
*target
,
662 uint32_t address
, uint32_t size
,
663 uint32_t count
, uint8_t *buffer
)
665 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
667 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
668 address
, size
, count
, buffer
);
671 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
672 struct jtag_tap
*tap
)
674 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
676 arm7_9
->armv4_5_common
.mrc
= arm926ejs_mrc
;
677 arm7_9
->armv4_5_common
.mcr
= arm926ejs_mcr
;
679 /* initialize arm7/arm9 specific info (including armv4_5) */
680 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
682 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
684 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
685 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
687 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
688 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
689 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
690 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
691 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
692 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
693 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
694 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
695 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
696 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
698 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
700 /* The ARM926EJ-S implements the ARMv5TE architecture which
701 * has the BKPT instruction, so we don't have to use a watchpoint comparator
703 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
704 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
709 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
711 struct arm926ejs_common
*arm926ejs
= calloc(1,sizeof(struct arm926ejs_common
));
713 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
714 target
->tap
->ir_capture_mask
= 0x0f;
716 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
719 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
722 struct target
*target
= get_current_target(CMD_CTX
);
723 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
725 retval
= arm926ejs_verify_pointer(CMD_CTX
, arm926ejs
);
726 if (retval
!= ERROR_OK
)
729 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
732 static int arm926ejs_virt2phys(struct target
*target
, uint32_t virtual, uint32_t *physical
)
738 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
740 uint32_t ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
749 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
751 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
753 if (target
->state
!= TARGET_HALTED
)
755 LOG_ERROR("Target not halted");
756 return ERROR_TARGET_INVALID
;
758 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
762 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
764 .name
= "cache_info",
765 .handler
= &arm926ejs_handle_cache_info_command
,
766 .mode
= COMMAND_EXEC
,
767 .help
= "display information about target caches",
770 COMMAND_REGISTRATION_DONE
772 const struct command_registration arm926ejs_command_handlers
[] = {
774 .chain
= arm9tdmi_command_handlers
,
779 .help
= "arm926ejs command group",
780 .chain
= arm926ejs_exec_command_handlers
,
782 COMMAND_REGISTRATION_DONE
785 /** Holds methods for ARM926 targets. */
786 struct target_type arm926ejs_target
=
791 .arch_state
= arm926ejs_arch_state
,
793 .target_request_data
= arm7_9_target_request_data
,
796 .resume
= arm7_9_resume
,
799 .assert_reset
= arm7_9_assert_reset
,
800 .deassert_reset
= arm7_9_deassert_reset
,
801 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
803 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
805 .read_memory
= arm7_9_read_memory
,
806 .write_memory
= arm926ejs_write_memory
,
807 .bulk_write_memory
= arm7_9_bulk_write_memory
,
809 .checksum_memory
= arm_checksum_memory
,
810 .blank_check_memory
= arm_blank_check_memory
,
812 .run_algorithm
= armv4_5_run_algorithm
,
814 .add_breakpoint
= arm7_9_add_breakpoint
,
815 .remove_breakpoint
= arm7_9_remove_breakpoint
,
816 .add_watchpoint
= arm7_9_add_watchpoint
,
817 .remove_watchpoint
= arm7_9_remove_watchpoint
,
819 .commands
= arm926ejs_command_handlers
,
820 .target_create
= arm926ejs_target_create
,
821 .init_target
= arm9tdmi_init_target
,
822 .examine
= arm7_9_examine
,
823 .virt2phys
= arm926ejs_virt2phys
,
824 .mmu
= arm926ejs_mmu
,
826 .read_phys_memory
= arm926ejs_read_phys_memory
,
827 .write_phys_memory
= arm926ejs_write_phys_memory
,
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