1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
28 #include "arm926ejs.h"
29 #include <helper/time_support.h>
30 #include "target_type.h"
32 #include "arm_opcodes.h"
36 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
37 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
38 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
40 * 1 ... core debugging
42 * 3 ... external boundary scan (SoC-specific, unused here)
44 * 15 ... coprocessor 15
48 #define _DEBUG_INSTRUCTION_EXECUTION_
51 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
53 static int arm926ejs_cp15_read(struct target
*target
, uint32_t op1
, uint32_t op2
,
54 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
56 int retval
= ERROR_OK
;
57 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
58 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
59 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
60 struct scan_field fields
[4];
61 uint8_t address_buf
[2] = {0, 0};
65 buf_set_u32(address_buf
, 0, 14, address
);
67 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
68 if (retval
!= ERROR_OK
)
70 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
71 if (retval
!= ERROR_OK
)
74 fields
[0].num_bits
= 32;
75 fields
[0].out_value
= NULL
;
76 fields
[0].in_value
= (uint8_t *)value
;
78 fields
[1].num_bits
= 1;
79 fields
[1].out_value
= &access_t
;
80 fields
[1].in_value
= &access_t
;
82 fields
[2].num_bits
= 14;
83 fields
[2].out_value
= address_buf
;
84 fields
[2].in_value
= NULL
;
86 fields
[3].num_bits
= 1;
87 fields
[3].out_value
= &nr_w_buf
;
88 fields
[3].in_value
= NULL
;
90 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
92 long long then
= timeval_ms();
95 /* rescan with NOP, to wait for the access to complete */
98 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
100 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
102 retval
= jtag_execute_queue();
103 if (retval
!= ERROR_OK
)
106 if (buf_get_u32(&access_t
, 0, 1) == 1)
110 if ((timeval_ms()-then
) > 10) {
111 LOG_ERROR("cp15 read operation timed out");
116 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
117 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
120 retval
= arm_jtag_set_instr(jtag_info
, 0xc, NULL
, TAP_IDLE
);
121 if (retval
!= ERROR_OK
)
127 static int arm926ejs_mrc(struct target
*target
, int cpnum
, uint32_t op1
,
128 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
131 LOG_ERROR("Only cp15 is supported");
134 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
137 static int arm926ejs_cp15_write(struct target
*target
, uint32_t op1
, uint32_t op2
,
138 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
140 int retval
= ERROR_OK
;
141 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
142 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
143 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
144 struct scan_field fields
[4];
145 uint8_t value_buf
[4];
146 uint8_t address_buf
[2] = {0, 0};
147 uint8_t nr_w_buf
= 1;
148 uint8_t access_t
= 1;
150 buf_set_u32(address_buf
, 0, 14, address
);
151 buf_set_u32(value_buf
, 0, 32, value
);
153 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
154 if (retval
!= ERROR_OK
)
156 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
157 if (retval
!= ERROR_OK
)
160 fields
[0].num_bits
= 32;
161 fields
[0].out_value
= value_buf
;
162 fields
[0].in_value
= NULL
;
164 fields
[1].num_bits
= 1;
165 fields
[1].out_value
= &access_t
;
166 fields
[1].in_value
= &access_t
;
168 fields
[2].num_bits
= 14;
169 fields
[2].out_value
= address_buf
;
170 fields
[2].in_value
= NULL
;
172 fields
[3].num_bits
= 1;
173 fields
[3].out_value
= &nr_w_buf
;
174 fields
[3].in_value
= NULL
;
176 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
178 long long then
= timeval_ms();
181 /* rescan with NOP, to wait for the access to complete */
184 jtag_add_dr_scan(jtag_info
->tap
, 4, fields
, TAP_IDLE
);
185 retval
= jtag_execute_queue();
186 if (retval
!= ERROR_OK
)
189 if (buf_get_u32(&access_t
, 0, 1) == 1)
193 if ((timeval_ms()-then
) > 10) {
194 LOG_ERROR("cp15 write operation timed out");
199 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
200 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
203 retval
= arm_jtag_set_instr(jtag_info
, 0xf, NULL
, TAP_IDLE
);
204 if (retval
!= ERROR_OK
)
210 static int arm926ejs_mcr(struct target
*target
, int cpnum
, uint32_t op1
,
211 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
214 LOG_ERROR("Only cp15 is supported");
217 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
220 static int arm926ejs_examine_debug_reason(struct target
*target
)
222 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
223 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
227 embeddedice_read_reg(dbg_stat
);
228 retval
= jtag_execute_queue();
229 if (retval
!= ERROR_OK
)
232 /* Method-Of-Entry (MOE) field */
233 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
235 switch (debug_reason
) {
237 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
238 /* ... since last restart or debug reset ... */
239 target
->debug_reason
= DBG_REASON_DBGRQ
;
242 LOG_DEBUG("breakpoint from EICE unit 0");
243 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
246 LOG_DEBUG("breakpoint from EICE unit 1");
247 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
250 LOG_DEBUG("soft breakpoint (BKPT instruction)");
251 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
254 LOG_DEBUG("vector catch breakpoint");
255 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
258 LOG_DEBUG("external breakpoint");
259 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
262 LOG_DEBUG("watchpoint from EICE unit 0");
263 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
266 LOG_DEBUG("watchpoint from EICE unit 1");
267 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
270 LOG_DEBUG("external watchpoint");
271 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
274 LOG_DEBUG("internal debug request");
275 target
->debug_reason
= DBG_REASON_DBGRQ
;
278 LOG_DEBUG("external debug request");
279 target
->debug_reason
= DBG_REASON_DBGRQ
;
282 LOG_DEBUG("debug re-entry from system speed access");
283 /* This is normal when connecting to something that's
284 * already halted, or in some related code paths, but
285 * otherwise is surprising (and presumably wrong).
287 switch (target
->debug_reason
) {
288 case DBG_REASON_DBGRQ
:
291 LOG_ERROR("unexpected -- debug re-entry");
293 case DBG_REASON_UNDEFINED
:
294 target
->debug_reason
= DBG_REASON_DBGRQ
;
299 /* FIX!!!! here be dragons!!! We need to fail here so
300 * the target will interpreted as halted but we won't
301 * try to talk to it right now... a resume + halt seems
302 * to sync things up again. Please send an email to
303 * openocd development mailing list if you have hardware
304 * to donate to look into this problem....
306 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
307 target
->debug_reason
= DBG_REASON_DBGRQ
;
310 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
311 /* Oh agony! should we interpret this as a halt request or
312 * that the target stopped on it's own accord?
314 target
->debug_reason
= DBG_REASON_DBGRQ
;
315 /* if we fail here, we won't talk to the target and it will
316 * be reported to be in the halted state */
323 static int arm926ejs_get_ttb(struct target
*target
, uint32_t *result
)
325 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
329 retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
);
330 if (retval
!= ERROR_OK
)
338 static int arm926ejs_disable_mmu_caches(struct target
*target
, int mmu
,
339 int d_u_cache
, int i_cache
)
341 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
342 uint32_t cp15_control
;
345 /* read cp15 control register */
346 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
347 if (retval
!= ERROR_OK
)
349 retval
= jtag_execute_queue();
350 if (retval
!= ERROR_OK
)
355 retval
= arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
356 if (retval
!= ERROR_OK
)
359 cp15_control
&= ~0x1U
;
363 uint32_t debug_override
;
364 /* read-modify-write CP15 debug override register
365 * to enable "test and clean all" */
366 retval
= arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
367 if (retval
!= ERROR_OK
)
369 debug_override
|= 0x80000;
370 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
371 if (retval
!= ERROR_OK
)
374 /* clean and invalidate DCache */
375 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
376 if (retval
!= ERROR_OK
)
379 /* write CP15 debug override register
380 * to disable "test and clean all" */
381 debug_override
&= ~0x80000;
382 retval
= arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
383 if (retval
!= ERROR_OK
)
386 cp15_control
&= ~0x4U
;
390 /* invalidate ICache */
391 retval
= arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
392 if (retval
!= ERROR_OK
)
395 cp15_control
&= ~0x1000U
;
398 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
402 static int arm926ejs_enable_mmu_caches(struct target
*target
, int mmu
,
403 int d_u_cache
, int i_cache
)
405 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
406 uint32_t cp15_control
;
409 /* read cp15 control register */
410 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
411 if (retval
!= ERROR_OK
)
413 retval
= jtag_execute_queue();
414 if (retval
!= ERROR_OK
)
418 cp15_control
|= 0x1U
;
421 cp15_control
|= 0x4U
;
424 cp15_control
|= 0x1000U
;
426 retval
= arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
430 static int arm926ejs_post_debug_entry(struct target
*target
)
432 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
435 /* examine cp15 control reg */
436 retval
= arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
437 if (retval
!= ERROR_OK
)
439 retval
= jtag_execute_queue();
440 if (retval
!= ERROR_OK
)
442 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
444 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1) {
445 uint32_t cache_type_reg
;
446 /* identify caches */
447 retval
= arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
448 if (retval
!= ERROR_OK
)
450 retval
= jtag_execute_queue();
451 if (retval
!= ERROR_OK
)
453 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
456 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
457 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
458 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
460 /* save i/d fault status and address register */
461 retval
= arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
462 if (retval
!= ERROR_OK
)
464 retval
= arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
465 if (retval
!= ERROR_OK
)
467 retval
= arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
468 if (retval
!= ERROR_OK
)
471 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
472 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
474 uint32_t cache_dbg_ctrl
;
476 /* read-modify-write CP15 cache debug control register
477 * to disable I/D-cache linefills and force WT */
478 retval
= arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
479 if (retval
!= ERROR_OK
)
481 cache_dbg_ctrl
|= 0x7;
482 retval
= arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
486 static void arm926ejs_pre_restore_context(struct target
*target
)
488 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
490 /* restore i/d fault status and address register */
491 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
492 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
493 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
495 uint32_t cache_dbg_ctrl
;
497 /* read-modify-write CP15 cache debug control register
498 * to reenable I/D-cache linefills and disable WT */
499 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
500 cache_dbg_ctrl
&= ~0x7;
501 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
504 static const char arm926_not
[] = "target is not an ARM926";
506 static int arm926ejs_verify_pointer(struct command_context
*cmd_ctx
,
507 struct arm926ejs_common
*arm926
)
509 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
510 command_print(cmd_ctx
, arm926_not
);
511 return ERROR_TARGET_INVALID
;
516 /** Logs summary of ARM926 state for a halted target. */
517 int arm926ejs_arch_state(struct target
*target
)
519 static const char *state
[] = {
520 "disabled", "enabled"
523 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
525 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
526 LOG_ERROR("BUG: %s", arm926_not
);
527 return ERROR_TARGET_INVALID
;
530 arm_arch_state(target
);
531 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
532 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
533 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
534 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
539 int arm926ejs_soft_reset_halt(struct target
*target
)
541 int retval
= ERROR_OK
;
542 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
543 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
544 struct arm
*arm
= &arm7_9
->arm
;
545 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
547 retval
= target_halt(target
);
548 if (retval
!= ERROR_OK
)
551 long long then
= timeval_ms();
553 while (!(timeout
= ((timeval_ms()-then
) > 1000))) {
554 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0) {
555 embeddedice_read_reg(dbg_stat
);
556 retval
= jtag_execute_queue();
557 if (retval
!= ERROR_OK
)
561 if (debug_level
>= 1) {
562 /* do not eat all CPU, time out after 1 se*/
568 LOG_ERROR("Failed to halt CPU after 1 sec");
569 return ERROR_TARGET_TIMEOUT
;
572 target
->state
= TARGET_HALTED
;
574 /* SVC, ARM state, IRQ and FIQ disabled */
577 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
580 arm_set_cpsr(arm
, cpsr
);
581 arm
->cpsr
->dirty
= 1;
583 /* start fetching from 0x0 */
584 buf_set_u32(arm
->pc
->value
, 0, 32, 0x0);
588 retval
= arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
589 if (retval
!= ERROR_OK
)
591 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
592 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
593 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
595 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
598 /** Writes a buffer, in the specified word size, with current MMU settings. */
599 int arm926ejs_write_memory(struct target
*target
, uint32_t address
,
600 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
603 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
605 /* FIX!!!! this should be cleaned up and made much more general. The
606 * plan is to write up and test on arm926ejs specifically and
607 * then generalize and clean up afterwards.
610 * Also it should be moved to the callbacks that handle breakpoints
611 * specifically and not the generic memory write fn's. See XScale code.
613 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
== 2) || (size
== 4))) {
614 /* special case the handling of single word writes to bypass MMU
615 * to allow implementation of breakpoints in memory marked read only
617 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
618 /* flush and invalidate data cache
620 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
623 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
624 if (retval
!= ERROR_OK
)
629 retval
= target
->type
->virt2phys(target
, address
, &pa
);
630 if (retval
!= ERROR_OK
)
633 /* write directly to physical memory bypassing any read only MMU bits, etc. */
634 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
635 if (retval
!= ERROR_OK
)
638 retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
);
639 if (retval
!= ERROR_OK
)
643 /* If ICache is enabled, we have to invalidate affected ICache lines
644 * the DCache is forced to write-through, so we don't have to clean it here
646 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) {
648 /* invalidate ICache single entry with MVA */
649 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
651 /* invalidate ICache */
652 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
659 static int arm926ejs_write_phys_memory(struct target
*target
,
660 uint32_t address
, uint32_t size
,
661 uint32_t count
, const uint8_t *buffer
)
663 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
665 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
666 address
, size
, count
, buffer
);
669 static int arm926ejs_read_phys_memory(struct target
*target
,
670 uint32_t address
, uint32_t size
,
671 uint32_t count
, uint8_t *buffer
)
673 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
675 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
676 address
, size
, count
, buffer
);
679 int arm926ejs_init_arch_info(struct target
*target
, struct arm926ejs_common
*arm926ejs
,
680 struct jtag_tap
*tap
)
682 struct arm7_9_common
*arm7_9
= &arm926ejs
->arm7_9_common
;
684 arm7_9
->arm
.mrc
= arm926ejs_mrc
;
685 arm7_9
->arm
.mcr
= arm926ejs_mcr
;
687 /* initialize arm7/arm9 specific info (including armv4_5) */
688 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
690 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
692 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
693 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
695 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
696 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
697 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
698 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
699 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
700 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
701 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
702 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
703 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
704 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
706 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
708 /* The ARM926EJ-S implements the ARMv5TE architecture which
709 * has the BKPT instruction, so we don't have to use a watchpoint comparator
711 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
712 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
717 static int arm926ejs_target_create(struct target
*target
, Jim_Interp
*interp
)
719 struct arm926ejs_common
*arm926ejs
= calloc(1, sizeof(struct arm926ejs_common
));
721 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
722 target
->tap
->ir_capture_mask
= 0x0f;
724 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
727 COMMAND_HANDLER(arm926ejs_handle_cache_info_command
)
730 struct target
*target
= get_current_target(CMD_CTX
);
731 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
733 retval
= arm926ejs_verify_pointer(CMD_CTX
, arm926ejs
);
734 if (retval
!= ERROR_OK
)
737 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
740 static int arm926ejs_virt2phys(struct target
*target
, uint32_t virtual, uint32_t *physical
)
743 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
746 int retval
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
,
748 if (retval
!= ERROR_OK
)
754 static int arm926ejs_mmu(struct target
*target
, int *enabled
)
756 struct arm926ejs_common
*arm926ejs
= target_to_arm926(target
);
758 if (target
->state
!= TARGET_HALTED
) {
759 LOG_ERROR("Target not halted");
760 return ERROR_TARGET_INVALID
;
762 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
766 static const struct command_registration arm926ejs_exec_command_handlers
[] = {
768 .name
= "cache_info",
769 .handler
= arm926ejs_handle_cache_info_command
,
770 .mode
= COMMAND_EXEC
,
772 .help
= "display information about target caches",
775 COMMAND_REGISTRATION_DONE
777 const struct command_registration arm926ejs_command_handlers
[] = {
779 .chain
= arm9tdmi_command_handlers
,
784 .help
= "arm926ejs command group",
786 .chain
= arm926ejs_exec_command_handlers
,
788 COMMAND_REGISTRATION_DONE
791 /** Holds methods for ARM926 targets. */
792 struct target_type arm926ejs_target
= {
796 .arch_state
= arm926ejs_arch_state
,
798 .target_request_data
= arm7_9_target_request_data
,
801 .resume
= arm7_9_resume
,
804 .assert_reset
= arm7_9_assert_reset
,
805 .deassert_reset
= arm7_9_deassert_reset
,
806 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
808 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
810 .read_memory
= arm7_9_read_memory
,
811 .write_memory
= arm926ejs_write_memory
,
812 .bulk_write_memory
= arm7_9_bulk_write_memory
,
814 .checksum_memory
= arm_checksum_memory
,
815 .blank_check_memory
= arm_blank_check_memory
,
817 .run_algorithm
= armv4_5_run_algorithm
,
819 .add_breakpoint
= arm7_9_add_breakpoint
,
820 .remove_breakpoint
= arm7_9_remove_breakpoint
,
821 .add_watchpoint
= arm7_9_add_watchpoint
,
822 .remove_watchpoint
= arm7_9_remove_watchpoint
,
824 .commands
= arm926ejs_command_handlers
,
825 .target_create
= arm926ejs_target_create
,
826 .init_target
= arm9tdmi_init_target
,
827 .examine
= arm7_9_examine
,
828 .check_reset
= arm7_9_check_reset
,
829 .virt2phys
= arm926ejs_virt2phys
,
830 .mmu
= arm926ejs_mmu
,
832 .read_phys_memory
= arm926ejs_read_phys_memory
,
833 .write_phys_memory
= arm926ejs_write_phys_memory
,
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