1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 by Drasko DRASKOVIC *
9 * drasko.draskovic@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include "target_type.h"
31 #include "arm_opcodes.h"
33 #include "breakpoints.h"
36 #define _DEBUG_INSTRUCTION_EXECUTION_
39 #define NB_CACHE_WAYS 4
42 #define CP15_CTL_DCACHE (1<<2)
43 #define CP15_CTL_ICACHE (1<<12)
46 * flag to give info about cache manipulation during debug :
47 * "0" - cache lines are invalidated "on the fly", for affected addresses.
48 * This is prefered from performance point of view.
49 * "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
50 * It is kept off during debugging.
52 static uint8_t arm946e_preserve_cache
;
54 int arm946e_post_debug_entry(struct target
*target
);
55 void arm946e_pre_restore_context(struct target
*target
);
56 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
);
58 int arm946e_init_arch_info(struct target
*target
,
59 struct arm946e_common
*arm946e
,
62 struct arm7_9_common
*arm7_9
= &arm946e
->arm7_9_common
;
64 /* initialize arm7/arm9 specific info (including armv4_5) */
65 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
67 arm946e
->common_magic
= ARM946E_COMMON_MAGIC
;
70 * The ARM946E-S implements the ARMv5TE architecture which
71 * has the BKPT instruction, so we don't have to use a watchpoint comparator
73 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
74 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
77 arm7_9
->post_debug_entry
= arm946e_post_debug_entry
;
78 arm7_9
->pre_restore_context
= arm946e_pre_restore_context
;
81 * disabling linefills leads to lockups, so keep them enabled for now
82 * this doesn't affect correctness, but might affect timing issues, if
83 * important data is evicted from the cache during the debug session
85 arm946e_preserve_cache
= 0;
87 /* override hw single-step capability from ARM9TDMI */
88 /* arm7_9->has_single_step = 1; */
93 static int arm946e_target_create(struct target
*target
, Jim_Interp
*interp
)
95 struct arm946e_common
*arm946e
= calloc(1, sizeof(struct arm946e_common
));
97 arm946e_init_arch_info(target
, arm946e
, target
->tap
);
102 static int arm946e_verify_pointer(struct command_context
*cmd_ctx
,
103 struct arm946e_common
*arm946e
)
105 if (arm946e
->common_magic
!= ARM946E_COMMON_MAGIC
) {
106 command_print(cmd_ctx
, "target is not an ARM946");
107 return ERROR_TARGET_INVALID
;
113 * Update cp15_control_reg, saved on debug_entry.
115 static void arm946e_update_cp15_caches(struct target
*target
, uint32_t value
)
117 struct arm946e_common
*arm946e
= target_to_arm946(target
);
118 arm946e
->cp15_control_reg
= (arm946e
->cp15_control_reg
& ~(CP15_CTL_DCACHE
|CP15_CTL_ICACHE
))
119 | (value
& (CP15_CTL_DCACHE
|CP15_CTL_ICACHE
));
123 * REVISIT: The "read_cp15" and "write_cp15" commands could hook up
124 * to eventual mrc() and mcr() routines ... the reg_addr values being
125 * constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
126 * See section 7.3 of the ARM946E-S TRM.
128 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
)
130 int retval
= ERROR_OK
;
131 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
132 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
133 struct scan_field fields
[3];
134 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
135 uint8_t nr_w_buf
= 0;
137 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
138 if (retval
!= ERROR_OK
)
140 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
141 if (retval
!= ERROR_OK
)
144 fields
[0].num_bits
= 32;
145 /* REVISIT: table 7-2 shows that bits 31-31 need to be
146 * specified for accessing BIST registers ...
148 fields
[0].out_value
= NULL
;
149 fields
[0].in_value
= NULL
;
151 fields
[1].num_bits
= 6;
152 fields
[1].out_value
= ®_addr_buf
;
153 fields
[1].in_value
= NULL
;
155 fields
[2].num_bits
= 1;
156 fields
[2].out_value
= &nr_w_buf
;
157 fields
[2].in_value
= NULL
;
159 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
161 fields
[0].in_value
= (uint8_t *)value
;
162 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
164 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
166 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
167 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
170 retval
= jtag_execute_queue();
171 if (retval
!= ERROR_OK
)
177 int arm946e_write_cp15(struct target
*target
, int reg_addr
, uint32_t value
)
179 int retval
= ERROR_OK
;
180 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
181 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
182 struct scan_field fields
[3];
183 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
184 uint8_t nr_w_buf
= 1;
185 uint8_t value_buf
[4];
187 buf_set_u32(value_buf
, 0, 32, value
);
189 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
190 if (retval
!= ERROR_OK
)
192 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
193 if (retval
!= ERROR_OK
)
196 fields
[0].num_bits
= 32;
197 fields
[0].out_value
= value_buf
;
198 fields
[0].in_value
= NULL
;
200 fields
[1].num_bits
= 6;
201 fields
[1].out_value
= ®_addr_buf
;
202 fields
[1].in_value
= NULL
;
204 fields
[2].num_bits
= 1;
205 fields
[2].out_value
= &nr_w_buf
;
206 fields
[2].in_value
= NULL
;
208 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
210 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
211 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
214 retval
= jtag_execute_queue();
215 if (retval
!= ERROR_OK
)
221 #define GET_ICACHE_SIZE 6
222 #define GET_DCACHE_SIZE 18
225 * \param target struct target pointer
226 * \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
227 * \returns cache size, given in bytes
229 static uint32_t arm946e_cp15_get_csize(struct target
*target
, int idsel
)
231 struct arm946e_common
*arm946e
= target_to_arm946(target
);
232 uint32_t csize
= arm946e
->cp15_cache_info
;
234 if (arm946e_read_cp15(target
, 0x01, &csize
) == ERROR_OK
)
235 arm946e
->cp15_cache_info
= csize
;
237 if (csize
& (1<<(idsel
-4))) /* cache absent */
239 csize
= (csize
>> idsel
) & 0x0F;
240 return csize
? 1 << (12 + (csize
-3)) : 0;
243 uint32_t arm946e_invalidate_whole_dcache(struct target
*target
)
245 uint32_t csize
= arm946e_cp15_get_csize(target
, GET_DCACHE_SIZE
);
247 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
249 /* One line (index) is 32 bytes (8 words) long, 4-way assoc
250 * ARM DDI 0201D, Section 3.3.5
252 int nb_idx
= (csize
/ (4*8*NB_CACHE_WAYS
)); /* gives nb of lines (indexes) in the cache */
254 /* Loop for all segmentde (i.e. ways) */
256 for (seg
= 0; seg
< NB_CACHE_WAYS
; seg
++) {
257 /* Loop for all indexes */
259 for (idx
= 0; idx
< nb_idx
; idx
++) {
260 /* Form and write cp15 index (segment + line idx) */
261 uint32_t cp15_idx
= seg
<< 30 | idx
<< 5;
262 int retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
263 if (retval
!= ERROR_OK
) {
264 LOG_DEBUG("ERROR writing index");
270 arm946e_read_cp15(target
, 0x16, (uint32_t *) &dtag
);
272 /* Check cache line VALID bit */
273 if (!(dtag
>> 4 & 0x1))
276 /* Clean data cache line */
277 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
278 if (retval
!= ERROR_OK
) {
279 LOG_DEBUG("ERROR cleaning cache line");
283 /* Flush data cache line */
284 retval
= arm946e_write_cp15(target
, 0x1a, 0x1);
285 if (retval
!= ERROR_OK
) {
286 LOG_DEBUG("ERROR flushing cache line");
295 uint32_t arm946e_invalidate_whole_icache(struct target
*target
)
297 /* Check cache presence before flushing - avoid undefined behavior */
298 uint32_t csize
= arm946e_cp15_get_csize(target
, GET_ICACHE_SIZE
);
300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
302 LOG_DEBUG("FLUSHING I$");
304 * Invalidate (flush) I$
305 * mcr 15, 0, r0, cr7, cr5, {0}
307 int retval
= arm946e_write_cp15(target
, 0x0f, 0x1);
308 if (retval
!= ERROR_OK
) {
309 LOG_DEBUG("ERROR flushing I$");
316 int arm946e_post_debug_entry(struct target
*target
)
318 uint32_t ctr_reg
= 0x0;
319 uint32_t retval
= ERROR_OK
;
320 struct arm946e_common
*arm946e
= target_to_arm946(target
);
322 /* See if CACHES are enabled, and save that info
323 * in the context bits, so that arm946e_pre_restore_context() can use them */
324 arm946e_read_cp15(target
, CP15_CTL
, (uint32_t *) &ctr_reg
);
326 /* Save control reg in the context */
327 arm946e
->cp15_control_reg
= ctr_reg
;
329 if (arm946e_preserve_cache
) {
330 if (ctr_reg
& CP15_CTL_DCACHE
) {
331 /* Clean and flush D$ */
332 arm946e_invalidate_whole_dcache(target
);
335 ctr_reg
&= ~CP15_CTL_DCACHE
;
338 if (ctr_reg
& CP15_CTL_ICACHE
) {
340 arm946e_invalidate_whole_icache(target
);
343 ctr_reg
&= ~CP15_CTL_ICACHE
;
346 /* Write the new configuration */
347 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
348 if (retval
!= ERROR_OK
) {
349 LOG_DEBUG("ERROR disabling cache");
352 } /* if preserve_cache */
357 void arm946e_pre_restore_context(struct target
*target
)
359 uint32_t ctr_reg
= 0x0;
362 if (arm946e_preserve_cache
) {
363 struct arm946e_common
*arm946e
= target_to_arm946(target
);
364 /* Get the contents of the CTR reg */
365 arm946e_read_cp15(target
, CP15_CTL
, (uint32_t *) &ctr_reg
);
368 * Read-modify-write CP15 control
369 * to reenable I/D-cache operation
370 * NOTE: It is not possible to disable cache by CP15.
371 * if arm946e_preserve_cache debugging flag enabled.
373 ctr_reg
|= arm946e
->cp15_control_reg
& (CP15_CTL_DCACHE
|CP15_CTL_ICACHE
);
375 /* Write the new configuration */
376 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
377 if (retval
!= ERROR_OK
)
378 LOG_DEBUG("ERROR enabling cache");
379 } /* if preserve_cache */
382 uint32_t arm946e_invalidate_dcache(struct target
*target
, uint32_t address
,
383 uint32_t size
, uint32_t count
)
385 uint32_t cur_addr
= 0x0;
386 uint32_t cp15_idx
, set
, way
, dtag
;
390 for (i
= 0; i
< count
*size
; i
++) {
391 cur_addr
= address
+ i
;
394 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
396 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
398 * Find if the affected address is kept in the cache.
399 * Because JTAG Scan Chain 15 offers limited approach,
400 * we have to loop through all cache ways (segments) and
401 * read cache tags, then compare them with with address.
404 /* Form and write cp15 index (segment + line idx) */
405 cp15_idx
= way
<< 30 | set
<< 5;
406 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
407 if (retval
!= ERROR_OK
) {
408 LOG_DEBUG("ERROR writing index");
413 arm946e_read_cp15(target
, 0x16, (uint32_t *) &dtag
);
415 /* Check cache line VALID bit */
416 if (!(dtag
>> 4 & 0x1))
419 /* If line is valid and corresponds to affected address - invalidate it */
420 if (dtag
>> 5 == cur_addr
>> 5) {
421 /* Clean data cache line */
422 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
423 if (retval
!= ERROR_OK
) {
424 LOG_DEBUG("ERROR cleaning cache line");
428 /* Flush data cache line */
429 retval
= arm946e_write_cp15(target
, 0x1c, 0x1);
430 if (retval
!= ERROR_OK
) {
431 LOG_DEBUG("ERROR flushing cache line");
437 } /* loop through all 4 ways */
438 } /* loop through all addresses */
443 uint32_t arm946e_invalidate_icache(struct target
*target
, uint32_t address
,
444 uint32_t size
, uint32_t count
)
446 uint32_t cur_addr
= 0x0;
447 uint32_t cp15_idx
, set
, way
, itag
;
451 for (i
= 0; i
< count
*size
; i
++) {
452 cur_addr
= address
+ i
;
454 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
456 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
457 /* Form and write cp15 index (segment + line idx) */
458 cp15_idx
= way
<< 30 | set
<< 5;
459 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
460 if (retval
!= ERROR_OK
) {
461 LOG_DEBUG("ERROR writing index");
466 arm946e_read_cp15(target
, 0x17, (uint32_t *) &itag
);
468 /* Check cache line VALID bit */
469 if (!(itag
>> 4 & 0x1))
472 /* If line is valid and corresponds to affected address - invalidate it */
473 if (itag
>> 5 == cur_addr
>> 5) {
475 retval
= arm946e_write_cp15(target
, 0x1d, 0x0);
476 if (retval
!= ERROR_OK
) {
477 LOG_DEBUG("ERROR flushing cache line");
489 /** Writes a buffer, in the specified word size, with current MMU settings. */
490 int arm946e_write_memory(struct target
*target
, target_addr_t address
,
491 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
497 struct arm946e_common
*arm946e
= target_to_arm946(target
);
498 /* Invalidate D$ if it is ON */
499 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_DCACHE
))
500 arm946e_invalidate_dcache(target
, address
, size
, count
);
505 retval
= arm7_9_write_memory_opt(target
, address
, size
, count
, buffer
);
506 if (retval
!= ERROR_OK
)
510 * Invalidate I$ if it is ON.
512 * D$ has been cleaned and flushed before mem write thus forcing it to behave like write-through,
513 * because arm7_9_write_memory() has seen non-valid bit in D$
514 * and wrote data into physical RAM (without touching or allocating the cache line).
515 * From ARM946ES Technical Reference Manual we can see that it uses "allocate on read-miss"
516 * policy for both I$ and D$ (Chapter 3.2 and 3.3)
519 * "ARM system developer's guide: designing and optimizing system software" by
520 * Andrew N. Sloss, Dominic Symes and Chris Wright,
521 * Chapter 12.3.3 Allocating Policy on a Cache Miss :
522 * A read allocate on cache miss policy allocates a cache line only during a read from main memory.
523 * If the victim cache line contains valid data, then it is written to main memory before the cache line
524 * is filled with new data.
525 * Under this strategy, a write of new data to memory does not update the contents of the cache memory
526 * unless a cache line was allocated on a previous read from main memory.
527 * If the cache line contains valid data, then the write updates the cache and may update the main memory if
528 * the cache write policy is write-through.
529 * If the data is not in the cache, the controller writes to main memory only.
531 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_ICACHE
))
532 arm946e_invalidate_icache(target
, address
, size
, count
);
538 int arm946e_read_memory(struct target
*target
, target_addr_t address
,
539 uint32_t size
, uint32_t count
, uint8_t *buffer
)
545 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
546 if (retval
!= ERROR_OK
)
552 static int jim_arm946e_cp15(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
554 /* one or two arguments, access a single register (write if second argument is given) */
555 if (argc
< 2 || argc
> 3) {
556 Jim_WrongNumArgs(interp
, 1, argv
, "addr [value]");
560 struct command_context
*cmd_ctx
= current_command_context(interp
);
561 assert(cmd_ctx
!= NULL
);
563 struct target
*target
= get_current_target(cmd_ctx
);
564 if (target
== NULL
) {
565 LOG_ERROR("arm946e: no current target");
569 struct arm946e_common
*arm946e
= target_to_arm946(target
);
570 int retval
= arm946e_verify_pointer(cmd_ctx
, arm946e
);
571 if (retval
!= ERROR_OK
)
574 if (target
->state
!= TARGET_HALTED
) {
575 command_print(cmd_ctx
, "target %s must be stopped for \"cp15\" command", target_name(target
));
581 retval
= Jim_GetLong(interp
, argv
[1], &l
);
583 if (JIM_OK
!= retval
)
588 retval
= arm946e_read_cp15(target
, address
, &value
);
589 if (retval
!= ERROR_OK
) {
590 command_print(cmd_ctx
, "%s cp15 reg %" PRIi32
" access failed", target_name(target
), address
);
593 retval
= jtag_execute_queue();
594 if (retval
!= ERROR_OK
)
597 sprintf(buf
, "0x%08" PRIx32
, value
);
598 /* Return value in hex format */
599 Jim_SetResultString(interp
, buf
, -1);
600 } else if (argc
== 3) {
602 retval
= Jim_GetLong(interp
, argv
[2], &l
);
604 if (JIM_OK
!= retval
)
606 retval
= arm946e_write_cp15(target
, address
, value
);
607 if (retval
!= ERROR_OK
) {
608 command_print(cmd_ctx
, "%s cp15 reg %" PRIi32
" access failed", target_name(target
), address
);
611 if (address
== CP15_CTL
)
612 arm946e_update_cp15_caches(target
, value
);
618 COMMAND_HANDLER(arm946e_handle_idcache
)
621 return ERROR_COMMAND_SYNTAX_ERROR
;
624 struct target
*target
= get_current_target(CMD_CTX
);
625 struct arm946e_common
*arm946e
= target_to_arm946(target
);
627 retval
= arm946e_verify_pointer(CMD_CTX
, arm946e
);
628 if (retval
!= ERROR_OK
)
631 if (target
->state
!= TARGET_HALTED
) {
632 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
633 return ERROR_TARGET_NOT_HALTED
;
636 bool icache
= (strcmp(CMD_NAME
, "icache") == 0);
637 uint32_t csize
= arm946e_cp15_get_csize(target
, icache
? GET_ICACHE_SIZE
: GET_DCACHE_SIZE
) / 1024;
639 bool bena
= ((arm946e
->cp15_control_reg
& (icache
? CP15_CTL_ICACHE
: CP15_CTL_DCACHE
)) != 0)
640 && (arm946e
->cp15_control_reg
& 0x1);
642 command_print(CMD_CTX
, "%s-cache absent", icache
? "I" : "D");
644 command_print(CMD_CTX
, "%s-cache size: %" PRIu32
"K, %s",
645 icache
? "I" : "D", csize
, bena
? "enabled" : "disabled");
651 retval
= command_parse_bool_arg(CMD_ARGV
[0], &enable
);
652 if (retval
== ERROR_COMMAND_SYNTAX_ERROR
) {
653 if (strcmp(CMD_ARGV
[0], "flush") == 0) {
660 /* Do not invalidate or change state, if cache is absent */
662 command_print(CMD_CTX
, "%s-cache absent, '%s' operation undefined", icache
? "I" : "D", CMD_ARGV
[0]);
663 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
666 /* NOTE: flushing entire cache will not preserve lock-down cache regions */
668 if ((arm946e
->cp15_control_reg
& CP15_CTL_ICACHE
) && !enable
)
669 retval
= arm946e_invalidate_whole_icache(target
);
671 if ((arm946e
->cp15_control_reg
& CP15_CTL_DCACHE
) && !enable
)
672 retval
= arm946e_invalidate_whole_dcache(target
);
675 if (retval
!= ERROR_OK
|| flush
)
679 retval
= arm946e_read_cp15(target
, CP15_CTL
, &value
);
680 if (retval
!= ERROR_OK
)
683 uint32_t vnew
= value
;
684 uint32_t cmask
= icache
? CP15_CTL_ICACHE
: CP15_CTL_DCACHE
;
686 if ((value
& 0x1) == 0)
687 LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
695 retval
= arm946e_write_cp15(target
, CP15_CTL
, vnew
);
696 if (retval
!= ERROR_OK
)
699 arm946e_update_cp15_caches(target
, vnew
);
703 static const struct command_registration arm946e_exec_command_handlers
[] = {
706 .jim_handler
= jim_arm946e_cp15
,
707 .mode
= COMMAND_EXEC
,
708 .usage
= "regnum [value]",
709 .help
= "read/modify cp15 register",
713 .handler
= arm946e_handle_idcache
,
714 .mode
= COMMAND_EXEC
,
715 .usage
= "['enable'|'disable'|'flush']",
716 .help
= "I-cache info and operations",
720 .handler
= arm946e_handle_idcache
,
721 .mode
= COMMAND_EXEC
,
722 .usage
= "['enable'|'disable'|'flush']",
723 .help
= "D-cache info and operations",
725 COMMAND_REGISTRATION_DONE
728 const struct command_registration arm946e_command_handlers
[] = {
730 .chain
= arm9tdmi_command_handlers
,
735 .help
= "arm946e command group",
737 .chain
= arm946e_exec_command_handlers
,
739 COMMAND_REGISTRATION_DONE
742 /** Holds methods for ARM946 targets. */
743 struct target_type arm946e_target
= {
747 .arch_state
= arm_arch_state
,
749 .target_request_data
= arm7_9_target_request_data
,
752 .resume
= arm7_9_resume
,
755 .assert_reset
= arm7_9_assert_reset
,
756 .deassert_reset
= arm7_9_deassert_reset
,
757 .soft_reset_halt
= arm7_9_soft_reset_halt
,
759 .get_gdb_arch
= arm_get_gdb_arch
,
760 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
762 /* .read_memory = arm7_9_read_memory, */
763 /* .write_memory = arm7_9_write_memory, */
764 .read_memory
= arm946e_read_memory
,
765 .write_memory
= arm946e_write_memory
,
767 .checksum_memory
= arm_checksum_memory
,
768 .blank_check_memory
= arm_blank_check_memory
,
770 .run_algorithm
= armv4_5_run_algorithm
,
772 .add_breakpoint
= arm7_9_add_breakpoint
,
773 .remove_breakpoint
= arm7_9_remove_breakpoint
,
774 /* .add_breakpoint = arm946e_add_breakpoint, */
775 /* .remove_breakpoint = arm946e_remove_breakpoint, */
777 .add_watchpoint
= arm7_9_add_watchpoint
,
778 .remove_watchpoint
= arm7_9_remove_watchpoint
,
780 .commands
= arm946e_command_handlers
,
781 .target_create
= arm946e_target_create
,
782 .init_target
= arm9tdmi_init_target
,
783 .examine
= arm7_9_examine
,
784 .check_reset
= arm7_9_check_reset
,
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