1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 #include "arm7_9_common.h"
33 #include "embeddedice.h"
44 #define _DEBUG_INSTRUCTION_EXECUTION_
48 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
);
49 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 /* forward declarations */
52 int arm9tdmi_target_create( struct target_s
*target
, Jim_Interp
*interp
);
54 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
55 int arm9tdmi_quit(void);
57 target_type_t arm9tdmi_target
=
62 .arch_state
= armv4_5_arch_state
,
64 .target_request_data
= arm7_9_target_request_data
,
67 .resume
= arm7_9_resume
,
70 .assert_reset
= arm7_9_assert_reset
,
71 .deassert_reset
= arm7_9_deassert_reset
,
72 .soft_reset_halt
= arm7_9_soft_reset_halt
,
74 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
76 .read_memory
= arm7_9_read_memory
,
77 .write_memory
= arm7_9_write_memory
,
78 .bulk_write_memory
= arm7_9_bulk_write_memory
,
79 .checksum_memory
= arm7_9_checksum_memory
,
80 .blank_check_memory
= arm7_9_blank_check_memory
,
82 .run_algorithm
= armv4_5_run_algorithm
,
84 .add_breakpoint
= arm7_9_add_breakpoint
,
85 .remove_breakpoint
= arm7_9_remove_breakpoint
,
86 .add_watchpoint
= arm7_9_add_watchpoint
,
87 .remove_watchpoint
= arm7_9_remove_watchpoint
,
89 .register_commands
= arm9tdmi_register_commands
,
90 .target_create
= arm9tdmi_target_create
,
91 .init_target
= arm9tdmi_init_target
,
92 .examine
= arm9tdmi_examine
,
96 arm9tdmi_vector_t arm9tdmi_vectors
[] =
98 {"reset", ARM9TDMI_RESET_VECTOR
},
99 {"undef", ARM9TDMI_UNDEF_VECTOR
},
100 {"swi", ARM9TDMI_SWI_VECTOR
},
101 {"pabt", ARM9TDMI_PABT_VECTOR
},
102 {"dabt", ARM9TDMI_DABT_VECTOR
},
103 {"reserved", ARM9TDMI_RESERVED_VECTOR
},
104 {"irq", ARM9TDMI_IRQ_VECTOR
},
105 {"fiq", ARM9TDMI_FIQ_VECTOR
},
109 int arm9tdmi_examine_debug_reason(target_t
*target
)
111 int retval
= ERROR_OK
;
112 /* get pointers to arch-specific information */
113 armv4_5_common_t
*armv4_5
= target
->arch_info
;
114 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
116 /* only check the debug reason if we don't know it already */
117 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
118 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
120 scan_field_t fields
[3];
122 u8 instructionbus
[4];
125 jtag_add_end_state(TAP_PD
);
127 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
128 fields
[0].num_bits
= 32;
129 fields
[0].out_value
= NULL
;
130 fields
[0].out_mask
= NULL
;
131 fields
[0].in_value
= databus
;
132 fields
[0].in_check_value
= NULL
;
133 fields
[0].in_check_mask
= NULL
;
134 fields
[0].in_handler
= NULL
;
135 fields
[0].in_handler_priv
= NULL
;
137 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
138 fields
[1].num_bits
= 3;
139 fields
[1].out_value
= NULL
;
140 fields
[1].out_mask
= NULL
;
141 fields
[1].in_value
= &debug_reason
;
142 fields
[1].in_check_value
= NULL
;
143 fields
[1].in_check_mask
= NULL
;
144 fields
[1].in_handler
= NULL
;
145 fields
[1].in_handler_priv
= NULL
;
147 fields
[2].device
= arm7_9
->jtag_info
.chain_pos
;
148 fields
[2].num_bits
= 32;
149 fields
[2].out_value
= NULL
;
150 fields
[2].out_mask
= NULL
;
151 fields
[2].in_value
= instructionbus
;
152 fields
[2].in_check_value
= NULL
;
153 fields
[2].in_check_mask
= NULL
;
154 fields
[2].in_handler
= NULL
;
155 fields
[2].in_handler_priv
= NULL
;
157 if((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1)) != ERROR_OK
)
161 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
163 jtag_add_dr_scan(3, fields
, TAP_PD
);
164 if((retval
= jtag_execute_queue()) != ERROR_OK
)
169 fields
[0].in_value
= NULL
;
170 fields
[0].out_value
= databus
;
171 fields
[1].in_value
= NULL
;
172 fields
[1].out_value
= &debug_reason
;
173 fields
[2].in_value
= NULL
;
174 fields
[2].out_value
= instructionbus
;
176 jtag_add_dr_scan(3, fields
, TAP_PD
);
178 if (debug_reason
& 0x4)
179 if (debug_reason
& 0x2)
180 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
182 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
184 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
190 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
191 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 instr
, u32 out
, u32
*in
, int sysspeed
)
193 int retval
= ERROR_OK
;
194 scan_field_t fields
[3];
197 u8 sysspeed_buf
= 0x0;
200 buf_set_u32(out_buf
, 0, 32, out
);
202 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
205 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
207 jtag_add_end_state(TAP_PD
);
208 if((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
213 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
215 fields
[0].device
= jtag_info
->chain_pos
;
216 fields
[0].num_bits
= 32;
217 fields
[0].out_value
= out_buf
;
218 fields
[0].out_mask
= NULL
;
219 fields
[0].in_value
= NULL
;
222 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
223 fields
[0].in_handler_priv
= in
;
227 fields
[0].in_handler
= NULL
;
228 fields
[0].in_handler_priv
= NULL
;
230 fields
[0].in_check_value
= NULL
;
231 fields
[0].in_check_mask
= NULL
;
233 fields
[1].device
= jtag_info
->chain_pos
;
234 fields
[1].num_bits
= 3;
235 fields
[1].out_value
= &sysspeed_buf
;
236 fields
[1].out_mask
= NULL
;
237 fields
[1].in_value
= NULL
;
238 fields
[1].in_check_value
= NULL
;
239 fields
[1].in_check_mask
= NULL
;
240 fields
[1].in_handler
= NULL
;
241 fields
[1].in_handler_priv
= NULL
;
243 fields
[2].device
= jtag_info
->chain_pos
;
244 fields
[2].num_bits
= 32;
245 fields
[2].out_value
= instr_buf
;
246 fields
[2].out_mask
= NULL
;
247 fields
[2].in_value
= NULL
;
248 fields
[2].in_check_value
= NULL
;
249 fields
[2].in_check_mask
= NULL
;
250 fields
[2].in_handler
= NULL
;
251 fields
[2].in_handler_priv
= NULL
;
253 jtag_add_dr_scan(3, fields
, -1);
255 jtag_add_runtest(0, -1);
257 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
259 if((retval
= jtag_execute_queue()) != ERROR_OK
)
266 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
269 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
276 /* just read data (instruction and data-out = don't care) */
277 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
279 int retval
= ERROR_OK
;;
280 scan_field_t fields
[3];
282 jtag_add_end_state(TAP_PD
);
283 if((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
288 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
290 fields
[0].device
= jtag_info
->chain_pos
;
291 fields
[0].num_bits
= 32;
292 fields
[0].out_value
= NULL
;
293 fields
[0].out_mask
= NULL
;
294 fields
[0].in_value
= NULL
;
295 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
296 fields
[0].in_handler_priv
= in
;
297 fields
[0].in_check_value
= NULL
;
298 fields
[0].in_check_mask
= NULL
;
300 fields
[1].device
= jtag_info
->chain_pos
;
301 fields
[1].num_bits
= 3;
302 fields
[1].out_value
= NULL
;
303 fields
[1].out_mask
= NULL
;
304 fields
[1].in_value
= NULL
;
305 fields
[1].in_handler
= NULL
;
306 fields
[1].in_handler_priv
= NULL
;
307 fields
[1].in_check_value
= NULL
;
308 fields
[1].in_check_mask
= NULL
;
310 fields
[2].device
= jtag_info
->chain_pos
;
311 fields
[2].num_bits
= 32;
312 fields
[2].out_value
= NULL
;
313 fields
[2].out_mask
= NULL
;
314 fields
[2].in_value
= NULL
;
315 fields
[2].in_check_value
= NULL
;
316 fields
[2].in_check_mask
= NULL
;
317 fields
[2].in_handler
= NULL
;
318 fields
[2].in_handler_priv
= NULL
;
320 jtag_add_dr_scan(3, fields
, -1);
322 jtag_add_runtest(0, -1);
324 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
326 if((retval
= jtag_execute_queue()) != ERROR_OK
)
333 LOG_DEBUG("in: 0x%8.8x", *in
);
337 LOG_ERROR("BUG: called with in == NULL");
345 /* clock the target, and read the databus
346 * the *in pointer points to a buffer where elements of 'size' bytes
347 * are stored in big (be==1) or little (be==0) endianness
349 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
351 int retval
= ERROR_OK
;
352 scan_field_t fields
[3];
354 jtag_add_end_state(TAP_PD
);
355 if((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
360 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
362 fields
[0].device
= jtag_info
->chain_pos
;
363 fields
[0].num_bits
= 32;
364 fields
[0].out_value
= NULL
;
365 fields
[0].out_mask
= NULL
;
366 fields
[0].in_value
= NULL
;
370 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be32
: arm_jtag_buf_to_le32
;
373 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be16
: arm_jtag_buf_to_le16
;
376 fields
[0].in_handler
= arm_jtag_buf_to_8
;
379 fields
[0].in_handler_priv
= in
;
380 fields
[0].in_check_value
= NULL
;
381 fields
[0].in_check_mask
= NULL
;
383 fields
[1].device
= jtag_info
->chain_pos
;
384 fields
[1].num_bits
= 3;
385 fields
[1].out_value
= NULL
;
386 fields
[1].out_mask
= NULL
;
387 fields
[1].in_value
= NULL
;
388 fields
[1].in_handler
= NULL
;
389 fields
[1].in_handler_priv
= NULL
;
390 fields
[1].in_check_value
= NULL
;
391 fields
[1].in_check_mask
= NULL
;
393 fields
[2].device
= jtag_info
->chain_pos
;
394 fields
[2].num_bits
= 32;
395 fields
[2].out_value
= NULL
;
396 fields
[2].out_mask
= NULL
;
397 fields
[2].in_value
= NULL
;
398 fields
[2].in_check_value
= NULL
;
399 fields
[2].in_check_mask
= NULL
;
400 fields
[2].in_handler
= NULL
;
401 fields
[2].in_handler_priv
= NULL
;
403 jtag_add_dr_scan(3, fields
, -1);
405 jtag_add_runtest(0, -1);
407 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
409 if((retval
= jtag_execute_queue()) != ERROR_OK
)
416 LOG_DEBUG("in: 0x%8.8x", *(u32
*)in
);
420 LOG_ERROR("BUG: called with in == NULL");
428 void arm9tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
430 int retval
= ERROR_OK
;
431 /* get pointers to arch-specific information */
432 armv4_5_common_t
*armv4_5
= target
->arch_info
;
433 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
434 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
436 /* save r0 before using it and put system in ARM state
437 * to allow common handling of ARM and THUMB debugging */
439 /* fetch STR r0, [r0] */
440 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
441 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
442 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
443 /* STR r0, [r0] in Memory */
444 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
446 /* MOV r0, r15 fetched, STR in Decode */
447 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
448 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
449 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
450 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
451 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
452 /* nothing fetched, STR r0, [r0] in Memory */
453 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
455 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
456 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
458 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
460 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
461 /* LDR in Memory (to account for interlock) */
462 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
465 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
466 /* NOP fetched, BX in Decode, MOV in Execute */
467 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
468 /* NOP fetched, BX in Execute (1) */
469 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
471 if((retval
= jtag_execute_queue()) != ERROR_OK
)
476 /* fix program counter:
477 * MOV r0, r15 was the 5th instruction (+8)
478 * reading PC in Thumb state gives address of instruction + 4
483 void arm9tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
486 /* get pointers to arch-specific information */
487 armv4_5_common_t
*armv4_5
= target
->arch_info
;
488 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
489 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
491 /* STMIA r0-15, [r0] at debug speed
492 * register values will start to appear on 4th DCLK
494 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
496 /* fetch NOP, STM in DECODE stage */
497 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
498 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
499 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
501 for (i
= 0; i
<= 15; i
++)
504 /* nothing fetched, STM in MEMORY (i'th cycle) */
505 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
510 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
513 /* get pointers to arch-specific information */
514 armv4_5_common_t
*armv4_5
= target
->arch_info
;
515 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
516 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
517 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
518 u32
*buf_u32
= buffer
;
519 u16
*buf_u16
= buffer
;
522 /* STMIA r0-15, [r0] at debug speed
523 * register values will start to appear on 4th DCLK
525 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
527 /* fetch NOP, STM in DECODE stage */
528 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
529 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
530 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
532 for (i
= 0; i
<= 15; i
++)
535 /* nothing fetched, STM in MEMORY (i'th cycle) */
539 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
542 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
545 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
552 void arm9tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
554 /* get pointers to arch-specific information */
555 armv4_5_common_t
*armv4_5
= target
->arch_info
;
556 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
557 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
560 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
561 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
562 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
563 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
564 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
567 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
568 /* fetch NOP, STR in DECODE stage */
569 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
570 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
571 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
572 /* nothing fetched, STR in MEMORY */
573 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
577 void arm9tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
579 /* get pointers to arch-specific information */
580 armv4_5_common_t
*armv4_5
= target
->arch_info
;
581 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
582 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
584 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
587 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
588 /* MSR2 fetched, MSR1 in DECODE */
589 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
590 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
592 /* nothing fetched, MSR1 in EXECUTE (2) */
593 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
594 /* nothing fetched, MSR1 in EXECUTE (3) */
595 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
596 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
597 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
598 /* nothing fetched, MSR2 in EXECUTE (2) */
599 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
600 /* nothing fetched, MSR2 in EXECUTE (3) */
601 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
602 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
603 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
604 /* nothing fetched, MSR3 in EXECUTE (2) */
605 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
606 /* nothing fetched, MSR3 in EXECUTE (3) */
607 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
608 /* NOP fetched, MSR4 in EXECUTE (1) */
609 /* last MSR writes flags, which takes only one cycle */
610 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
613 void arm9tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
615 /* get pointers to arch-specific information */
616 armv4_5_common_t
*armv4_5
= target
->arch_info
;
617 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
618 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
620 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
623 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
624 /* NOP fetched, MSR in DECODE */
625 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
626 /* NOP fetched, MSR in EXECUTE (1) */
627 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
629 /* rot == 4 writes flags, which takes only one cycle */
632 /* nothing fetched, MSR in EXECUTE (2) */
633 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
634 /* nothing fetched, MSR in EXECUTE (3) */
635 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
639 void arm9tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
642 /* get pointers to arch-specific information */
643 armv4_5_common_t
*armv4_5
= target
->arch_info
;
644 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
645 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
647 /* LDMIA r0-15, [r0] at debug speed
648 * register values will start to appear on 4th DCLK
650 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
652 /* fetch NOP, LDM in DECODE stage */
653 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
654 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
655 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
657 for (i
= 0; i
<= 15; i
++)
660 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
661 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
663 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
667 void arm9tdmi_load_word_regs(target_t
*target
, u32 mask
)
669 /* get pointers to arch-specific information */
670 armv4_5_common_t
*armv4_5
= target
->arch_info
;
671 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
672 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
674 /* put system-speed load-multiple into the pipeline */
675 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
676 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
680 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
682 /* get pointers to arch-specific information */
683 armv4_5_common_t
*armv4_5
= target
->arch_info
;
684 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
685 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
687 /* put system-speed load half-word into the pipeline */
688 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
689 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
692 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
694 /* get pointers to arch-specific information */
695 armv4_5_common_t
*armv4_5
= target
->arch_info
;
696 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
697 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
699 /* put system-speed load byte into the pipeline */
700 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
701 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
705 void arm9tdmi_store_word_regs(target_t
*target
, u32 mask
)
707 /* get pointers to arch-specific information */
708 armv4_5_common_t
*armv4_5
= target
->arch_info
;
709 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
710 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
712 /* put system-speed store-multiple into the pipeline */
713 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
714 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
718 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
720 /* get pointers to arch-specific information */
721 armv4_5_common_t
*armv4_5
= target
->arch_info
;
722 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
723 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
725 /* put system-speed store half-word into the pipeline */
726 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
727 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
731 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
733 /* get pointers to arch-specific information */
734 armv4_5_common_t
*armv4_5
= target
->arch_info
;
735 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
736 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
738 /* put system-speed store byte into the pipeline */
739 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
740 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
744 void arm9tdmi_write_pc(target_t
*target
, u32 pc
)
746 /* get pointers to arch-specific information */
747 armv4_5_common_t
*armv4_5
= target
->arch_info
;
748 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
749 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
751 /* LDMIA r0-15, [r0] at debug speed
752 * register values will start to appear on 4th DCLK
754 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
756 /* fetch NOP, LDM in DECODE stage */
757 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
758 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
759 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
760 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
761 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
762 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
763 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
764 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
765 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
766 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
767 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
771 void arm9tdmi_branch_resume(target_t
*target
)
773 /* get pointers to arch-specific information */
774 armv4_5_common_t
*armv4_5
= target
->arch_info
;
775 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
776 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
778 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
779 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
783 void arm9tdmi_branch_resume_thumb(target_t
*target
)
787 /* get pointers to arch-specific information */
788 armv4_5_common_t
*armv4_5
= target
->arch_info
;
789 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
790 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
791 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
793 /* LDMIA r0-15, [r0] at debug speed
794 * register values will start to appear on 4th DCLK
796 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
798 /* fetch NOP, LDM in DECODE stage */
799 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
800 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
801 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
802 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
803 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
804 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
805 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
807 /* Branch and eXchange */
808 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
810 embeddedice_read_reg(dbg_stat
);
812 /* fetch NOP, BX in DECODE stage */
813 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
815 embeddedice_read_reg(dbg_stat
);
817 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
818 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
820 /* target is now in Thumb state */
821 embeddedice_read_reg(dbg_stat
);
823 /* load r0 value, MOV_IM in Decode*/
824 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
825 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
826 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
827 /* fetch NOP, LDR in Execute */
828 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
829 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
830 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
831 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
832 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
834 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
835 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
837 embeddedice_read_reg(dbg_stat
);
839 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
840 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
844 void arm9tdmi_enable_single_step(target_t
*target
)
846 /* get pointers to arch-specific information */
847 armv4_5_common_t
*armv4_5
= target
->arch_info
;
848 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
850 if (arm7_9
->has_single_step
)
852 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
853 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
857 arm7_9_enable_eice_step(target
);
861 void arm9tdmi_disable_single_step(target_t
*target
)
863 /* get pointers to arch-specific information */
864 armv4_5_common_t
*armv4_5
= target
->arch_info
;
865 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
867 if (arm7_9
->has_single_step
)
869 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
870 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
874 arm7_9_disable_eice_step(target
);
878 void arm9tdmi_build_reg_cache(target_t
*target
)
880 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
881 /* get pointers to arch-specific information */
882 armv4_5_common_t
*armv4_5
= target
->arch_info
;
884 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
885 armv4_5
->core_cache
= (*cache_p
);
889 int arm9tdmi_examine(struct target_s
*target
)
891 /* get pointers to arch-specific information */
893 armv4_5_common_t
*armv4_5
= target
->arch_info
;
894 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
895 if (!target
->type
->examined
)
897 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
899 /* one extra register (vector catch) */
900 t
=embeddedice_build_reg_cache(target
, arm7_9
);
904 arm7_9
->eice_cache
= (*cache_p
);
908 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
909 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
910 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
912 target
->type
->examined
= 1;
914 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
916 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
920 if ((retval
=etm_setup(target
))!=ERROR_OK
)
926 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
929 arm9tdmi_build_reg_cache(target
);
935 int arm9tdmi_quit(void)
941 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, int chain_pos
, const char *variant
)
943 armv4_5_common_t
*armv4_5
;
944 arm7_9_common_t
*arm7_9
;
946 arm7_9
= &arm9tdmi
->arm7_9_common
;
947 armv4_5
= &arm7_9
->armv4_5_common
;
949 /* prepare JTAG information for the new target */
950 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
951 arm7_9
->jtag_info
.scann_size
= 5;
953 /* register arch-specific functions */
954 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
955 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
956 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
957 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
958 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
960 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
961 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
962 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
964 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
965 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
966 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
968 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
969 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
970 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
972 arm7_9
->write_pc
= arm9tdmi_write_pc
;
973 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
974 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
976 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
977 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
979 arm7_9
->pre_debug_entry
= NULL
;
980 arm7_9
->post_debug_entry
= NULL
;
982 arm7_9
->pre_restore_context
= NULL
;
983 arm7_9
->post_restore_context
= NULL
;
985 /* initialize arch-specific breakpoint handling */
986 arm7_9
->arm_bkpt
= 0xdeeedeee;
987 arm7_9
->thumb_bkpt
= 0xdeee;
989 arm7_9
->dbgreq_adjust_pc
= 3;
990 arm7_9
->arch_info
= arm9tdmi
;
992 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
993 arm9tdmi
->arch_info
= NULL
;
997 arm9tdmi
->variant
= strdup(variant
);
1001 arm9tdmi
->variant
= strdup("");
1004 arm7_9_init_arch_info(target
, arm7_9
);
1006 /* override use of DBGRQ, this is safe on ARM9TDMI */
1007 arm7_9
->use_dbgrq
= 1;
1009 /* all ARM9s have the vector catch register */
1010 arm7_9
->has_vector_catch
= 1;
1015 int arm9tdmi_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
)
1017 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1018 arm7_9_common_t
*arm7_9
;
1019 arm9tdmi_common_t
*arm9tdmi
;
1021 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
1026 arm7_9
= armv4_5
->arch_info
;
1027 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
1032 arm9tdmi
= arm7_9
->arch_info
;
1033 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
1038 *armv4_5_p
= armv4_5
;
1040 *arm9tdmi_p
= arm9tdmi
;
1047 int arm9tdmi_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1049 arm9tdmi_common_t
*arm9tdmi
= calloc(1,sizeof(arm9tdmi_common_t
));
1051 arm9tdmi_init_arch_info(target
, arm9tdmi
, target
->chain_position
, target
->variant
);
1056 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
1060 command_t
*arm9tdmi_cmd
;
1063 retval
= arm7_9_register_commands(cmd_ctx
);
1065 arm9tdmi_cmd
= register_command(cmd_ctx
, NULL
, "arm9tdmi", NULL
, COMMAND_ANY
, "arm9tdmi specific commands");
1067 register_command(cmd_ctx
, arm9tdmi_cmd
, "vector_catch", handle_arm9tdmi_catch_vectors_command
, COMMAND_EXEC
, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1074 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1076 target_t
*target
= get_current_target(cmd_ctx
);
1077 armv4_5_common_t
*armv4_5
;
1078 arm7_9_common_t
*arm7_9
;
1079 arm9tdmi_common_t
*arm9tdmi
;
1080 reg_t
*vector_catch
;
1081 u32 vector_catch_value
;
1084 if (arm9tdmi_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
) != ERROR_OK
)
1086 command_print(cmd_ctx
, "current target isn't an ARM9TDMI based target");
1090 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
1092 /* read the vector catch register if necessary */
1093 if (!vector_catch
->valid
)
1094 embeddedice_read_reg(vector_catch
);
1096 /* get the current setting */
1097 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1101 vector_catch_value
= 0x0;
1102 if (strcmp(args
[0], "all") == 0)
1104 vector_catch_value
= 0xdf;
1106 else if (strcmp(args
[0], "none") == 0)
1112 for (i
= 0; i
< argc
; i
++)
1114 /* go through list of vectors */
1115 for(j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
1117 if (strcmp(args
[i
], arm9tdmi_vectors
[j
].name
) == 0)
1119 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
1124 /* complain if vector wasn't found */
1125 if (!arm9tdmi_vectors
[j
].name
)
1127 command_print(cmd_ctx
, "vector '%s' not found, leaving current setting unchanged", args
[i
]);
1129 /* reread current setting */
1130 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1137 /* store new settings */
1138 buf_set_u32(vector_catch
->value
, 0, 32, vector_catch_value
);
1139 embeddedice_store_reg(vector_catch
);
1142 /* output current settings (skip RESERVED vector) */
1143 for (i
= 0; i
< 8; i
++)
1147 command_print(cmd_ctx
, "%s: %s", arm9tdmi_vectors
[i
].name
,
1148 (vector_catch_value
& (1 << i
)) ? "catch" : "don't catch");
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