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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * Copyright (C) 2019-2021, Ampere Computing LLC *
17 * *
18 * This program is free software; you can redistribute it and/or modify *
19 * it under the terms of the GNU General Public License as published by *
20 * the Free Software Foundation; either version 2 of the License, or *
21 * (at your option) any later version. *
22 * *
23 * This program is distributed in the hope that it will be useful, *
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
26 * GNU General Public License for more details. *
27 * *
28 * You should have received a copy of the GNU General Public License *
29 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focuses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction pipelining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include "arm_coresight.h"
79 #include "jtag/swd.h"
80 #include "transport/transport.h"
81 #include <helper/align.h>
82 #include <helper/jep106.h>
83 #include <helper/time_support.h>
84 #include <helper/list.h>
85 #include <helper/jim-nvp.h>
86
87 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
88
89 /*
90 uint32_t tar_block_size(uint32_t address)
91 Return the largest block starting at address that does not cross a tar block size alignment boundary
92 */
93 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
94 {
95 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
96 }
97
98 /***************************************************************************
99 * *
100 * DP and MEM-AP register access through APACC and DPACC *
101 * *
102 ***************************************************************************/
103
104 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
105 {
106 csw |= ap->csw_default;
107
108 if (csw != ap->csw_value) {
109 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
110 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
111 if (retval != ERROR_OK) {
112 ap->csw_value = 0;
113 return retval;
114 }
115 ap->csw_value = csw;
116 }
117 return ERROR_OK;
118 }
119
120 static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
121 {
122 if (!ap->tar_valid || tar != ap->tar_value) {
123 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
124 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL));
125 if (retval == ERROR_OK && is_64bit_ap(ap)) {
126 /* See if bits 63:32 of tar is different from last setting */
127 if ((ap->tar_value >> 32) != (tar >> 32))
128 retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32));
129 }
130 if (retval != ERROR_OK) {
131 ap->tar_valid = false;
132 return retval;
133 }
134 ap->tar_value = tar;
135 ap->tar_valid = true;
136 }
137 return ERROR_OK;
138 }
139
140 static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
141 {
142 uint32_t lower;
143 uint32_t upper = 0;
144
145 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower);
146 if (retval == ERROR_OK && is_64bit_ap(ap))
147 retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper);
148
149 if (retval != ERROR_OK) {
150 ap->tar_valid = false;
151 return retval;
152 }
153
154 retval = dap_run(ap->dap);
155 if (retval != ERROR_OK) {
156 ap->tar_valid = false;
157 return retval;
158 }
159
160 *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
161
162 ap->tar_value = *tar;
163 ap->tar_valid = true;
164 return ERROR_OK;
165 }
166
167 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
168 {
169 switch (ap->csw_value & CSW_ADDRINC_MASK) {
170 case CSW_ADDRINC_SINGLE:
171 switch (ap->csw_value & CSW_SIZE_MASK) {
172 case CSW_8BIT:
173 return 1;
174 case CSW_16BIT:
175 return 2;
176 case CSW_32BIT:
177 return 4;
178 default:
179 return 0;
180 }
181 case CSW_ADDRINC_PACKED:
182 return 4;
183 }
184 return 0;
185 }
186
187 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
188 */
189 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
190 {
191 if (!ap->tar_valid)
192 return;
193
194 uint32_t inc = mem_ap_get_tar_increment(ap);
195 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
196 ap->tar_valid = false;
197 else
198 ap->tar_value += inc;
199 }
200
201 /**
202 * Queue transactions setting up transfer parameters for the
203 * currently selected MEM-AP.
204 *
205 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
206 * initiate data reads or writes using memory or peripheral addresses.
207 * If the CSW is configured for it, the TAR may be automatically
208 * incremented after each transfer.
209 *
210 * @param ap The MEM-AP.
211 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
212 * matches the cached value, the register is not changed.
213 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
214 * matches the cached address, the register is not changed.
215 *
216 * @return ERROR_OK if the transaction was properly queued, else a fault code.
217 */
218 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
219 {
220 int retval;
221 retval = mem_ap_setup_csw(ap, csw);
222 if (retval != ERROR_OK)
223 return retval;
224 retval = mem_ap_setup_tar(ap, tar);
225 if (retval != ERROR_OK)
226 return retval;
227 return ERROR_OK;
228 }
229
230 /**
231 * Asynchronous (queued) read of a word from memory or a system register.
232 *
233 * @param ap The MEM-AP to access.
234 * @param address Address of the 32-bit word to read; it must be
235 * readable by the currently selected MEM-AP.
236 * @param value points to where the word will be stored when the
237 * transaction queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
242 uint32_t *value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when reading several consecutive addresses.
248 */
249 retval = mem_ap_setup_transfer(ap,
250 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
251 address & 0xFFFFFFFFFFFFFFF0ull);
252 if (retval != ERROR_OK)
253 return retval;
254
255 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
256 }
257
258 /**
259 * Synchronous read of a word from memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param ap The MEM-AP to access.
263 * @param address Address of the 32-bit word to read; it must be
264 * readable by the currently selected MEM-AP.
265 * @param value points to where the result will be stored.
266 *
267 * @return ERROR_OK for success; *value holds the result.
268 * Otherwise a fault code.
269 */
270 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
271 uint32_t *value)
272 {
273 int retval;
274
275 retval = mem_ap_read_u32(ap, address, value);
276 if (retval != ERROR_OK)
277 return retval;
278
279 return dap_run(ap->dap);
280 }
281
282 /**
283 * Asynchronous (queued) write of a word to memory or a system register.
284 *
285 * @param ap The MEM-AP to access.
286 * @param address Address to be written; it must be writable by
287 * the currently selected MEM-AP.
288 * @param value Word that will be written to the address when transaction
289 * queue is flushed (assuming no errors).
290 *
291 * @return ERROR_OK for success. Otherwise a fault code.
292 */
293 int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
294 uint32_t value)
295 {
296 int retval;
297
298 /* Use banked addressing (REG_BDx) to avoid some link traffic
299 * (updating TAR) when writing several consecutive addresses.
300 */
301 retval = mem_ap_setup_transfer(ap,
302 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
303 address & 0xFFFFFFFFFFFFFFF0ull);
304 if (retval != ERROR_OK)
305 return retval;
306
307 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
308 value);
309 }
310
311 /**
312 * Synchronous write of a word to memory or a system register.
313 * As a side effect, this flushes any queued transactions.
314 *
315 * @param ap The MEM-AP to access.
316 * @param address Address to be written; it must be writable by
317 * the currently selected MEM-AP.
318 * @param value Word that will be written.
319 *
320 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
321 */
322 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
323 uint32_t value)
324 {
325 int retval = mem_ap_write_u32(ap, address, value);
326
327 if (retval != ERROR_OK)
328 return retval;
329
330 return dap_run(ap->dap);
331 }
332
333 /**
334 * Synchronous write of a block of memory, using a specific access size.
335 *
336 * @param ap The MEM-AP to access.
337 * @param buffer The data buffer to write. No particular alignment is assumed.
338 * @param size Which access size to use, in bytes. 1, 2 or 4.
339 * @param count The number of writes to do (in size units, not bytes).
340 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
341 * @param addrinc Whether the target address should be increased for each write or not. This
342 * should normally be true, except when writing to e.g. a FIFO.
343 * @return ERROR_OK on success, otherwise an error code.
344 */
345 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
346 target_addr_t address, bool addrinc)
347 {
348 struct adiv5_dap *dap = ap->dap;
349 size_t nbytes = size * count;
350 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
351 uint32_t csw_size;
352 target_addr_t addr_xor;
353 int retval = ERROR_OK;
354
355 /* TI BE-32 Quirks mode:
356 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
357 * size write address bytes written in order
358 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
359 * 2 TAR ^ 2 (val >> 8), (val)
360 * 1 TAR ^ 3 (val)
361 * For example, if you attempt to write a single byte to address 0, the processor
362 * will actually write a byte to address 3.
363 *
364 * To make writes of size < 4 work as expected, we xor a value with the address before
365 * setting the TAP, and we set the TAP after every transfer rather then relying on
366 * address increment. */
367
368 if (size == 4) {
369 csw_size = CSW_32BIT;
370 addr_xor = 0;
371 } else if (size == 2) {
372 csw_size = CSW_16BIT;
373 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
374 } else if (size == 1) {
375 csw_size = CSW_8BIT;
376 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
377 } else {
378 return ERROR_TARGET_UNALIGNED_ACCESS;
379 }
380
381 if (ap->unaligned_access_bad && (address % size != 0))
382 return ERROR_TARGET_UNALIGNED_ACCESS;
383
384 while (nbytes > 0) {
385 uint32_t this_size = size;
386
387 /* Select packed transfer if possible */
388 if (addrinc && ap->packed_transfers && nbytes >= 4
389 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
390 this_size = 4;
391 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
392 } else {
393 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
394 }
395
396 if (retval != ERROR_OK)
397 break;
398
399 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
400 if (retval != ERROR_OK)
401 return retval;
402
403 /* How many source bytes each transfer will consume, and their location in the DRW,
404 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
405 uint32_t outvalue = 0;
406 uint32_t drw_byte_idx = address;
407 if (dap->ti_be_32_quirks) {
408 switch (this_size) {
409 case 4:
410 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
411 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
412 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
413 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
414 break;
415 case 2:
416 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
417 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
418 break;
419 case 1:
420 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
421 break;
422 }
423 } else {
424 switch (this_size) {
425 case 4:
426 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
427 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
428 /* fallthrough */
429 case 2:
430 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
431 /* fallthrough */
432 case 1:
433 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
434 }
435 }
436
437 nbytes -= this_size;
438
439 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
440 if (retval != ERROR_OK)
441 break;
442
443 mem_ap_update_tar_cache(ap);
444 if (addrinc)
445 address += this_size;
446 }
447
448 /* REVISIT: Might want to have a queued version of this function that does not run. */
449 if (retval == ERROR_OK)
450 retval = dap_run(dap);
451
452 if (retval != ERROR_OK) {
453 target_addr_t tar;
454 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
455 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
456 else
457 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
458 }
459
460 return retval;
461 }
462
463 /**
464 * Synchronous read of a block of memory, using a specific access size.
465 *
466 * @param ap The MEM-AP to access.
467 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
468 * @param size Which access size to use, in bytes. 1, 2 or 4.
469 * @param count The number of reads to do (in size units, not bytes).
470 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
471 * @param addrinc Whether the target address should be increased after each read or not. This
472 * should normally be true, except when reading from e.g. a FIFO.
473 * @return ERROR_OK on success, otherwise an error code.
474 */
475 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
476 target_addr_t adr, bool addrinc)
477 {
478 struct adiv5_dap *dap = ap->dap;
479 size_t nbytes = size * count;
480 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
481 uint32_t csw_size;
482 target_addr_t address = adr;
483 int retval = ERROR_OK;
484
485 /* TI BE-32 Quirks mode:
486 * Reads on big-endian TMS570 behave strangely differently than writes.
487 * They read from the physical address requested, but with DRW byte-reversed.
488 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
489 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
490 * so avoid them. */
491
492 if (size == 4)
493 csw_size = CSW_32BIT;
494 else if (size == 2)
495 csw_size = CSW_16BIT;
496 else if (size == 1)
497 csw_size = CSW_8BIT;
498 else
499 return ERROR_TARGET_UNALIGNED_ACCESS;
500
501 if (ap->unaligned_access_bad && (adr % size != 0))
502 return ERROR_TARGET_UNALIGNED_ACCESS;
503
504 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
505 * over-allocation if packed transfers are going to be used, but determining the real need at
506 * this point would be messy. */
507 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
508 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
509 uint32_t *read_ptr = read_buf;
510 if (!read_buf) {
511 LOG_ERROR("Failed to allocate read buffer");
512 return ERROR_FAIL;
513 }
514
515 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
516 * useful bytes it contains, and their location in the word, depends on the type of transfer
517 * and alignment. */
518 while (nbytes > 0) {
519 uint32_t this_size = size;
520
521 /* Select packed transfer if possible */
522 if (addrinc && ap->packed_transfers && nbytes >= 4
523 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
524 this_size = 4;
525 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
526 } else {
527 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
528 }
529 if (retval != ERROR_OK)
530 break;
531
532 retval = mem_ap_setup_tar(ap, address);
533 if (retval != ERROR_OK)
534 break;
535
536 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
537 if (retval != ERROR_OK)
538 break;
539
540 nbytes -= this_size;
541 if (addrinc)
542 address += this_size;
543
544 mem_ap_update_tar_cache(ap);
545 }
546
547 if (retval == ERROR_OK)
548 retval = dap_run(dap);
549
550 /* Restore state */
551 address = adr;
552 nbytes = size * count;
553 read_ptr = read_buf;
554
555 /* If something failed, read TAR to find out how much data was successfully read, so we can
556 * at least give the caller what we have. */
557 if (retval != ERROR_OK) {
558 target_addr_t tar;
559 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
560 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
561 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
562 if (nbytes > tar - address)
563 nbytes = tar - address;
564 } else {
565 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
566 nbytes = 0;
567 }
568 }
569
570 /* Replay loop to populate caller's buffer from the correct word and byte lane */
571 while (nbytes > 0) {
572 uint32_t this_size = size;
573
574 if (addrinc && ap->packed_transfers && nbytes >= 4
575 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
576 this_size = 4;
577 }
578
579 if (dap->ti_be_32_quirks) {
580 switch (this_size) {
581 case 4:
582 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
583 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
584 /* fallthrough */
585 case 2:
586 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
587 /* fallthrough */
588 case 1:
589 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
590 }
591 } else {
592 switch (this_size) {
593 case 4:
594 *buffer++ = *read_ptr >> 8 * (address++ & 3);
595 *buffer++ = *read_ptr >> 8 * (address++ & 3);
596 /* fallthrough */
597 case 2:
598 *buffer++ = *read_ptr >> 8 * (address++ & 3);
599 /* fallthrough */
600 case 1:
601 *buffer++ = *read_ptr >> 8 * (address++ & 3);
602 }
603 }
604
605 read_ptr++;
606 nbytes -= this_size;
607 }
608
609 free(read_buf);
610 return retval;
611 }
612
613 int mem_ap_read_buf(struct adiv5_ap *ap,
614 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
615 {
616 return mem_ap_read(ap, buffer, size, count, address, true);
617 }
618
619 int mem_ap_write_buf(struct adiv5_ap *ap,
620 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
621 {
622 return mem_ap_write(ap, buffer, size, count, address, true);
623 }
624
625 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
626 uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
627 {
628 return mem_ap_read(ap, buffer, size, count, address, false);
629 }
630
631 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
632 const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
633 {
634 return mem_ap_write(ap, buffer, size, count, address, false);
635 }
636
637 /*--------------------------------------------------------------------------*/
638
639
640 #define DAP_POWER_DOMAIN_TIMEOUT (10)
641
642 /*--------------------------------------------------------------------------*/
643
644 /**
645 * Invalidate cached DP select and cached TAR and CSW of all APs
646 */
647 void dap_invalidate_cache(struct adiv5_dap *dap)
648 {
649 dap->select = DP_SELECT_INVALID;
650 dap->last_read = NULL;
651
652 int i;
653 for (i = 0; i <= DP_APSEL_MAX; i++) {
654 /* force csw and tar write on the next mem-ap access */
655 dap->ap[i].tar_valid = false;
656 dap->ap[i].csw_value = 0;
657 }
658 }
659
660 /**
661 * Initialize a DAP. This sets up the power domains, prepares the DP
662 * for further use and activates overrun checking.
663 *
664 * @param dap The DAP being initialized.
665 */
666 int dap_dp_init(struct adiv5_dap *dap)
667 {
668 int retval;
669
670 LOG_DEBUG("%s", adiv5_dap_name(dap));
671
672 dap->do_reconnect = false;
673 dap_invalidate_cache(dap);
674
675 /*
676 * Early initialize dap->dp_ctrl_stat.
677 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
678 * fails and sets the sticky error, it will trigger the clearing
679 * of the sticky. Without this initialization system and debug power
680 * would be disabled while clearing the sticky error bit.
681 */
682 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
683
684 /*
685 * This write operation clears the sticky error bit in jtag mode only and
686 * is ignored in swd mode. It also powers-up system and debug domains in
687 * both jtag and swd modes, if not done before.
688 */
689 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
690 if (retval != ERROR_OK)
691 return retval;
692
693 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
694 if (retval != ERROR_OK)
695 return retval;
696
697 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
698 if (retval != ERROR_OK)
699 return retval;
700
701 /* Check that we have debug power domains activated */
702 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
703 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
704 CDBGPWRUPACK, CDBGPWRUPACK,
705 DAP_POWER_DOMAIN_TIMEOUT);
706 if (retval != ERROR_OK)
707 return retval;
708
709 if (!dap->ignore_syspwrupack) {
710 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
711 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
712 CSYSPWRUPACK, CSYSPWRUPACK,
713 DAP_POWER_DOMAIN_TIMEOUT);
714 if (retval != ERROR_OK)
715 return retval;
716 }
717
718 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
719 if (retval != ERROR_OK)
720 return retval;
721
722 /* With debug power on we can activate OVERRUN checking */
723 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
724 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
725 if (retval != ERROR_OK)
726 return retval;
727 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
728 if (retval != ERROR_OK)
729 return retval;
730
731 retval = dap_run(dap);
732 if (retval != ERROR_OK)
733 return retval;
734
735 return retval;
736 }
737
738 /**
739 * Initialize a DAP or do reconnect if DAP is not accessible.
740 *
741 * @param dap The DAP being initialized.
742 */
743 int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
744 {
745 LOG_DEBUG("%s", adiv5_dap_name(dap));
746
747 /*
748 * Early initialize dap->dp_ctrl_stat.
749 * In jtag mode only, if the following atomic reads fail and set the
750 * sticky error, it will trigger the clearing of the sticky. Without this
751 * initialization system and debug power would be disabled while clearing
752 * the sticky error bit.
753 */
754 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
755
756 dap->do_reconnect = false;
757
758 dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
759 if (dap->do_reconnect) {
760 /* dap connect calls dap_dp_init() after transport dependent initialization */
761 return dap->ops->connect(dap);
762 } else {
763 return dap_dp_init(dap);
764 }
765 }
766
767 /**
768 * Initialize a DAP. This sets up the power domains, prepares the DP
769 * for further use, and arranges to use AP #0 for all AP operations
770 * until dap_ap-select() changes that policy.
771 *
772 * @param ap The MEM-AP being initialized.
773 */
774 int mem_ap_init(struct adiv5_ap *ap)
775 {
776 /* check that we support packed transfers */
777 uint32_t csw, cfg;
778 int retval;
779 struct adiv5_dap *dap = ap->dap;
780
781 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
782 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
783 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
784 if (retval != ERROR_OK)
785 return retval;
786
787 retval = dap_run(dap);
788 if (retval != ERROR_OK)
789 return retval;
790
791 ap->cfg_reg = cfg;
792 ap->tar_valid = false;
793 ap->csw_value = 0; /* force csw and tar write */
794 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
795 if (retval != ERROR_OK)
796 return retval;
797
798 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
799 if (retval != ERROR_OK)
800 return retval;
801
802 retval = dap_run(dap);
803 if (retval != ERROR_OK)
804 return retval;
805
806 if (csw & CSW_ADDRINC_PACKED)
807 ap->packed_transfers = true;
808 else
809 ap->packed_transfers = false;
810
811 /* Packed transfers on TI BE-32 processors do not work correctly in
812 * many cases. */
813 if (dap->ti_be_32_quirks)
814 ap->packed_transfers = false;
815
816 LOG_DEBUG("MEM_AP Packed Transfers: %s",
817 ap->packed_transfers ? "enabled" : "disabled");
818
819 /* The ARM ADI spec leaves implementation-defined whether unaligned
820 * memory accesses work, only work partially, or cause a sticky error.
821 * On TI BE-32 processors, reads seem to return garbage in some bytes
822 * and unaligned writes seem to cause a sticky error.
823 * TODO: it would be nice to have a way to detect whether unaligned
824 * operations are supported on other processors. */
825 ap->unaligned_access_bad = dap->ti_be_32_quirks;
826
827 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
828 !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
829
830 return ERROR_OK;
831 }
832
833 /**
834 * Put the debug link into SWD mode, if the target supports it.
835 * The link's initial mode may be either JTAG (for example,
836 * with SWJ-DP after reset) or SWD.
837 *
838 * Note that targets using the JTAG-DP do not support SWD, and that
839 * some targets which could otherwise support it may have been
840 * configured to disable SWD signaling
841 *
842 * @param dap The DAP used
843 * @return ERROR_OK or else a fault code.
844 */
845 int dap_to_swd(struct adiv5_dap *dap)
846 {
847 LOG_DEBUG("Enter SWD mode");
848
849 return dap_send_sequence(dap, JTAG_TO_SWD);
850 }
851
852 /**
853 * Put the debug link into JTAG mode, if the target supports it.
854 * The link's initial mode may be either SWD or JTAG.
855 *
856 * Note that targets implemented with SW-DP do not support JTAG, and
857 * that some targets which could otherwise support it may have been
858 * configured to disable JTAG signaling
859 *
860 * @param dap The DAP used
861 * @return ERROR_OK or else a fault code.
862 */
863 int dap_to_jtag(struct adiv5_dap *dap)
864 {
865 LOG_DEBUG("Enter JTAG mode");
866
867 return dap_send_sequence(dap, SWD_TO_JTAG);
868 }
869
870 /* CID interpretation -- see ARM IHI 0029E table B2-7
871 * and ARM IHI 0031E table D1-2.
872 *
873 * From 2009/11/25 commit 21378f58b604:
874 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
875 * Let's keep it as is, for the time being
876 */
877 static const char *class_description[16] = {
878 [0x0] = "Generic verification component",
879 [0x1] = "ROM table",
880 [0x2] = "Reserved",
881 [0x3] = "Reserved",
882 [0x4] = "Reserved",
883 [0x5] = "Reserved",
884 [0x6] = "Reserved",
885 [0x7] = "Reserved",
886 [0x8] = "Reserved",
887 [0x9] = "CoreSight component",
888 [0xA] = "Reserved",
889 [0xB] = "Peripheral Test Block",
890 [0xC] = "Reserved",
891 [0xD] = "OptimoDE DESS", /* see above */
892 [0xE] = "Generic IP component",
893 [0xF] = "CoreLink, PrimeCell or System component",
894 };
895
896 #define ARCH_ID(architect, archid) ( \
897 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
898 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
899 )
900
901 static const struct {
902 uint32_t arch_id;
903 const char *description;
904 } class0x9_devarch[] = {
905 /* keep same unsorted order as in ARM IHI0029E */
906 { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
907 { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
908 { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
909 { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
910 { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
911 { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
912 { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
913 { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
914 { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
915 { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
916 { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
917 { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
918 { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
919 { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
920 { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
921 { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
922 { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
923 { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
924 { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
925 { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
926 { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
927 { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
928 };
929
930 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
931 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
932
933 static const char *class0x9_devarch_description(uint32_t devarch)
934 {
935 if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
936 return "not present";
937
938 for (unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++)
939 if ((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id)
940 return class0x9_devarch[i].description;
941
942 return "unknown";
943 }
944
945 static const struct {
946 enum ap_type type;
947 const char *description;
948 } ap_types[] = {
949 { AP_TYPE_JTAG_AP, "JTAG-AP" },
950 { AP_TYPE_COM_AP, "COM-AP" },
951 { AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
952 { AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
953 { AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
954 { AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
955 { AP_TYPE_APB4_AP, "MEM-AP APB4" },
956 { AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
957 { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
958 };
959
960 static const char *ap_type_to_description(enum ap_type type)
961 {
962 for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
963 if (type == ap_types[i].type)
964 return ap_types[i].description;
965
966 return "Unknown";
967 }
968
969 /*
970 * This function checks the ID for each access port to find the requested Access Port type
971 */
972 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
973 {
974 int ap_num;
975
976 /* Maximum AP number is 255 since the SELECT register is 8 bits */
977 for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
978
979 /* read the IDR register of the Access Port */
980 uint32_t id_val = 0;
981
982 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
983 if (retval != ERROR_OK)
984 return retval;
985
986 retval = dap_run(dap);
987
988 /* Reading register for a non-existent AP should not cause an error,
989 * but just to be sure, try to continue searching if an error does happen.
990 */
991 if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
992 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
993 ap_type_to_description(type_to_find),
994 ap_num, id_val);
995
996 *ap_out = &dap->ap[ap_num];
997 return ERROR_OK;
998 }
999 }
1000
1001 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
1002 return ERROR_FAIL;
1003 }
1004
1005 int dap_get_debugbase(struct adiv5_ap *ap,
1006 target_addr_t *dbgbase, uint32_t *apid)
1007 {
1008 struct adiv5_dap *dap = ap->dap;
1009 int retval;
1010 uint32_t baseptr_upper, baseptr_lower;
1011
1012 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
1013 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
1014 if (retval != ERROR_OK)
1015 return retval;
1016 }
1017 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
1018 if (retval != ERROR_OK)
1019 return retval;
1020 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
1021 if (retval != ERROR_OK)
1022 return retval;
1023 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1024 if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
1025 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
1026 if (retval != ERROR_OK)
1027 return retval;
1028 }
1029
1030 retval = dap_run(dap);
1031 if (retval != ERROR_OK)
1032 return retval;
1033
1034 if (!is_64bit_ap(ap))
1035 baseptr_upper = 0;
1036 *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
1037
1038 return ERROR_OK;
1039 }
1040
1041 int dap_lookup_cs_component(struct adiv5_ap *ap,
1042 target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx)
1043 {
1044 uint32_t romentry, entry_offset = 0, devtype;
1045 target_addr_t component_base;
1046 int retval;
1047
1048 dbgbase &= 0xFFFFFFFFFFFFF000ull;
1049 *addr = 0;
1050
1051 do {
1052 retval = mem_ap_read_atomic_u32(ap, dbgbase |
1053 entry_offset, &romentry);
1054 if (retval != ERROR_OK)
1055 return retval;
1056
1057 component_base = dbgbase + (target_addr_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK);
1058
1059 if (romentry & ARM_CS_ROMENTRY_PRESENT) {
1060 uint32_t c_cid1;
1061 retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_CIDR1, &c_cid1);
1062 if (retval != ERROR_OK) {
1063 LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
1064 ", the corresponding core might be turned off", component_base);
1065 return retval;
1066 }
1067 unsigned int class = (c_cid1 & ARM_CS_CIDR1_CLASS_MASK) >> ARM_CS_CIDR1_CLASS_SHIFT;
1068 if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
1069 retval = dap_lookup_cs_component(ap, component_base,
1070 type, addr, idx);
1071 if (retval == ERROR_OK)
1072 break;
1073 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1074 return retval;
1075 }
1076
1077 retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &devtype);
1078 if (retval != ERROR_OK)
1079 return retval;
1080 if ((devtype & ARM_CS_C9_DEVTYPE_MASK) == type) {
1081 if (!*idx) {
1082 *addr = component_base;
1083 break;
1084 } else
1085 (*idx)--;
1086 }
1087 }
1088 entry_offset += 4;
1089 } while ((romentry > 0) && (entry_offset < 0xf00));
1090
1091 if (!*addr)
1092 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1093
1094 return ERROR_OK;
1095 }
1096
1097 /** Holds registers of a CoreSight component */
1098 struct cs_component_vals {
1099 uint64_t pid;
1100 uint32_t cid;
1101 uint32_t devarch;
1102 uint32_t devid;
1103 uint32_t devtype_memtype;
1104 };
1105
1106 /**
1107 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1108 *
1109 * @param ap Pointer to AP containing the component.
1110 * @param component_base On MEM-AP access method, base address of the component.
1111 * @param v Pointer to the struct holding the value of registers.
1112 *
1113 * @return ERROR_OK on success, else a fault code.
1114 */
1115 static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
1116 struct cs_component_vals *v)
1117 {
1118 assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
1119 assert(ap && v);
1120
1121 uint32_t cid0, cid1, cid2, cid3;
1122 uint32_t pid0, pid1, pid2, pid3, pid4;
1123 int retval = ERROR_OK;
1124
1125 /* sort by offset to gain speed */
1126
1127 /*
1128 * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1129 * only, but are at offset above 0xf00, so can be read on any device
1130 * without triggering error. Read them for eventual use on Class 0x9.
1131 */
1132 if (retval == ERROR_OK)
1133 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
1134
1135 if (retval == ERROR_OK)
1136 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVID, &v->devid);
1137
1138 /* Same address as ARM_CS_C1_MEMTYPE */
1139 if (retval == ERROR_OK)
1140 retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
1141
1142 if (retval == ERROR_OK)
1143 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
1144
1145 if (retval == ERROR_OK)
1146 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
1147 if (retval == ERROR_OK)
1148 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
1149 if (retval == ERROR_OK)
1150 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
1151 if (retval == ERROR_OK)
1152 retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
1153
1154 if (retval == ERROR_OK)
1155 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
1156 if (retval == ERROR_OK)
1157 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
1158 if (retval == ERROR_OK)
1159 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
1160 if (retval == ERROR_OK)
1161 retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
1162
1163 if (retval == ERROR_OK)
1164 retval = dap_run(ap->dap);
1165 if (retval != ERROR_OK) {
1166 LOG_DEBUG("Failed read CoreSight registers");
1167 return retval;
1168 }
1169
1170 v->cid = (cid3 & 0xff) << 24
1171 | (cid2 & 0xff) << 16
1172 | (cid1 & 0xff) << 8
1173 | (cid0 & 0xff);
1174 v->pid = (uint64_t)(pid4 & 0xff) << 32
1175 | (pid3 & 0xff) << 24
1176 | (pid2 & 0xff) << 16
1177 | (pid1 & 0xff) << 8
1178 | (pid0 & 0xff);
1179
1180 return ERROR_OK;
1181 }
1182
1183 /* Part number interpretations are from Cortex
1184 * core specs, the CoreSight components TRM
1185 * (ARM DDI 0314H), CoreSight System Design
1186 * Guide (ARM DGI 0012D) and ETM specs; also
1187 * from chip observation (e.g. TI SDTI).
1188 */
1189
1190 static const struct dap_part_nums {
1191 uint16_t designer_id;
1192 uint16_t part_num;
1193 const char *type;
1194 const char *full;
1195 } dap_part_nums[] = {
1196 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1197 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1198 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1199 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1200 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1201 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1202 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1203 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1204 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1205 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1206 { ARM_ID, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1207 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1208 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1209 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1210 { ARM_ID, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1211 { ARM_ID, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1212 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1213 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1214 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1215 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1216 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1217 { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1218 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1219 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1220 { ARM_ID, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1221 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1222 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1223 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1224 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1225 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1226 { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1227 { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1228 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1229 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1230 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1231 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1232 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1233 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1234 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1235 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1236 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1237 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1238 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1239 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1240 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1241 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1242 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1243 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1244 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1245 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1246 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1247 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1248 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1249 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1250 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1251 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1252 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1253 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1254 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1255 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1256 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1257 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1258 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1259 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1260 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1261 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1262 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1263 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1264 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1265 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1266 { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1267 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1268 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1269 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1270 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1271 { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1272 { ARM_ID, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1273 { ARM_ID, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1274 { ARM_ID, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1275 { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1276 { ARM_ID, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1277 { ARM_ID, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1278 { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1279 { ARM_ID, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1280 { ARM_ID, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1281 { ARM_ID, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1282 { ARM_ID, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1283 { ARM_ID, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1284 { ARM_ID, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1285 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1286 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1287 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1288 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1289 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1290 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1291 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1292 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1293 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1294 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1295 { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1296 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1297 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1298 { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1299 { ARM_ID, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1300 { ARM_ID, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1301 { ARM_ID, 0xd49, "Neoverse N2", "(Debug Unit)", },
1302 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1303 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1304 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1305 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1306 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1307 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1308 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1309 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1310 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1311 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1312 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1313 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1314 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1315 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1316 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1317 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1318 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1319 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1320 };
1321
1322 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
1323 {
1324 static const struct dap_part_nums unknown = {
1325 .type = "Unrecognized",
1326 .full = "",
1327 };
1328
1329 for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
1330 if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
1331 return &dap_part_nums[i];
1332
1333 return &unknown;
1334 }
1335
1336 static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
1337 {
1338 const char *major = "Reserved", *subtype = "Reserved";
1339 const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
1340 const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
1341 switch (devtype_major) {
1342 case 0:
1343 major = "Miscellaneous";
1344 switch (minor) {
1345 case 0:
1346 subtype = "other";
1347 break;
1348 case 4:
1349 subtype = "Validation component";
1350 break;
1351 }
1352 break;
1353 case 1:
1354 major = "Trace Sink";
1355 switch (minor) {
1356 case 0:
1357 subtype = "other";
1358 break;
1359 case 1:
1360 subtype = "Port";
1361 break;
1362 case 2:
1363 subtype = "Buffer";
1364 break;
1365 case 3:
1366 subtype = "Router";
1367 break;
1368 }
1369 break;
1370 case 2:
1371 major = "Trace Link";
1372 switch (minor) {
1373 case 0:
1374 subtype = "other";
1375 break;
1376 case 1:
1377 subtype = "Funnel, router";
1378 break;
1379 case 2:
1380 subtype = "Filter";
1381 break;
1382 case 3:
1383 subtype = "FIFO, buffer";
1384 break;
1385 }
1386 break;
1387 case 3:
1388 major = "Trace Source";
1389 switch (minor) {
1390 case 0:
1391 subtype = "other";
1392 break;
1393 case 1:
1394 subtype = "Processor";
1395 break;
1396 case 2:
1397 subtype = "DSP";
1398 break;
1399 case 3:
1400 subtype = "Engine/Coprocessor";
1401 break;
1402 case 4:
1403 subtype = "Bus";
1404 break;
1405 case 6:
1406 subtype = "Software";
1407 break;
1408 }
1409 break;
1410 case 4:
1411 major = "Debug Control";
1412 switch (minor) {
1413 case 0:
1414 subtype = "other";
1415 break;
1416 case 1:
1417 subtype = "Trigger Matrix";
1418 break;
1419 case 2:
1420 subtype = "Debug Auth";
1421 break;
1422 case 3:
1423 subtype = "Power Requestor";
1424 break;
1425 }
1426 break;
1427 case 5:
1428 major = "Debug Logic";
1429 switch (minor) {
1430 case 0:
1431 subtype = "other";
1432 break;
1433 case 1:
1434 subtype = "Processor";
1435 break;
1436 case 2:
1437 subtype = "DSP";
1438 break;
1439 case 3:
1440 subtype = "Engine/Coprocessor";
1441 break;
1442 case 4:
1443 subtype = "Bus";
1444 break;
1445 case 5:
1446 subtype = "Memory";
1447 break;
1448 }
1449 break;
1450 case 6:
1451 major = "Performance Monitor";
1452 switch (minor) {
1453 case 0:
1454 subtype = "other";
1455 break;
1456 case 1:
1457 subtype = "Processor";
1458 break;
1459 case 2:
1460 subtype = "DSP";
1461 break;
1462 case 3:
1463 subtype = "Engine/Coprocessor";
1464 break;
1465 case 4:
1466 subtype = "Bus";
1467 break;
1468 case 5:
1469 subtype = "Memory";
1470 break;
1471 }
1472 break;
1473 }
1474 command_print(cmd, "\t\tType is 0x%02x, %s, %s",
1475 devtype & ARM_CS_C9_DEVTYPE_MASK,
1476 major, subtype);
1477 return ERROR_OK;
1478 }
1479
1480 static int rtp_cs_component(struct command_invocation *cmd,
1481 struct adiv5_ap *ap, target_addr_t dbgbase, int depth);
1482
1483 static int rtp_rom_loop(struct command_invocation *cmd,
1484 struct adiv5_ap *ap, target_addr_t base_address, int depth,
1485 unsigned int max_entries)
1486 {
1487 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1488
1489 char tabs[16] = "";
1490
1491 if (depth)
1492 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1493
1494 unsigned int offset = 0;
1495 while (max_entries--) {
1496 uint32_t romentry;
1497 unsigned int saved_offset = offset;
1498
1499 int retval = mem_ap_read_atomic_u32(ap, base_address + offset, &romentry);
1500 offset += 4;
1501 if (retval != ERROR_OK) {
1502 LOG_DEBUG("Failed read ROM table entry");
1503 command_print(cmd, "\t%sROMTABLE[0x%x] Read error", tabs, saved_offset);
1504 command_print(cmd, "\t\tUnable to continue");
1505 command_print(cmd, "\t%s\tStop parsing of ROM table", tabs);
1506 return retval;
1507 }
1508
1509 command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32,
1510 tabs, saved_offset, romentry);
1511
1512 if (romentry == 0) {
1513 command_print(cmd, "\t%s\tEnd of ROM table", tabs);
1514 break;
1515 }
1516
1517 if (!(romentry & ARM_CS_ROMENTRY_PRESENT)) {
1518 command_print(cmd, "\t\tComponent not present");
1519 continue;
1520 }
1521
1522 /* Recurse. "romentry" is signed */
1523 target_addr_t component_base = base_address + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK);
1524 retval = rtp_cs_component(cmd, ap, component_base, depth + 1);
1525 if (retval != ERROR_OK) {
1526 /* TODO: do we need to send an ABORT before continuing? */
1527 LOG_DEBUG("Ignore error parsing CoreSight component");
1528 continue;
1529 }
1530 }
1531
1532 return ERROR_OK;
1533 }
1534
1535 static int rtp_cs_component(struct command_invocation *cmd,
1536 struct adiv5_ap *ap, target_addr_t base_address, int depth)
1537 {
1538 struct cs_component_vals v;
1539 int retval;
1540 char tabs[16] = "";
1541
1542 assert(IS_ALIGNED(base_address, ARM_CS_ALIGN));
1543
1544 if (depth > 16) {
1545 command_print(cmd, "\tTables too deep");
1546 return ERROR_FAIL;
1547 }
1548
1549 if (depth)
1550 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1551
1552 command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_address);
1553
1554 retval = rtp_read_cs_regs(ap, base_address, &v);
1555 if (retval != ERROR_OK) {
1556 command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
1557 return ERROR_OK; /* Don't abort recursion */
1558 }
1559
1560 if (!is_valid_arm_cs_cidr(v.cid)) {
1561 command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v.cid);
1562 return ERROR_OK; /* Don't abort recursion */
1563 }
1564
1565 /* component may take multiple 4K pages */
1566 uint32_t size = ARM_CS_PIDR_SIZE(v.pid);
1567 if (size > 0)
1568 command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_address - 0x1000 * size);
1569
1570 command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v.pid);
1571
1572 const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
1573 const unsigned int part_num = ARM_CS_PIDR_PART(v.pid);
1574 unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v.pid);
1575
1576 if (v.pid & ARM_CS_PIDR_JEDEC) {
1577 /* JEP106 code */
1578 command_print(cmd, "\t\tDesigner is 0x%03x, %s",
1579 designer_id, jep106_manufacturer(designer_id));
1580 } else {
1581 /* Legacy ASCII ID, clear invalid bits */
1582 designer_id &= 0x7f;
1583 command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
1584 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1585 }
1586
1587 const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
1588 command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
1589 command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
1590
1591 if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
1592 if (v.devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
1593 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1594 else
1595 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1596
1597 return rtp_rom_loop(cmd, ap, base_address, depth, 960);
1598 }
1599
1600 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
1601 retval = dap_devtype_display(cmd, v.devtype_memtype);
1602 if (retval != ERROR_OK)
1603 return retval;
1604
1605 /* REVISIT also show ARM_CS_C9_DEVID */
1606
1607 if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
1608 return ERROR_OK;
1609
1610 unsigned int architect_id = (v.devarch & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT;
1611 unsigned int revision = (v.devarch & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT;
1612 command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v.devarch,
1613 jep106_manufacturer(architect_id), class0x9_devarch_description(v.devarch),
1614 revision);
1615 /* quit if not ROM table */
1616 if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
1617 return ERROR_OK;
1618
1619 if (v.devid & ARM_CS_C9_DEVID_SYSMEM_MASK)
1620 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1621 else
1622 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1623
1624 return rtp_rom_loop(cmd, ap, base_address, depth, 512);
1625 }
1626
1627 /* Class other than 0x1 and 0x9 */
1628 return ERROR_OK;
1629 }
1630
1631 int dap_info_command(struct command_invocation *cmd,
1632 struct adiv5_ap *ap)
1633 {
1634 int retval;
1635 uint32_t apid;
1636 target_addr_t dbgbase;
1637 target_addr_t dbgaddr;
1638
1639 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1640 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1641 if (retval != ERROR_OK)
1642 return retval;
1643
1644 command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
1645 if (apid == 0) {
1646 command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
1647 return ERROR_FAIL;
1648 }
1649
1650 command_print(cmd, "\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
1651
1652 /* NOTE: a MEM-AP may have a single CoreSight component that's
1653 * not a ROM table ... or have no such components at all.
1654 */
1655 const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
1656
1657 if (class == AP_REG_IDR_CLASS_MEM_AP) {
1658 if (is_64bit_ap(ap))
1659 dbgaddr = 0xFFFFFFFFFFFFFFFFull;
1660 else
1661 dbgaddr = 0xFFFFFFFFul;
1662
1663 command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
1664
1665 if (dbgbase == dbgaddr || (dbgbase & 0x3) == 0x2) {
1666 command_print(cmd, "\tNo ROM table present");
1667 } else {
1668 if (dbgbase & 0x01)
1669 command_print(cmd, "\tValid ROM table present");
1670 else
1671 command_print(cmd, "\tROM table in legacy format");
1672
1673 rtp_cs_component(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
1674 }
1675 }
1676
1677 return ERROR_OK;
1678 }
1679
1680 enum adiv5_cfg_param {
1681 CFG_DAP,
1682 CFG_AP_NUM,
1683 CFG_BASEADDR,
1684 CFG_CTIBASE, /* DEPRECATED */
1685 };
1686
1687 static const struct jim_nvp nvp_config_opts[] = {
1688 { .name = "-dap", .value = CFG_DAP },
1689 { .name = "-ap-num", .value = CFG_AP_NUM },
1690 { .name = "-baseaddr", .value = CFG_BASEADDR },
1691 { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
1692 { .name = NULL, .value = -1 }
1693 };
1694
1695 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
1696 struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p)
1697 {
1698 if (!goi->argc)
1699 return JIM_OK;
1700
1701 Jim_SetEmptyResult(goi->interp);
1702
1703 struct jim_nvp *n;
1704 int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
1705 goi->argv[0], &n);
1706 if (e != JIM_OK)
1707 return JIM_CONTINUE;
1708
1709 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
1710 if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
1711 return JIM_CONTINUE;
1712
1713 e = jim_getopt_obj(goi, NULL);
1714 if (e != JIM_OK)
1715 return e;
1716
1717 switch (n->value) {
1718 case CFG_DAP:
1719 if (goi->isconfigure) {
1720 Jim_Obj *o_t;
1721 struct adiv5_dap *dap;
1722 e = jim_getopt_obj(goi, &o_t);
1723 if (e != JIM_OK)
1724 return e;
1725 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1726 if (!dap) {
1727 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1728 return JIM_ERR;
1729 }
1730 if (*dap_p && *dap_p != dap) {
1731 Jim_SetResultString(goi->interp,
1732 "DAP assignment cannot be changed!", -1);
1733 return JIM_ERR;
1734 }
1735 *dap_p = dap;
1736 } else {
1737 if (goi->argc)
1738 goto err_no_param;
1739 if (!*dap_p) {
1740 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1741 return JIM_ERR;
1742 }
1743 Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
1744 }
1745 break;
1746
1747 case CFG_AP_NUM:
1748 if (goi->isconfigure) {
1749 jim_wide ap_num;
1750 e = jim_getopt_wide(goi, &ap_num);
1751 if (e != JIM_OK)
1752 return e;
1753 if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
1754 Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
1755 return JIM_ERR;
1756 }
1757 *ap_num_p = ap_num;
1758 } else {
1759 if (goi->argc)
1760 goto err_no_param;
1761 if (*ap_num_p == DP_APSEL_INVALID) {
1762 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1763 return JIM_ERR;
1764 }
1765 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
1766 }
1767 break;
1768
1769 case CFG_CTIBASE:
1770 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
1771 /* fall through */
1772 case CFG_BASEADDR:
1773 if (goi->isconfigure) {
1774 jim_wide base;
1775 e = jim_getopt_wide(goi, &base);
1776 if (e != JIM_OK)
1777 return e;
1778 *base_p = (uint32_t)base;
1779 } else {
1780 if (goi->argc)
1781 goto err_no_param;
1782 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
1783 }
1784 break;
1785 };
1786
1787 return JIM_OK;
1788
1789 err_no_param:
1790 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
1791 return JIM_ERR;
1792 }
1793
1794 int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
1795 {
1796 struct adiv5_private_config *pc;
1797 int e;
1798
1799 pc = (struct adiv5_private_config *)target->private_config;
1800 if (!pc) {
1801 pc = calloc(1, sizeof(struct adiv5_private_config));
1802 pc->ap_num = DP_APSEL_INVALID;
1803 target->private_config = pc;
1804 }
1805
1806 target->has_dap = true;
1807
1808 e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
1809 if (e != JIM_OK)
1810 return e;
1811
1812 if (pc->dap && !target->dap_configured) {
1813 if (target->tap_configured) {
1814 pc->dap = NULL;
1815 Jim_SetResultString(goi->interp,
1816 "-chain-position and -dap configparams are mutually exclusive!", -1);
1817 return JIM_ERR;
1818 }
1819 target->tap = pc->dap->tap;
1820 target->dap_configured = true;
1821 }
1822
1823 return JIM_OK;
1824 }
1825
1826 int adiv5_verify_config(struct adiv5_private_config *pc)
1827 {
1828 if (!pc)
1829 return ERROR_FAIL;
1830
1831 if (!pc->dap)
1832 return ERROR_FAIL;
1833
1834 return ERROR_OK;
1835 }
1836
1837 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
1838 struct jim_getopt_info *goi)
1839 {
1840 return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
1841 }
1842
1843 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
1844 {
1845 p->dap = NULL;
1846 p->ap_num = DP_APSEL_INVALID;
1847 p->base = 0;
1848 return ERROR_OK;
1849 }
1850
1851 COMMAND_HANDLER(handle_dap_info_command)
1852 {
1853 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1854 uint32_t apsel;
1855
1856 switch (CMD_ARGC) {
1857 case 0:
1858 apsel = dap->apsel;
1859 break;
1860 case 1:
1861 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1862 if (apsel > DP_APSEL_MAX) {
1863 command_print(CMD, "Invalid AP number");
1864 return ERROR_COMMAND_ARGUMENT_INVALID;
1865 }
1866 break;
1867 default:
1868 return ERROR_COMMAND_SYNTAX_ERROR;
1869 }
1870
1871 return dap_info_command(CMD, &dap->ap[apsel]);
1872 }
1873
1874 COMMAND_HANDLER(dap_baseaddr_command)
1875 {
1876 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1877 uint32_t apsel, baseaddr_lower, baseaddr_upper;
1878 struct adiv5_ap *ap;
1879 target_addr_t baseaddr;
1880 int retval;
1881
1882 baseaddr_upper = 0;
1883
1884 switch (CMD_ARGC) {
1885 case 0:
1886 apsel = dap->apsel;
1887 break;
1888 case 1:
1889 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1890 /* AP address is in bits 31:24 of DP_SELECT */
1891 if (apsel > DP_APSEL_MAX) {
1892 command_print(CMD, "Invalid AP number");
1893 return ERROR_COMMAND_ARGUMENT_INVALID;
1894 }
1895 break;
1896 default:
1897 return ERROR_COMMAND_SYNTAX_ERROR;
1898 }
1899
1900 /* NOTE: assumes we're talking to a MEM-AP, which
1901 * has a base address. There are other kinds of AP,
1902 * though they're not common for now. This should
1903 * use the ID register to verify it's a MEM-AP.
1904 */
1905
1906 ap = dap_ap(dap, apsel);
1907 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
1908
1909 if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
1910 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
1911
1912 if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
1913 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1914 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
1915 }
1916
1917 if (retval == ERROR_OK)
1918 retval = dap_run(dap);
1919 if (retval != ERROR_OK)
1920 return retval;
1921
1922 if (is_64bit_ap(ap)) {
1923 baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
1924 command_print(CMD, "0x%016" PRIx64, baseaddr);
1925 } else
1926 command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
1927
1928 return ERROR_OK;
1929 }
1930
1931 COMMAND_HANDLER(dap_memaccess_command)
1932 {
1933 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1934 uint32_t memaccess_tck;
1935
1936 switch (CMD_ARGC) {
1937 case 0:
1938 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1939 break;
1940 case 1:
1941 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1942 break;
1943 default:
1944 return ERROR_COMMAND_SYNTAX_ERROR;
1945 }
1946 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1947
1948 command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
1949 dap->ap[dap->apsel].memaccess_tck);
1950
1951 return ERROR_OK;
1952 }
1953
1954 COMMAND_HANDLER(dap_apsel_command)
1955 {
1956 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1957 uint32_t apsel;
1958
1959 switch (CMD_ARGC) {
1960 case 0:
1961 command_print(CMD, "%" PRIu32, dap->apsel);
1962 return ERROR_OK;
1963 case 1:
1964 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1965 /* AP address is in bits 31:24 of DP_SELECT */
1966 if (apsel > DP_APSEL_MAX) {
1967 command_print(CMD, "Invalid AP number");
1968 return ERROR_COMMAND_ARGUMENT_INVALID;
1969 }
1970 break;
1971 default:
1972 return ERROR_COMMAND_SYNTAX_ERROR;
1973 }
1974
1975 dap->apsel = apsel;
1976 return ERROR_OK;
1977 }
1978
1979 COMMAND_HANDLER(dap_apcsw_command)
1980 {
1981 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1982 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1983 uint32_t csw_val, csw_mask;
1984
1985 switch (CMD_ARGC) {
1986 case 0:
1987 command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
1988 dap->apsel, apcsw);
1989 return ERROR_OK;
1990 case 1:
1991 if (strcmp(CMD_ARGV[0], "default") == 0)
1992 csw_val = CSW_AHB_DEFAULT;
1993 else
1994 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1995
1996 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1997 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1998 return ERROR_COMMAND_ARGUMENT_INVALID;
1999 }
2000 apcsw = csw_val;
2001 break;
2002 case 2:
2003 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
2004 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
2005 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
2006 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2007 return ERROR_COMMAND_ARGUMENT_INVALID;
2008 }
2009 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
2010 break;
2011 default:
2012 return ERROR_COMMAND_SYNTAX_ERROR;
2013 }
2014 dap->ap[dap->apsel].csw_default = apcsw;
2015
2016 return 0;
2017 }
2018
2019
2020
2021 COMMAND_HANDLER(dap_apid_command)
2022 {
2023 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2024 uint32_t apsel, apid;
2025 int retval;
2026
2027 switch (CMD_ARGC) {
2028 case 0:
2029 apsel = dap->apsel;
2030 break;
2031 case 1:
2032 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
2033 /* AP address is in bits 31:24 of DP_SELECT */
2034 if (apsel > DP_APSEL_MAX) {
2035 command_print(CMD, "Invalid AP number");
2036 return ERROR_COMMAND_ARGUMENT_INVALID;
2037 }
2038 break;
2039 default:
2040 return ERROR_COMMAND_SYNTAX_ERROR;
2041 }
2042
2043 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
2044 if (retval != ERROR_OK)
2045 return retval;
2046 retval = dap_run(dap);
2047 if (retval != ERROR_OK)
2048 return retval;
2049
2050 command_print(CMD, "0x%8.8" PRIx32, apid);
2051
2052 return retval;
2053 }
2054
2055 COMMAND_HANDLER(dap_apreg_command)
2056 {
2057 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2058 uint32_t apsel, reg, value;
2059 struct adiv5_ap *ap;
2060 int retval;
2061
2062 if (CMD_ARGC < 2 || CMD_ARGC > 3)
2063 return ERROR_COMMAND_SYNTAX_ERROR;
2064
2065 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
2066 /* AP address is in bits 31:24 of DP_SELECT */
2067 if (apsel > DP_APSEL_MAX) {
2068 command_print(CMD, "Invalid AP number");
2069 return ERROR_COMMAND_ARGUMENT_INVALID;
2070 }
2071
2072 ap = dap_ap(dap, apsel);
2073
2074 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
2075 if (reg >= 256 || (reg & 3)) {
2076 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2077 return ERROR_COMMAND_ARGUMENT_INVALID;
2078 }
2079
2080 if (CMD_ARGC == 3) {
2081 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2082 switch (reg) {
2083 case MEM_AP_REG_CSW:
2084 ap->csw_value = 0; /* invalid, in case write fails */
2085 retval = dap_queue_ap_write(ap, reg, value);
2086 if (retval == ERROR_OK)
2087 ap->csw_value = value;
2088 break;
2089 case MEM_AP_REG_TAR:
2090 retval = dap_queue_ap_write(ap, reg, value);
2091 if (retval == ERROR_OK)
2092 ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
2093 else {
2094 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2095 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2096 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2097 /* if tar_valid is false. */
2098 ap->tar_valid = false;
2099 }
2100 break;
2101 case MEM_AP_REG_TAR64:
2102 retval = dap_queue_ap_write(ap, reg, value);
2103 if (retval == ERROR_OK)
2104 ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
2105 else {
2106 /* See above comment for the MEM_AP_REG_TAR failed write case */
2107 ap->tar_valid = false;
2108 }
2109 break;
2110 default:
2111 retval = dap_queue_ap_write(ap, reg, value);
2112 break;
2113 }
2114 } else {
2115 retval = dap_queue_ap_read(ap, reg, &value);
2116 }
2117 if (retval == ERROR_OK)
2118 retval = dap_run(dap);
2119
2120 if (retval != ERROR_OK)
2121 return retval;
2122
2123 if (CMD_ARGC == 2)
2124 command_print(CMD, "0x%08" PRIx32, value);
2125
2126 return retval;
2127 }
2128
2129 COMMAND_HANDLER(dap_dpreg_command)
2130 {
2131 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2132 uint32_t reg, value;
2133 int retval;
2134
2135 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2136 return ERROR_COMMAND_SYNTAX_ERROR;
2137
2138 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
2139 if (reg >= 256 || (reg & 3)) {
2140 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2141 return ERROR_COMMAND_ARGUMENT_INVALID;
2142 }
2143
2144 if (CMD_ARGC == 2) {
2145 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2146 retval = dap_queue_dp_write(dap, reg, value);
2147 } else {
2148 retval = dap_queue_dp_read(dap, reg, &value);
2149 }
2150 if (retval == ERROR_OK)
2151 retval = dap_run(dap);
2152
2153 if (retval != ERROR_OK)
2154 return retval;
2155
2156 if (CMD_ARGC == 1)
2157 command_print(CMD, "0x%08" PRIx32, value);
2158
2159 return retval;
2160 }
2161
2162 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
2163 {
2164 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
2165 return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
2166 "TI BE-32 quirks mode");
2167 }
2168
2169 const struct command_registration dap_instance_commands[] = {
2170 {
2171 .name = "info",
2172 .handler = handle_dap_info_command,
2173 .mode = COMMAND_EXEC,
2174 .help = "display ROM table for MEM-AP "
2175 "(default currently selected AP)",
2176 .usage = "[ap_num]",
2177 },
2178 {
2179 .name = "apsel",
2180 .handler = dap_apsel_command,
2181 .mode = COMMAND_ANY,
2182 .help = "Set the currently selected AP (default 0) "
2183 "and display the result",
2184 .usage = "[ap_num]",
2185 },
2186 {
2187 .name = "apcsw",
2188 .handler = dap_apcsw_command,
2189 .mode = COMMAND_ANY,
2190 .help = "Set CSW default bits",
2191 .usage = "[value [mask]]",
2192 },
2193
2194 {
2195 .name = "apid",
2196 .handler = dap_apid_command,
2197 .mode = COMMAND_EXEC,
2198 .help = "return ID register from AP "
2199 "(default currently selected AP)",
2200 .usage = "[ap_num]",
2201 },
2202 {
2203 .name = "apreg",
2204 .handler = dap_apreg_command,
2205 .mode = COMMAND_EXEC,
2206 .help = "read/write a register from AP "
2207 "(reg is byte address of a word register, like 0 4 8...)",
2208 .usage = "ap_num reg [value]",
2209 },
2210 {
2211 .name = "dpreg",
2212 .handler = dap_dpreg_command,
2213 .mode = COMMAND_EXEC,
2214 .help = "read/write a register from DP "
2215 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2216 .usage = "reg [value]",
2217 },
2218 {
2219 .name = "baseaddr",
2220 .handler = dap_baseaddr_command,
2221 .mode = COMMAND_EXEC,
2222 .help = "return debug base address from MEM-AP "
2223 "(default currently selected AP)",
2224 .usage = "[ap_num]",
2225 },
2226 {
2227 .name = "memaccess",
2228 .handler = dap_memaccess_command,
2229 .mode = COMMAND_EXEC,
2230 .help = "set/get number of extra tck for MEM-AP memory "
2231 "bus access [0-255]",
2232 .usage = "[cycles]",
2233 },
2234 {
2235 .name = "ti_be_32_quirks",
2236 .handler = dap_ti_be_32_quirks_command,
2237 .mode = COMMAND_CONFIG,
2238 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
2239 .usage = "[enable]",
2240 },
2241 COMMAND_REGISTRATION_DONE
2242 };
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