1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "arm_adi_v5.h"
73 #include <helper/time_support.h>
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
84 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
87 /***************************************************************************
89 * DPACC and APACC scanchain access through JTAG-DP *
91 ***************************************************************************/
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
111 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
112 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
113 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
115 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
116 struct scan_field fields
[2];
117 uint8_t out_addr_buf
;
119 jtag_set_end_state(TAP_IDLE
);
120 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
122 /* Scan out a read or write operation using some DP or AP register.
123 * For APACC access with any sticky error flag set, this is discarded.
125 fields
[0].tap
= jtag_info
->tap
;
126 fields
[0].num_bits
= 3;
127 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
128 fields
[0].out_value
= &out_addr_buf
;
129 fields
[0].in_value
= ack
;
131 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
132 * complete; data we write is discarded, data we read is unpredictable.
133 * When overrun detect is active, STICKYORUN is set.
136 fields
[1].tap
= jtag_info
->tap
;
137 fields
[1].num_bits
= 32;
138 fields
[1].out_value
= outvalue
;
139 fields
[1].in_value
= invalue
;
141 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
143 /* Add specified number of tck clocks after starting memory bus
144 * access, giving the hardware time to complete the access.
145 * They provide more time for the (MEM) AP to complete the read ...
146 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
148 if ((instr
== JTAG_DP_APACC
)
149 && ((reg_addr
== AP_REG_DRW
)
150 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
151 && (swjdp
->memaccess_tck
!= 0))
152 jtag_add_runtest(swjdp
->memaccess_tck
,
153 jtag_set_end_state(TAP_IDLE
));
155 return jtag_get_error();
159 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
160 * This is exactly like adi_jtag_dp_scan(), except that endianness
161 * conversions are performed (so the types of invalue and outvalue
162 * must be different).
164 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
165 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
166 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
168 uint8_t out_value_buf
[4];
171 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
173 retval
= adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
,
174 out_value_buf
, (uint8_t *)invalue
, ack
);
175 if (retval
!= ERROR_OK
)
179 jtag_add_callback(arm_le_to_h_u32
,
180 (jtag_callback_data_t
) invalue
);
186 * Utility to write AP registers.
188 static inline int adi_jtag_ap_write_check(struct swjdp_common
*dap
,
189 uint8_t reg_addr
, uint8_t *outvalue
)
191 return adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg_addr
, DPAP_WRITE
,
192 outvalue
, NULL
, NULL
);
195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common
*swjdp
,
196 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
197 uint32_t outvalue
, uint32_t *invalue
)
201 /* Issue the read or write */
202 retval
= adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
,
203 RnW
, outvalue
, NULL
, NULL
);
204 if (retval
!= ERROR_OK
)
207 /* For reads, collect posted value; RDBUFF has no other effect.
208 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
210 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
211 retval
= adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
212 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
216 static int jtagdp_transaction_endcheck(struct swjdp_common
*swjdp
)
221 /* too expensive to call keep_alive() here */
224 /* Danger!!!! BROKEN!!!! */
225 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
226 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
227 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
228 R956 introduced the check on return value here and now Michael Schwingen reports
229 that this code no longer works....
231 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
233 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
235 LOG_ERROR("BUG: Why does this fail the first time????");
237 /* Why??? second time it works??? */
240 /* Post CTRL/STAT read; discard any previous posted read value
241 * but collect its ACK status.
243 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
244 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
245 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
248 swjdp
->ack
= swjdp
->ack
& 0x7;
250 /* common code path avoids calling timeval_ms() */
251 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
253 long long then
= timeval_ms();
255 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
257 if (swjdp
->ack
== JTAG_ACK_WAIT
)
259 if ((timeval_ms()-then
) > 1000)
261 /* NOTE: this would be a good spot
262 * to use JTAG_DP_ABORT.
264 LOG_WARNING("Timeout (1000ms) waiting "
266 "in JTAG-DP transaction");
267 return ERROR_JTAG_DEVICE_ERROR
;
272 LOG_WARNING("Invalid ACK %#x "
273 "in JTAG-DP transaction",
275 return ERROR_JTAG_DEVICE_ERROR
;
278 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
279 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
280 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
282 swjdp
->ack
= swjdp
->ack
& 0x7;
286 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
288 /* Check for STICKYERR and STICKYORUN */
289 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
291 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
292 /* Check power to debug regions */
293 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp
);
297 uint32_t mem_ap_csw
, mem_ap_tar
;
299 /* Maybe print information about last intended
300 * MEM-AP access; but not if autoincrementing.
301 * *Real* CSW and TAR values are always shown.
303 if (swjdp
->ap_tar_value
!= (uint32_t) -1)
304 LOG_DEBUG("MEM-AP Cached values: "
306 ", ap_csw 0x%" PRIx32
307 ", ap_tar 0x%" PRIx32
,
308 swjdp
->ap_bank_value
,
310 swjdp
->ap_tar_value
);
312 if (ctrlstat
& SSTICKYORUN
)
313 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
314 "memaccess, or reduce jtag speed");
316 if (ctrlstat
& SSTICKYERR
)
317 LOG_ERROR("JTAG-DP STICKY ERROR");
319 /* Clear Sticky Error Bits */
320 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
321 DP_CTRL_STAT
, DPAP_WRITE
,
322 swjdp
->dp_ctrl_stat
| SSTICKYORUN
324 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
325 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
326 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
329 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
331 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
332 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
333 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
335 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
336 PRIx32
, mem_ap_csw
, mem_ap_tar
);
339 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
341 return ERROR_JTAG_DEVICE_ERROR
;
347 /***************************************************************************
349 * DP and MEM-AP register access through APACC and DPACC *
351 ***************************************************************************/
354 * Select one of the APs connected to the specified DAP. The
355 * selection is implicitly used with future AP transactions.
356 * This is a NOP if the specified AP is already selected.
358 * @param swjdp The DAP
359 * @param apsel Number of the AP to (implicitly) use with further
360 * transactions. This normally identifies a MEM-AP.
362 void dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
364 uint32_t select
= (apsel
<< 24) & 0xFF000000;
366 if (select
!= swjdp
->apsel
)
368 swjdp
->apsel
= select
;
369 /* Switching AP invalidates cached values.
370 * Values MUST BE UPDATED BEFORE AP ACCESS.
372 swjdp
->ap_bank_value
= -1;
373 swjdp
->ap_csw_value
= -1;
374 swjdp
->ap_tar_value
= -1;
378 /** Select the AP register bank matching bits 7:4 of ap_reg. */
379 static int dap_ap_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
381 uint32_t select
= (ap_reg
& 0x000000F0);
383 if (select
!= swjdp
->ap_bank_value
)
385 swjdp
->ap_bank_value
= select
;
386 select
|= swjdp
->apsel
;
387 return dap_queue_dp_write(swjdp
, DP_SELECT
, select
);
392 /* FIXME remove dap_ap_{read,write}_reg() and dap_ap_write_reg_u32()
393 * ... these should become the bodies of the JTAG implementations of
394 * dap_queue_ap_{read,write}(), then all their current callers should
395 * switch over to the transport-neutral calls.
398 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
399 uint32_t reg_addr
, uint8_t *out_value_buf
)
403 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
404 if (retval
!= ERROR_OK
)
407 return adi_jtag_ap_write_check(swjdp
, reg_addr
, out_value_buf
);
411 * Asynchronous (queued) AP register write.
413 * @param swjdp The DAP whose currently selected AP will be written.
414 * @param reg_addr Eight bit AP register address.
415 * @param value Word to be written at reg_addr
417 * @return ERROR_OK if the transaction was properly queued, else a fault code.
419 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
,
420 uint32_t reg_addr
, uint32_t value
)
422 uint8_t out_value_buf
[4];
424 buf_set_u32(out_value_buf
, 0, 32, value
);
425 return dap_ap_write_reg(swjdp
,
426 reg_addr
, out_value_buf
);
430 * Asynchronous (queued) AP register eread.
432 * @param swjdp The DAP whose currently selected AP will be read.
433 * @param reg_addr Eight bit AP register address.
434 * @param value Points to where the 32-bit (little-endian) word will be stored.
436 * @return ERROR_OK if the transaction was properly queued, else a fault code.
438 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
,
439 uint32_t reg_addr
, uint32_t *value
)
443 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
444 if (retval
!= ERROR_OK
)
447 return adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
448 DPAP_READ
, 0, value
);
452 * Queue transactions setting up transfer parameters for the
453 * currently selected MEM-AP.
455 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
456 * initiate data reads or writes using memory or peripheral addresses.
457 * If the CSW is configured for it, the TAR may be automatically
458 * incremented after each transfer.
460 * @todo Rename to reflect it being specifically a MEM-AP function.
462 * @param swjdp The DAP connected to the MEM-AP.
463 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
464 * matches the cached value, the register is not changed.
465 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
466 * matches the cached address, the register is not changed.
468 * @return ERROR_OK if the transaction was properly queued, else a fault code.
470 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
474 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
475 if (csw
!= swjdp
->ap_csw_value
)
477 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
478 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
479 if (retval
!= ERROR_OK
)
481 swjdp
->ap_csw_value
= csw
;
483 if (tar
!= swjdp
->ap_tar_value
)
485 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
486 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
487 if (retval
!= ERROR_OK
)
489 swjdp
->ap_tar_value
= tar
;
491 /* Disable TAR cache when autoincrementing */
492 if (csw
& CSW_ADDRINC_MASK
)
493 swjdp
->ap_tar_value
= -1;
498 * Asynchronous (queued) read of a word from memory or a system register.
500 * @param swjdp The DAP connected to the MEM-AP performing the read.
501 * @param address Address of the 32-bit word to read; it must be
502 * readable by the currently selected MEM-AP.
503 * @param value points to where the word will be stored when the
504 * transaction queue is flushed (assuming no errors).
506 * @return ERROR_OK for success. Otherwise a fault code.
508 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
,
513 /* Use banked addressing (REG_BDx) to avoid some link traffic
514 * (updating TAR) when reading several consecutive addresses.
516 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
517 address
& 0xFFFFFFF0);
518 if (retval
!= ERROR_OK
)
521 return dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
525 * Synchronous read of a word from memory or a system register.
526 * As a side effect, this flushes any queued transactions.
528 * @param swjdp The DAP connected to the MEM-AP performing the read.
529 * @param address Address of the 32-bit word to read; it must be
530 * readable by the currently selected MEM-AP.
531 * @param value points to where the result will be stored.
533 * @return ERROR_OK for success; *value holds the result.
534 * Otherwise a fault code.
536 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
541 retval
= mem_ap_read_u32(swjdp
, address
, value
);
542 if (retval
!= ERROR_OK
)
545 return dap_run(swjdp
);
549 * Asynchronous (queued) write of a word to memory or a system register.
551 * @param swjdp The DAP connected to the MEM-AP.
552 * @param address Address to be written; it must be writable by
553 * the currently selected MEM-AP.
554 * @param value Word that will be written to the address when transaction
555 * queue is flushed (assuming no errors).
557 * @return ERROR_OK for success. Otherwise a fault code.
559 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
,
564 /* Use banked addressing (REG_BDx) to avoid some link traffic
565 * (updating TAR) when writing several consecutive addresses.
567 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
568 address
& 0xFFFFFFF0);
569 if (retval
!= ERROR_OK
)
572 return dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC),
577 * Synchronous write of a word to memory or a system register.
578 * As a side effect, this flushes any queued transactions.
580 * @param swjdp The DAP connected to the MEM-AP.
581 * @param address Address to be written; it must be writable by
582 * the currently selected MEM-AP.
583 * @param value Word that will be written.
585 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
587 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
590 int retval
= mem_ap_write_u32(swjdp
, address
, value
);
592 if (retval
!= ERROR_OK
)
595 return dap_run(swjdp
);
598 /*****************************************************************************
600 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
602 * Write a buffer in target order (little endian) *
604 *****************************************************************************/
605 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
607 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
608 uint32_t adr
= address
;
609 uint8_t* pBuffer
= buffer
;
614 /* if we have an unaligned access - reorder data */
617 for (writecount
= 0; writecount
< count
; writecount
++)
621 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
623 for (i
= 0; i
< 4; i
++)
625 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
629 pBuffer
+= sizeof(uint32_t);
635 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
636 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
637 if (wcount
< blocksize
)
640 /* handle unaligned data at 4k boundary */
644 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
646 for (writecount
= 0; writecount
< blocksize
; writecount
++)
648 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
651 if (dap_run(swjdp
) == ERROR_OK
)
653 wcount
= wcount
- blocksize
;
654 address
= address
+ 4 * blocksize
;
655 buffer
= buffer
+ 4 * blocksize
;
664 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
665 /* REVISIT return the *actual* fault code */
666 return ERROR_JTAG_DEVICE_ERROR
;
673 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
674 uint8_t *buffer
, int count
, uint32_t address
)
676 int retval
= ERROR_OK
;
677 int wcount
, blocksize
, writecount
, i
;
685 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
686 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
688 if (wcount
< blocksize
)
691 /* handle unaligned data at 4k boundary */
695 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
696 writecount
= blocksize
;
700 nbytes
= MIN((writecount
<< 1), 4);
704 if (mem_ap_write_buf_u16(swjdp
, buffer
,
705 nbytes
, address
) != ERROR_OK
)
707 LOG_WARNING("Block write error address "
708 "0x%" PRIx32
", count 0x%x",
710 return ERROR_JTAG_DEVICE_ERROR
;
713 address
+= nbytes
>> 1;
718 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
720 for (i
= 0; i
< nbytes
; i
++)
722 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
727 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
728 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
729 if (dap_run(swjdp
) != ERROR_OK
)
731 LOG_WARNING("Block write error address "
732 "0x%" PRIx32
", count 0x%x",
734 /* REVISIT return *actual* fault code */
735 return ERROR_JTAG_DEVICE_ERROR
;
739 buffer
+= nbytes
>> 1;
740 writecount
-= nbytes
>> 1;
742 } while (writecount
);
749 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
751 int retval
= ERROR_OK
;
754 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
758 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
760 memcpy(&svalue
, buffer
, sizeof(uint16_t));
761 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
762 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
763 retval
= dap_run(swjdp
);
764 if (retval
!= ERROR_OK
)
775 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
776 uint8_t *buffer
, int count
, uint32_t address
)
778 int retval
= ERROR_OK
;
779 int wcount
, blocksize
, writecount
, i
;
787 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
788 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
790 if (wcount
< blocksize
)
793 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
794 writecount
= blocksize
;
798 nbytes
= MIN(writecount
, 4);
802 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
804 LOG_WARNING("Block write error address "
805 "0x%" PRIx32
", count 0x%x",
807 return ERROR_JTAG_DEVICE_ERROR
;
815 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
817 for (i
= 0; i
< nbytes
; i
++)
819 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
824 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
825 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
826 if (dap_run(swjdp
) != ERROR_OK
)
828 LOG_WARNING("Block write error address "
829 "0x%" PRIx32
", count 0x%x",
831 /* REVISIT return *actual* fault code */
832 return ERROR_JTAG_DEVICE_ERROR
;
837 writecount
-= nbytes
;
839 } while (writecount
);
846 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
848 int retval
= ERROR_OK
;
851 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
855 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
856 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
857 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
858 retval
= dap_run(swjdp
);
859 if (retval
!= ERROR_OK
)
871 * Synchronously read a block of 32-bit words into a buffer
872 * @param swjdp The DAP connected to the MEM-AP.
873 * @param buffer where the words will be stored (in host byte order).
874 * @param count How many words to read.
875 * @param address Memory address from which to read words; all the
876 * words must be readable by the currently selected MEM-AP.
878 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
,
879 int count
, uint32_t address
)
881 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
882 uint32_t adr
= address
;
883 uint8_t* pBuffer
= buffer
;
890 /* Adjust to read blocks within boundaries aligned to the
891 * TAR autoincrement size (at least 2^10). Autoincrement
892 * mode avoids an extra per-word roundtrip to update TAR.
894 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
,
896 if (wcount
< blocksize
)
899 /* handle unaligned data at 4k boundary */
903 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
906 /* Scan out first read */
907 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
908 DPAP_READ
, 0, NULL
, NULL
);
909 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
911 /* Scan out next read; scan in posted value for the
912 * previous one. Assumes read is acked "OK/FAULT",
913 * and CTRL_STAT says that meant "OK".
915 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
916 DPAP_READ
, 0, buffer
+ 4 * readcount
,
920 /* Scan in last posted value; RDBUFF has no other effect,
921 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
923 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
924 DPAP_READ
, 0, buffer
+ 4 * readcount
,
926 if (dap_run(swjdp
) == ERROR_OK
)
928 wcount
= wcount
- blocksize
;
929 address
+= 4 * blocksize
;
930 buffer
+= 4 * blocksize
;
939 LOG_WARNING("Block read error address 0x%" PRIx32
940 ", count 0x%x", address
, count
);
941 /* REVISIT return the *actual* fault code */
942 return ERROR_JTAG_DEVICE_ERROR
;
946 /* if we have an unaligned access - reorder data */
949 for (readcount
= 0; readcount
< count
; readcount
++)
953 memcpy(&data
, pBuffer
, sizeof(uint32_t));
955 for (i
= 0; i
< 4; i
++)
957 *((uint8_t*)pBuffer
) =
958 (data
>> 8 * (adr
& 0x3));
968 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
969 uint8_t *buffer
, int count
, uint32_t address
)
972 int retval
= ERROR_OK
;
973 int wcount
, blocksize
, readcount
, i
;
981 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
982 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
983 if (wcount
< blocksize
)
986 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
988 /* handle unaligned data at 4k boundary */
991 readcount
= blocksize
;
995 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
996 if (dap_run(swjdp
) != ERROR_OK
)
998 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
999 /* REVISIT return the *actual* fault code */
1000 return ERROR_JTAG_DEVICE_ERROR
;
1003 nbytes
= MIN((readcount
<< 1), 4);
1005 for (i
= 0; i
< nbytes
; i
++)
1007 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1012 readcount
-= (nbytes
>> 1);
1013 } while (readcount
);
1014 wcount
-= blocksize
;
1021 * Synchronously read a block of 16-bit halfwords into a buffer
1022 * @param swjdp The DAP connected to the MEM-AP.
1023 * @param buffer where the halfwords will be stored (in host byte order).
1024 * @param count How many halfwords to read.
1025 * @param address Memory address from which to read words; all the
1026 * words must be readable by the currently selected MEM-AP.
1028 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
,
1029 int count
, uint32_t address
)
1031 uint32_t invalue
, i
;
1032 int retval
= ERROR_OK
;
1035 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
1039 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
1040 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1041 retval
= dap_run(swjdp
);
1042 if (retval
!= ERROR_OK
)
1047 for (i
= 0; i
< 2; i
++)
1049 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1056 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
1057 memcpy(buffer
, &svalue
, sizeof(uint16_t));
1067 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1068 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1070 * The solution is to arrange for a large out/in scan in this loop and
1071 * and convert data afterwards.
1073 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
1074 uint8_t *buffer
, int count
, uint32_t address
)
1077 int retval
= ERROR_OK
;
1078 int wcount
, blocksize
, readcount
, i
;
1086 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1087 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1089 if (wcount
< blocksize
)
1092 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
1093 readcount
= blocksize
;
1097 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1098 if (dap_run(swjdp
) != ERROR_OK
)
1100 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1101 /* REVISIT return the *actual* fault code */
1102 return ERROR_JTAG_DEVICE_ERROR
;
1105 nbytes
= MIN(readcount
, 4);
1107 for (i
= 0; i
< nbytes
; i
++)
1109 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1114 readcount
-= nbytes
;
1115 } while (readcount
);
1116 wcount
-= blocksize
;
1123 * Synchronously read a block of bytes into a buffer
1124 * @param swjdp The DAP connected to the MEM-AP.
1125 * @param buffer where the bytes will be stored.
1126 * @param count How many bytes to read.
1127 * @param address Memory address from which to read data; all the
1128 * data must be readable by the currently selected MEM-AP.
1130 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
,
1131 int count
, uint32_t address
)
1134 int retval
= ERROR_OK
;
1137 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1141 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1142 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1143 retval
= dap_run(swjdp
);
1144 if (retval
!= ERROR_OK
)
1147 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1156 /*--------------------------------------------------------------------------*/
1158 static int jtag_idcode_q_read(struct swjdp_common
*dap
,
1159 uint8_t *ack
, uint32_t *data
)
1161 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
1163 struct scan_field fields
[1];
1165 jtag_set_end_state(TAP_IDLE
);
1167 /* This is a standard JTAG operation -- no DAP tweakage */
1168 retval
= arm_jtag_set_instr(jtag_info
, JTAG_DP_IDCODE
, NULL
);
1169 if (retval
!= ERROR_OK
)
1172 fields
[0].tap
= jtag_info
->tap
;
1173 fields
[0].num_bits
= 32;
1174 fields
[0].out_value
= NULL
;
1175 fields
[0].in_value
= (void *) data
;
1177 jtag_add_dr_scan(1, fields
, jtag_get_end_state());
1178 retval
= jtag_get_error();
1179 if (retval
!= ERROR_OK
)
1182 jtag_add_callback(arm_le_to_h_u32
,
1183 (jtag_callback_data_t
) data
);
1188 static int jtag_dp_q_read(struct swjdp_common
*dap
, unsigned reg
,
1191 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
1192 reg
, DPAP_READ
, 0, data
);
1195 static int jtag_dp_q_write(struct swjdp_common
*dap
, unsigned reg
,
1198 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
1199 reg
, DPAP_WRITE
, data
, NULL
);
1202 static int jtag_ap_q_bankselect(struct swjdp_common
*dap
, unsigned reg
)
1204 uint32_t select
= reg
& 0x000000F0;
1206 if (select
== dap
->ap_bank_value
)
1208 dap
->ap_bank_value
= select
;
1210 select
|= dap
->apsel
;
1212 return jtag_dp_q_write(dap
, DP_SELECT
, select
);
1215 static int jtag_ap_q_read(struct swjdp_common
*dap
, unsigned reg
,
1218 int retval
= jtag_ap_q_bankselect(dap
, reg
);
1220 if (retval
!= ERROR_OK
)
1222 return dap_ap_read_reg_u32(dap
, reg
, data
);
1225 static int jtag_ap_q_write(struct swjdp_common
*dap
, unsigned reg
,
1228 int retval
= jtag_ap_q_bankselect(dap
, reg
);
1230 if (retval
!= ERROR_OK
)
1232 return dap_ap_write_reg_u32(dap
, reg
, data
);
1235 static int jtag_ap_q_abort(struct swjdp_common
*dap
, uint8_t *ack
)
1237 /* for JTAG, this is the only valid ABORT register operation */
1238 return adi_jtag_dp_scan_u32(dap
, JTAG_DP_ABORT
,
1239 0, DPAP_WRITE
, 1, NULL
, ack
);
1242 static int jtag_dp_run(struct swjdp_common
*dap
)
1244 return jtagdp_transaction_endcheck(dap
);
1247 static const struct dap_ops jtag_dp_ops
= {
1248 .queue_idcode_read
= jtag_idcode_q_read
,
1249 .queue_dp_read
= jtag_dp_q_read
,
1250 .queue_dp_write
= jtag_dp_q_write
,
1251 .queue_ap_read
= jtag_ap_q_read
,
1252 .queue_ap_write
= jtag_ap_q_write
,
1253 .queue_ap_abort
= jtag_ap_q_abort
,
1257 /*--------------------------------------------------------------------------*/
1260 * Initialize a DAP. This sets up the power domains, prepares the DP
1261 * for further use, and arranges to use AP #0 for all AP operations
1262 * until dap_ap-select() changes that policy.
1264 * @param swjdp The DAP being initialized.
1266 * @todo Rename this. We also need an initialization scheme which account
1267 * for SWD transports not just JTAG; that will need to address differences
1268 * in layering. (JTAG is useful without any debug target; but not SWD.)
1269 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1271 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1273 uint32_t idreg
, romaddr
, dummy
;
1280 /* JTAG-DP or SWJ-DP, in JTAG mode */
1281 swjdp
->ops
= &jtag_dp_ops
;
1283 /* Default MEM-AP setup.
1285 * REVISIT AP #0 may be an inappropriate default for this.
1286 * Should we probe, or take a hint from the caller?
1287 * Presumably we can ignore the possibility of multiple APs.
1290 dap_ap_select(swjdp
, 0);
1292 /* DP initialization */
1294 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &dummy
);
1295 if (retval
!= ERROR_OK
)
1298 retval
= dap_queue_dp_write(swjdp
, DP_CTRL_STAT
, SSTICKYERR
);
1299 if (retval
!= ERROR_OK
)
1302 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &dummy
);
1303 if (retval
!= ERROR_OK
)
1306 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1307 retval
= dap_queue_dp_write(swjdp
, DP_CTRL_STAT
, swjdp
->dp_ctrl_stat
);
1308 if (retval
!= ERROR_OK
)
1311 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &ctrlstat
);
1312 if (retval
!= ERROR_OK
)
1314 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1317 /* Check that we have debug power domains activated */
1318 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1320 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1321 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &ctrlstat
);
1322 if (retval
!= ERROR_OK
)
1324 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1329 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1331 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1332 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &ctrlstat
);
1333 if (retval
!= ERROR_OK
)
1335 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1340 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &dummy
);
1341 if (retval
!= ERROR_OK
)
1343 /* With debug power on we can activate OVERRUN checking */
1344 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1345 retval
= dap_queue_dp_write(swjdp
, DP_CTRL_STAT
, swjdp
->dp_ctrl_stat
);
1346 if (retval
!= ERROR_OK
)
1348 retval
= dap_queue_dp_read(swjdp
, DP_CTRL_STAT
, &dummy
);
1349 if (retval
!= ERROR_OK
)
1353 * REVISIT this isn't actually *initializing* anything in an AP,
1354 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1355 * Should it? If the ROM address is valid, is this the right
1356 * place to scan the table and do any topology detection?
1358 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1359 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1361 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1362 ", Debug ROM Address 0x%" PRIx32
,
1363 swjdp
->apsel
, idreg
, romaddr
);
1368 /* CID interpretation -- see ARM IHI 0029B section 3
1369 * and ARM IHI 0031A table 13-3.
1371 static const char *class_description
[16] ={
1372 "Reserved", "ROM table", "Reserved", "Reserved",
1373 "Reserved", "Reserved", "Reserved", "Reserved",
1374 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1375 "Reserved", "OptimoDE DESS",
1376 "Generic IP component", "PrimeCell or System component"
1380 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1382 return cid3
== 0xb1 && cid2
== 0x05
1383 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1386 int dap_info_command(struct command_context
*cmd_ctx
,
1387 struct swjdp_common
*swjdp
, int apsel
)
1390 uint32_t dbgbase
, apid
;
1391 int romtable_present
= 0;
1395 /* AP address is in bits 31:24 of DP_SELECT */
1397 return ERROR_INVALID_ARGUMENTS
;
1399 apselold
= swjdp
->apsel
;
1400 dap_ap_select(swjdp
, apsel
);
1401 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1402 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1403 retval
= dap_run(swjdp
);
1404 if (retval
!= ERROR_OK
)
1407 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1408 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1409 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1415 command_print(cmd_ctx
, "\tType is JTAG-AP");
1418 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1421 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1424 command_print(cmd_ctx
, "\tUnknown AP type");
1428 /* NOTE: a MEM-AP may have a single CoreSight component that's
1429 * not a ROM table ... or have no such components at all.
1432 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1437 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1440 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1441 if (romtable_present
)
1443 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1444 uint16_t entry_offset
;
1446 /* bit 16 of apid indicates a memory access port */
1448 command_print(cmd_ctx
, "\tValid ROM table present");
1450 command_print(cmd_ctx
, "\tROM table in legacy format");
1452 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1453 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1454 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1455 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1456 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1457 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1458 retval
= dap_run(swjdp
);
1459 if (retval
!= ERROR_OK
)
1462 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1463 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1464 ", CID2 0x%2.2" PRIx32
1465 ", CID1 0x%2.2" PRIx32
1466 ", CID0 0x%2.2" PRIx32
,
1467 cid3
, cid2
, cid1
, cid0
);
1469 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1471 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1472 "Dedicated debug bus.");
1474 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1478 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1479 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1482 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1483 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1484 uint32_t component_start
, component_base
;
1488 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1489 + (int)(romentry
& 0xFFFFF000));
1490 mem_ap_read_atomic_u32(swjdp
,
1491 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1492 mem_ap_read_atomic_u32(swjdp
,
1493 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1494 mem_ap_read_atomic_u32(swjdp
,
1495 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1496 mem_ap_read_atomic_u32(swjdp
,
1497 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1498 mem_ap_read_atomic_u32(swjdp
,
1499 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1500 mem_ap_read_atomic_u32(swjdp
,
1501 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1502 mem_ap_read_atomic_u32(swjdp
,
1503 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1504 mem_ap_read_atomic_u32(swjdp
,
1505 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1506 mem_ap_read_atomic_u32(swjdp
,
1507 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1508 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1510 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1511 ", start address 0x%" PRIx32
,
1512 component_base
, component_start
);
1513 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1514 (int) (c_cid1
>> 4) & 0xf,
1515 /* See ARM IHI 0029B Table 3-3 */
1516 class_description
[(c_cid1
>> 4) & 0xf]);
1518 /* CoreSight component? */
1519 if (((c_cid1
>> 4) & 0x0f) == 9) {
1522 char *major
= "Reserved", *subtype
= "Reserved";
1524 mem_ap_read_atomic_u32(swjdp
,
1525 (component_base
& 0xfffff000) | 0xfcc,
1527 minor
= (devtype
>> 4) & 0x0f;
1528 switch (devtype
& 0x0f) {
1530 major
= "Miscellaneous";
1536 subtype
= "Validation component";
1541 major
= "Trace Sink";
1555 major
= "Trace Link";
1561 subtype
= "Funnel, router";
1567 subtype
= "FIFO, buffer";
1572 major
= "Trace Source";
1578 subtype
= "Processor";
1584 subtype
= "Engine/Coprocessor";
1592 major
= "Debug Control";
1598 subtype
= "Trigger Matrix";
1601 subtype
= "Debug Auth";
1606 major
= "Debug Logic";
1612 subtype
= "Processor";
1618 subtype
= "Engine/Coprocessor";
1623 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1624 (unsigned) (devtype
& 0xff),
1626 /* REVISIT also show 0xfc8 DevId */
1629 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1630 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1631 ", CID2 0x%2.2" PRIx32
1632 ", CID1 0x%2.2" PRIx32
1633 ", CID0 0x%2.2" PRIx32
,
1634 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1635 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1636 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1638 (int) c_pid3
, (int) c_pid2
,
1639 (int) c_pid1
, (int) c_pid0
);
1641 /* Part number interpretations are from Cortex
1642 * core specs, the CoreSight components TRM
1643 * (ARM DDI 0314H), and ETM specs; also from
1644 * chip observation (e.g. TI SDTI).
1646 part_num
= c_pid0
& 0xff;
1647 part_num
|= (c_pid1
& 0x0f) << 8;
1650 type
= "Cortex-M3 NVIC";
1651 full
= "(Interrupt Controller)";
1654 type
= "Cortex-M3 ITM";
1655 full
= "(Instrumentation Trace Module)";
1658 type
= "Cortex-M3 DWT";
1659 full
= "(Data Watchpoint and Trace)";
1662 type
= "Cortex-M3 FBP";
1663 full
= "(Flash Patch and Breakpoint)";
1666 type
= "CoreSight ETM11";
1667 full
= "(Embedded Trace)";
1669 // case 0x113: what?
1670 case 0x120: /* from OMAP3 memmap */
1672 full
= "(System Debug Trace Interface)";
1674 case 0x343: /* from OMAP3 memmap */
1679 type
= "Coresight CTI";
1680 full
= "(Cross Trigger)";
1683 type
= "Coresight ETB";
1684 full
= "(Trace Buffer)";
1687 type
= "Coresight CSTF";
1688 full
= "(Trace Funnel)";
1691 type
= "CoreSight ETM9";
1692 full
= "(Embedded Trace)";
1695 type
= "Coresight TPIU";
1696 full
= "(Trace Port Interface Unit)";
1699 type
= "Cortex-A8 ETM";
1700 full
= "(Embedded Trace)";
1703 type
= "Cortex-A8 CTI";
1704 full
= "(Cross Trigger)";
1707 type
= "Cortex-M3 TPIU";
1708 full
= "(Trace Port Interface Unit)";
1711 type
= "Cortex-M3 ETM";
1712 full
= "(Embedded Trace)";
1715 type
= "Cortex-A8 Debug";
1716 full
= "(Debug Unit)";
1719 type
= "-*- unrecognized -*-";
1723 command_print(cmd_ctx
, "\t\tPart is %s %s",
1729 command_print(cmd_ctx
, "\t\tComponent not present");
1731 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1734 } while (romentry
> 0);
1738 command_print(cmd_ctx
, "\tNo ROM table present");
1740 dap_ap_select(swjdp
, apselold
);
1745 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1747 uint32_t apsel
, apselsave
, baseaddr
;
1750 apselsave
= swjdp
->apsel
;
1753 apsel
= swjdp
->apsel
;
1756 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1757 /* AP address is in bits 31:24 of DP_SELECT */
1759 return ERROR_INVALID_ARGUMENTS
;
1762 return ERROR_COMMAND_SYNTAX_ERROR
;
1765 if (apselsave
!= apsel
)
1766 dap_ap_select(swjdp
, apsel
);
1768 /* NOTE: assumes we're talking to a MEM-AP, which
1769 * has a base address. There are other kinds of AP,
1770 * though they're not common for now. This should
1771 * use the ID register to verify it's a MEM-AP.
1773 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1774 retval
= dap_run(swjdp
);
1775 if (retval
!= ERROR_OK
)
1778 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1780 if (apselsave
!= apsel
)
1781 dap_ap_select(swjdp
, apselsave
);
1786 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1788 uint32_t memaccess_tck
;
1792 memaccess_tck
= swjdp
->memaccess_tck
;
1795 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1798 return ERROR_COMMAND_SYNTAX_ERROR
;
1800 swjdp
->memaccess_tck
= memaccess_tck
;
1802 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1803 swjdp
->memaccess_tck
);
1808 DAP_COMMAND_HANDLER(dap_apsel_command
)
1810 uint32_t apsel
, apid
;
1818 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1819 /* AP address is in bits 31:24 of DP_SELECT */
1821 return ERROR_INVALID_ARGUMENTS
;
1824 return ERROR_COMMAND_SYNTAX_ERROR
;
1827 dap_ap_select(swjdp
, apsel
);
1828 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1829 retval
= dap_run(swjdp
);
1830 if (retval
!= ERROR_OK
)
1833 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1839 DAP_COMMAND_HANDLER(dap_apid_command
)
1841 uint32_t apsel
, apselsave
, apid
;
1844 apselsave
= swjdp
->apsel
;
1847 apsel
= swjdp
->apsel
;
1850 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1851 /* AP address is in bits 31:24 of DP_SELECT */
1853 return ERROR_INVALID_ARGUMENTS
;
1856 return ERROR_COMMAND_SYNTAX_ERROR
;
1859 if (apselsave
!= apsel
)
1860 dap_ap_select(swjdp
, apsel
);
1862 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1863 retval
= dap_run(swjdp
);
1864 if (retval
!= ERROR_OK
)
1867 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1868 if (apselsave
!= apsel
)
1869 dap_ap_select(swjdp
, apselsave
);
1875 * This represents the bits which must be sent out on TMS/SWDIO to
1876 * switch a DAP implemented using an SWJ-DP module into SWD mode.
1877 * These bits are stored (and transmitted) LSB-first.
1879 * See the DAP-Lite specification, section 2.2.5 for information
1880 * about making the debug link select SWD or JTAG. (Similar info
1881 * is in a few other ARM documents.)
1883 static const uint8_t jtag2swd_bitseq
[] = {
1884 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1885 * putting both JTAG and SWD logic into reset state.
1887 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1888 /* Switching sequence enables SWD and disables JTAG
1889 * NOTE: bits in the DP's IDCODE may expose the need for
1890 * an old/deprecated sequence (0xb6 0xed).
1893 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1894 * putting both JTAG and SWD logic into reset state.
1896 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1900 * Put the debug link into SWD mode, if the target supports it.
1901 * The link's initial mode may be either JTAG (for example,
1902 * with SWJ-DP after reset) or SWD.
1904 * @param target Enters SWD mode (if possible).
1906 * Note that targets using the JTAG-DP do not support SWD, and that
1907 * some targets which could otherwise support it may have have been
1908 * configured to disable SWD signaling
1910 * @return ERROR_OK or else a fault code.
1912 int dap_to_swd(struct target
*target
)
1916 LOG_DEBUG("Enter SWD mode");
1918 /* REVISIT it's nasty to need to make calls to a "jtag"
1919 * subsystem if the link isn't in JTAG mode...
1922 retval
= jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq
),
1923 jtag2swd_bitseq
, TAP_INVALID
);
1924 if (retval
== ERROR_OK
)
1925 retval
= jtag_execute_queue();
1927 /* REVISIT set up the DAP's ops vector for SWD mode. */
1933 * This represents the bits which must be sent out on TMS/SWDIO to
1934 * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1935 * These bits are stored (and transmitted) LSB-first.
1937 * These bits are stored (and transmitted) LSB-first.
1939 static const uint8_t swd2jtag_bitseq
[] = {
1940 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1941 * putting both JTAG and SWD logic into reset state.
1943 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1944 /* Switching equence disables SWD and enables JTAG
1945 * NOTE: bits in the DP's IDCODE can expose the need for
1946 * the old/deprecated sequence (0xae 0xde).
1949 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1950 * putting both JTAG and SWD logic into reset state.
1951 * NOTE: some docs say "at least 5".
1953 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1956 /** Put the debug link into JTAG mode, if the target supports it.
1957 * The link's initial mode may be either SWD or JTAG.
1959 * @param target Enters JTAG mode (if possible).
1961 * Note that targets implemented with SW-DP do not support JTAG, and
1962 * that some targets which could otherwise support it may have been
1963 * configured to disable JTAG signaling
1965 * @return ERROR_OK or else a fault code.
1967 int dap_to_jtag(struct target
*target
)
1971 LOG_DEBUG("Enter JTAG mode");
1973 /* REVISIT it's nasty to need to make calls to a "jtag"
1974 * subsystem if the link isn't in JTAG mode...
1977 retval
= jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq
),
1978 swd2jtag_bitseq
, TAP_RESET
);
1979 if (retval
== ERROR_OK
)
1980 retval
= jtag_execute_queue();
1982 /* REVISIT set up the DAP's ops vector for JTAG mode. */
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