1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
77 #include "transport/transport.h"
78 #include <helper/jep106.h>
79 #include <helper/time_support.h>
80 #include <helper/list.h>
81 #include <helper/jim-nvp.h>
83 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
86 uint32_t tar_block_size(uint32_t address)
87 Return the largest block starting at address that does not cross a tar block size alignment boundary
89 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
91 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
94 /***************************************************************************
96 * DP and MEM-AP register access through APACC and DPACC *
98 ***************************************************************************/
100 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
102 csw
|= ap
->csw_default
;
104 if (csw
!= ap
->csw_value
) {
105 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
106 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW
, csw
);
107 if (retval
!= ERROR_OK
) {
116 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, uint32_t tar
)
118 if (!ap
->tar_valid
|| tar
!= ap
->tar_value
) {
119 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
120 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR
, tar
);
121 if (retval
!= ERROR_OK
) {
122 ap
->tar_valid
= false;
126 ap
->tar_valid
= true;
131 static int mem_ap_read_tar(struct adiv5_ap
*ap
, uint32_t *tar
)
133 int retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, tar
);
134 if (retval
!= ERROR_OK
) {
135 ap
->tar_valid
= false;
139 retval
= dap_run(ap
->dap
);
140 if (retval
!= ERROR_OK
) {
141 ap
->tar_valid
= false;
145 ap
->tar_value
= *tar
;
146 ap
->tar_valid
= true;
150 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap
*ap
)
152 switch (ap
->csw_value
& CSW_ADDRINC_MASK
) {
153 case CSW_ADDRINC_SINGLE
:
154 switch (ap
->csw_value
& CSW_SIZE_MASK
) {
164 case CSW_ADDRINC_PACKED
:
170 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
172 static void mem_ap_update_tar_cache(struct adiv5_ap
*ap
)
177 uint32_t inc
= mem_ap_get_tar_increment(ap
);
178 if (inc
>= max_tar_block_size(ap
->tar_autoincr_block
, ap
->tar_value
))
179 ap
->tar_valid
= false;
181 ap
->tar_value
+= inc
;
185 * Queue transactions setting up transfer parameters for the
186 * currently selected MEM-AP.
188 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
189 * initiate data reads or writes using memory or peripheral addresses.
190 * If the CSW is configured for it, the TAR may be automatically
191 * incremented after each transfer.
193 * @param ap The MEM-AP.
194 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
195 * matches the cached value, the register is not changed.
196 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
197 * matches the cached address, the register is not changed.
199 * @return ERROR_OK if the transaction was properly queued, else a fault code.
201 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, uint32_t tar
)
204 retval
= mem_ap_setup_csw(ap
, csw
);
205 if (retval
!= ERROR_OK
)
207 retval
= mem_ap_setup_tar(ap
, tar
);
208 if (retval
!= ERROR_OK
)
214 * Asynchronous (queued) read of a word from memory or a system register.
216 * @param ap The MEM-AP to access.
217 * @param address Address of the 32-bit word to read; it must be
218 * readable by the currently selected MEM-AP.
219 * @param value points to where the word will be stored when the
220 * transaction queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_read_u32(struct adiv5_ap
*ap
, uint32_t address
,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when reading several consecutive addresses.
232 retval
= mem_ap_setup_transfer(ap
,
233 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
234 address
& 0xFFFFFFF0);
235 if (retval
!= ERROR_OK
)
238 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
242 * Synchronous read of a word from memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param ap The MEM-AP to access.
246 * @param address Address of the 32-bit word to read; it must be
247 * readable by the currently selected MEM-AP.
248 * @param value points to where the result will be stored.
250 * @return ERROR_OK for success; *value holds the result.
251 * Otherwise a fault code.
253 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
258 retval
= mem_ap_read_u32(ap
, address
, value
);
259 if (retval
!= ERROR_OK
)
262 return dap_run(ap
->dap
);
266 * Asynchronous (queued) write of a word to memory or a system register.
268 * @param ap The MEM-AP to access.
269 * @param address Address to be written; it must be writable by
270 * the currently selected MEM-AP.
271 * @param value Word that will be written to the address when transaction
272 * queue is flushed (assuming no errors).
274 * @return ERROR_OK for success. Otherwise a fault code.
276 int mem_ap_write_u32(struct adiv5_ap
*ap
, uint32_t address
,
281 /* Use banked addressing (REG_BDx) to avoid some link traffic
282 * (updating TAR) when writing several consecutive addresses.
284 retval
= mem_ap_setup_transfer(ap
,
285 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
286 address
& 0xFFFFFFF0);
287 if (retval
!= ERROR_OK
)
290 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0
| (address
& 0xC),
295 * Synchronous write of a word to memory or a system register.
296 * As a side effect, this flushes any queued transactions.
298 * @param ap The MEM-AP to access.
299 * @param address Address to be written; it must be writable by
300 * the currently selected MEM-AP.
301 * @param value Word that will be written.
303 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
305 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
308 int retval
= mem_ap_write_u32(ap
, address
, value
);
310 if (retval
!= ERROR_OK
)
313 return dap_run(ap
->dap
);
317 * Synchronous write of a block of memory, using a specific access size.
319 * @param ap The MEM-AP to access.
320 * @param buffer The data buffer to write. No particular alignment is assumed.
321 * @param size Which access size to use, in bytes. 1, 2 or 4.
322 * @param count The number of writes to do (in size units, not bytes).
323 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
324 * @param addrinc Whether the target address should be increased for each write or not. This
325 * should normally be true, except when writing to e.g. a FIFO.
326 * @return ERROR_OK on success, otherwise an error code.
328 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
329 uint32_t address
, bool addrinc
)
331 struct adiv5_dap
*dap
= ap
->dap
;
332 size_t nbytes
= size
* count
;
333 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
336 int retval
= ERROR_OK
;
338 /* TI BE-32 Quirks mode:
339 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
340 * size write address bytes written in order
341 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
342 * 2 TAR ^ 2 (val >> 8), (val)
344 * For example, if you attempt to write a single byte to address 0, the processor
345 * will actually write a byte to address 3.
347 * To make writes of size < 4 work as expected, we xor a value with the address before
348 * setting the TAP, and we set the TAP after every transfer rather then relying on
349 * address increment. */
352 csw_size
= CSW_32BIT
;
354 } else if (size
== 2) {
355 csw_size
= CSW_16BIT
;
356 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
357 } else if (size
== 1) {
359 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
361 return ERROR_TARGET_UNALIGNED_ACCESS
;
364 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
365 return ERROR_TARGET_UNALIGNED_ACCESS
;
368 uint32_t this_size
= size
;
370 /* Select packed transfer if possible */
371 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
372 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
374 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
376 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
379 if (retval
!= ERROR_OK
)
382 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
383 if (retval
!= ERROR_OK
)
386 /* How many source bytes each transfer will consume, and their location in the DRW,
387 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
388 uint32_t outvalue
= 0;
389 uint32_t drw_byte_idx
= address
;
390 if (dap
->ti_be_32_quirks
) {
393 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
394 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
395 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
396 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
& 3) ^ addr_xor
);
399 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
400 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
& 3) ^ addr_xor
);
403 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (drw_byte_idx
& 3) ^ addr_xor
);
409 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
410 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
413 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
416 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
& 3);
422 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW
, outvalue
);
423 if (retval
!= ERROR_OK
)
426 mem_ap_update_tar_cache(ap
);
428 address
+= this_size
;
431 /* REVISIT: Might want to have a queued version of this function that does not run. */
432 if (retval
== ERROR_OK
)
433 retval
= dap_run(dap
);
435 if (retval
!= ERROR_OK
) {
437 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
)
438 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
440 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
447 * Synchronous read of a block of memory, using a specific access size.
449 * @param ap The MEM-AP to access.
450 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
451 * @param size Which access size to use, in bytes. 1, 2 or 4.
452 * @param count The number of reads to do (in size units, not bytes).
453 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
454 * @param addrinc Whether the target address should be increased after each read or not. This
455 * should normally be true, except when reading from e.g. a FIFO.
456 * @return ERROR_OK on success, otherwise an error code.
458 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
459 uint32_t adr
, bool addrinc
)
461 struct adiv5_dap
*dap
= ap
->dap
;
462 size_t nbytes
= size
* count
;
463 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
465 uint32_t address
= adr
;
466 int retval
= ERROR_OK
;
468 /* TI BE-32 Quirks mode:
469 * Reads on big-endian TMS570 behave strangely differently than writes.
470 * They read from the physical address requested, but with DRW byte-reversed.
471 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
472 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
476 csw_size
= CSW_32BIT
;
478 csw_size
= CSW_16BIT
;
482 return ERROR_TARGET_UNALIGNED_ACCESS
;
484 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
485 return ERROR_TARGET_UNALIGNED_ACCESS
;
487 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
488 * over-allocation if packed transfers are going to be used, but determining the real need at
489 * this point would be messy. */
490 uint32_t *read_buf
= calloc(count
, sizeof(uint32_t));
491 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
492 uint32_t *read_ptr
= read_buf
;
493 if (read_buf
== NULL
) {
494 LOG_ERROR("Failed to allocate read buffer");
498 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
499 * useful bytes it contains, and their location in the word, depends on the type of transfer
502 uint32_t this_size
= size
;
504 /* Select packed transfer if possible */
505 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
506 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
508 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
510 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
512 if (retval
!= ERROR_OK
)
515 retval
= mem_ap_setup_tar(ap
, address
);
516 if (retval
!= ERROR_OK
)
519 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW
, read_ptr
++);
520 if (retval
!= ERROR_OK
)
525 address
+= this_size
;
527 mem_ap_update_tar_cache(ap
);
530 if (retval
== ERROR_OK
)
531 retval
= dap_run(dap
);
535 nbytes
= size
* count
;
538 /* If something failed, read TAR to find out how much data was successfully read, so we can
539 * at least give the caller what we have. */
540 if (retval
!= ERROR_OK
) {
542 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
) {
543 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
544 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
545 if (nbytes
> tar
- address
)
546 nbytes
= tar
- address
;
548 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
553 /* Replay loop to populate caller's buffer from the correct word and byte lane */
555 uint32_t this_size
= size
;
557 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
558 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
562 if (dap
->ti_be_32_quirks
) {
565 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
566 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
569 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
572 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
577 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
578 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
581 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
584 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
596 int mem_ap_read_buf(struct adiv5_ap
*ap
,
597 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
599 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
602 int mem_ap_write_buf(struct adiv5_ap
*ap
,
603 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
605 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
608 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
609 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
611 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
614 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
615 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
617 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /*--------------------------------------------------------------------------*/
628 * Invalidate cached DP select and cached TAR and CSW of all APs
630 void dap_invalidate_cache(struct adiv5_dap
*dap
)
632 dap
->select
= DP_SELECT_INVALID
;
633 dap
->last_read
= NULL
;
636 for (i
= 0; i
<= 255; i
++) {
637 /* force csw and tar write on the next mem-ap access */
638 dap
->ap
[i
].tar_valid
= false;
639 dap
->ap
[i
].csw_value
= 0;
644 * Initialize a DAP. This sets up the power domains, prepares the DP
645 * for further use and activates overrun checking.
647 * @param dap The DAP being initialized.
649 int dap_dp_init(struct adiv5_dap
*dap
)
653 LOG_DEBUG("%s", adiv5_dap_name(dap
));
655 dap_invalidate_cache(dap
);
658 * Early initialize dap->dp_ctrl_stat.
659 * In jtag mode only, if the following atomic reads fail and set the
660 * sticky error, it will trigger the clearing of the sticky. Without this
661 * initialization system and debug power would be disabled while clearing
662 * the sticky error bit.
664 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
666 for (size_t i
= 0; i
< 30; i
++) {
667 /* DP initialization */
669 retval
= dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
670 if (retval
== ERROR_OK
)
675 * This write operation clears the sticky error bit in jtag mode only and
676 * is ignored in swd mode. It also powers-up system and debug domains in
677 * both jtag and swd modes, if not done before.
678 * Actually we do not need to clear the sticky error here because it has
679 * been already cleared (if it was set) in the previous atomic read. This
680 * write could be removed, but this initial part of dap_dp_init() is the
681 * result of years of fine tuning and there are strong concerns about any
682 * unnecessary code change. It doesn't harm, so let's keep it here and
683 * preserve the historical sequence of read/write operations!
685 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
| SSTICKYERR
);
686 if (retval
!= ERROR_OK
)
689 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
690 if (retval
!= ERROR_OK
)
693 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
694 if (retval
!= ERROR_OK
)
697 /* Check that we have debug power domains activated */
698 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
699 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
700 CDBGPWRUPACK
, CDBGPWRUPACK
,
701 DAP_POWER_DOMAIN_TIMEOUT
);
702 if (retval
!= ERROR_OK
)
705 if (!dap
->ignore_syspwrupack
) {
706 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
707 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
708 CSYSPWRUPACK
, CSYSPWRUPACK
,
709 DAP_POWER_DOMAIN_TIMEOUT
);
710 if (retval
!= ERROR_OK
)
714 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
715 if (retval
!= ERROR_OK
)
718 /* With debug power on we can activate OVERRUN checking */
719 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
720 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
721 if (retval
!= ERROR_OK
)
723 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
724 if (retval
!= ERROR_OK
)
727 retval
= dap_run(dap
);
728 if (retval
!= ERROR_OK
)
735 * Initialize a DAP. This sets up the power domains, prepares the DP
736 * for further use, and arranges to use AP #0 for all AP operations
737 * until dap_ap-select() changes that policy.
739 * @param ap The MEM-AP being initialized.
741 int mem_ap_init(struct adiv5_ap
*ap
)
743 /* check that we support packed transfers */
746 struct adiv5_dap
*dap
= ap
->dap
;
748 ap
->tar_valid
= false;
749 ap
->csw_value
= 0; /* force csw and tar write */
750 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
751 if (retval
!= ERROR_OK
)
754 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW
, &csw
);
755 if (retval
!= ERROR_OK
)
758 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &cfg
);
759 if (retval
!= ERROR_OK
)
762 retval
= dap_run(dap
);
763 if (retval
!= ERROR_OK
)
766 if (csw
& CSW_ADDRINC_PACKED
)
767 ap
->packed_transfers
= true;
769 ap
->packed_transfers
= false;
771 /* Packed transfers on TI BE-32 processors do not work correctly in
773 if (dap
->ti_be_32_quirks
)
774 ap
->packed_transfers
= false;
776 LOG_DEBUG("MEM_AP Packed Transfers: %s",
777 ap
->packed_transfers
? "enabled" : "disabled");
779 /* The ARM ADI spec leaves implementation-defined whether unaligned
780 * memory accesses work, only work partially, or cause a sticky error.
781 * On TI BE-32 processors, reads seem to return garbage in some bytes
782 * and unaligned writes seem to cause a sticky error.
783 * TODO: it would be nice to have a way to detect whether unaligned
784 * operations are supported on other processors. */
785 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
787 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
788 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
794 * Put the debug link into SWD mode, if the target supports it.
795 * The link's initial mode may be either JTAG (for example,
796 * with SWJ-DP after reset) or SWD.
798 * Note that targets using the JTAG-DP do not support SWD, and that
799 * some targets which could otherwise support it may have been
800 * configured to disable SWD signaling
802 * @param dap The DAP used
803 * @return ERROR_OK or else a fault code.
805 int dap_to_swd(struct adiv5_dap
*dap
)
807 LOG_DEBUG("Enter SWD mode");
809 return dap_send_sequence(dap
, JTAG_TO_SWD
);
813 * Put the debug link into JTAG mode, if the target supports it.
814 * The link's initial mode may be either SWD or JTAG.
816 * Note that targets implemented with SW-DP do not support JTAG, and
817 * that some targets which could otherwise support it may have been
818 * configured to disable JTAG signaling
820 * @param dap The DAP used
821 * @return ERROR_OK or else a fault code.
823 int dap_to_jtag(struct adiv5_dap
*dap
)
825 LOG_DEBUG("Enter JTAG mode");
827 return dap_send_sequence(dap
, SWD_TO_JTAG
);
830 /* CID interpretation -- see ARM IHI 0029B section 3
831 * and ARM IHI 0031A table 13-3.
833 static const char *class_description
[16] = {
834 "Reserved", "ROM table", "Reserved", "Reserved",
835 "Reserved", "Reserved", "Reserved", "Reserved",
836 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
837 "Reserved", "OptimoDE DESS",
838 "Generic IP component", "PrimeCell or System component"
841 static bool is_dap_cid_ok(uint32_t cid
)
843 return (cid
& 0xffff0fff) == 0xb105000d;
847 * This function checks the ID for each access port to find the requested Access Port type
849 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
853 /* Maximum AP number is 255 since the SELECT register is 8 bits */
854 for (ap_num
= 0; ap_num
<= DP_APSEL_MAX
; ap_num
++) {
856 /* read the IDR register of the Access Port */
859 int retval
= dap_queue_ap_read(dap_ap(dap
, ap_num
), AP_REG_IDR
, &id_val
);
860 if (retval
!= ERROR_OK
)
863 retval
= dap_run(dap
);
867 * 27-24 : JEDEC bank (0x4 for ARM)
868 * 23-17 : JEDEC code (0x3B for ARM)
869 * 16-13 : Class (0b1000=Mem-AP)
871 * 7-4 : AP Variant (non-zero for JTAG-AP)
872 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
875 /* Reading register for a non-existant AP should not cause an error,
876 * but just to be sure, try to continue searching if an error does happen.
878 if ((retval
== ERROR_OK
) && /* Register read success */
879 ((id_val
& IDR_JEP106
) == IDR_JEP106_ARM
) && /* Jedec codes match */
880 ((id_val
& IDR_TYPE
) == type_to_find
)) { /* type matches*/
882 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
883 (type_to_find
== AP_TYPE_AHB3_AP
) ? "AHB3-AP" :
884 (type_to_find
== AP_TYPE_AHB5_AP
) ? "AHB5-AP" :
885 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
886 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
887 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
890 *ap_out
= &dap
->ap
[ap_num
];
895 LOG_DEBUG("No %s found",
896 (type_to_find
== AP_TYPE_AHB3_AP
) ? "AHB3-AP" :
897 (type_to_find
== AP_TYPE_AHB5_AP
) ? "AHB5-AP" :
898 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
899 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
900 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
904 int dap_get_debugbase(struct adiv5_ap
*ap
,
905 uint32_t *dbgbase
, uint32_t *apid
)
907 struct adiv5_dap
*dap
= ap
->dap
;
910 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, dbgbase
);
911 if (retval
!= ERROR_OK
)
913 retval
= dap_queue_ap_read(ap
, AP_REG_IDR
, apid
);
914 if (retval
!= ERROR_OK
)
916 retval
= dap_run(dap
);
917 if (retval
!= ERROR_OK
)
923 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
924 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
926 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
932 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) |
933 entry_offset
, &romentry
);
934 if (retval
!= ERROR_OK
)
937 component_base
= (dbgbase
& 0xFFFFF000)
938 + (romentry
& 0xFFFFF000);
940 if (romentry
& 0x1) {
942 retval
= mem_ap_read_atomic_u32(ap
, component_base
| 0xff4, &c_cid1
);
943 if (retval
!= ERROR_OK
) {
944 LOG_ERROR("Can't read component with base address 0x%" PRIx32
945 ", the corresponding core might be turned off", component_base
);
948 if (((c_cid1
>> 4) & 0x0f) == 1) {
949 retval
= dap_lookup_cs_component(ap
, component_base
,
951 if (retval
== ERROR_OK
)
953 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
957 retval
= mem_ap_read_atomic_u32(ap
,
958 (component_base
& 0xfffff000) | 0xfcc,
960 if (retval
!= ERROR_OK
)
962 if ((devtype
& 0xff) == type
) {
964 *addr
= component_base
;
971 } while (romentry
> 0);
974 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
979 static int dap_read_part_id(struct adiv5_ap
*ap
, uint32_t component_base
, uint32_t *cid
, uint64_t *pid
)
981 assert((component_base
& 0xFFF) == 0);
982 assert(ap
!= NULL
&& cid
!= NULL
&& pid
!= NULL
);
984 uint32_t cid0
, cid1
, cid2
, cid3
;
985 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
988 /* IDs are in last 4K section */
989 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE0, &pid0
);
990 if (retval
!= ERROR_OK
)
992 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE4, &pid1
);
993 if (retval
!= ERROR_OK
)
995 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE8, &pid2
);
996 if (retval
!= ERROR_OK
)
998 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFEC, &pid3
);
999 if (retval
!= ERROR_OK
)
1001 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFD0, &pid4
);
1002 if (retval
!= ERROR_OK
)
1004 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF0, &cid0
);
1005 if (retval
!= ERROR_OK
)
1007 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF4, &cid1
);
1008 if (retval
!= ERROR_OK
)
1010 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF8, &cid2
);
1011 if (retval
!= ERROR_OK
)
1013 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFFC, &cid3
);
1014 if (retval
!= ERROR_OK
)
1017 retval
= dap_run(ap
->dap
);
1018 if (retval
!= ERROR_OK
)
1021 *cid
= (cid3
& 0xff) << 24
1022 | (cid2
& 0xff) << 16
1023 | (cid1
& 0xff) << 8
1025 *pid
= (uint64_t)(pid4
& 0xff) << 32
1026 | (pid3
& 0xff) << 24
1027 | (pid2
& 0xff) << 16
1028 | (pid1
& 0xff) << 8
1034 /* The designer identity code is encoded as:
1035 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
1036 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
1037 * a legacy ASCII Identity Code.
1038 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
1039 * JEP106 is a standard available from jedec.org
1042 /* Part number interpretations are from Cortex
1043 * core specs, the CoreSight components TRM
1044 * (ARM DDI 0314H), CoreSight System Design
1045 * Guide (ARM DGI 0012D) and ETM specs; also
1046 * from chip observation (e.g. TI SDTI).
1049 /* The legacy code only used the part number field to identify CoreSight peripherals.
1050 * This meant that the same part number from two different manufacturers looked the same.
1051 * It is desirable for all future additions to identify with both part number and JEP106.
1052 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1055 #define ANY_ID 0x1000
1057 #define ARM_ID 0x4BB
1059 static const struct {
1060 uint16_t designer_id
;
1064 } dap_partnums
[] = {
1065 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1066 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1067 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1068 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1069 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1070 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1071 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1072 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1073 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1074 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1075 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1076 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1077 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1078 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1079 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1080 { ARM_ID
, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1081 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1082 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1083 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1084 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1085 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1086 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1087 { ARM_ID
, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1088 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1089 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1090 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1091 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1092 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1093 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1094 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1095 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1096 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1097 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1098 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1099 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1100 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1101 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1102 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1103 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1104 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1105 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1106 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1107 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1108 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1109 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1110 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1111 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1112 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1113 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1114 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1115 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1116 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1117 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1118 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1119 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1120 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1121 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1122 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1123 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1124 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1125 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1126 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1127 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1128 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1129 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1130 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1131 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1132 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1133 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1134 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1135 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1136 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1137 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1138 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1139 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1140 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1141 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1142 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1143 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1144 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1145 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1146 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1147 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1148 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1149 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1150 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1151 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1152 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1153 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1154 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1155 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1156 /* legacy comment: 0x113: what? */
1157 { ANY_ID
, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1158 { ANY_ID
, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1161 static int dap_rom_display(struct command_invocation
*cmd
,
1162 struct adiv5_ap
*ap
, uint32_t dbgbase
, int depth
)
1170 command_print(cmd
, "\tTables too deep");
1175 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
1177 uint32_t base_addr
= dbgbase
& 0xFFFFF000;
1178 command_print(cmd
, "\t\tComponent base address 0x%08" PRIx32
, base_addr
);
1180 retval
= dap_read_part_id(ap
, base_addr
, &cid
, &pid
);
1181 if (retval
!= ERROR_OK
) {
1182 command_print(cmd
, "\t\tCan't read component, the corresponding core might be turned off");
1183 return ERROR_OK
; /* Don't abort recursion */
1186 if (!is_dap_cid_ok(cid
)) {
1187 command_print(cmd
, "\t\tInvalid CID 0x%08" PRIx32
, cid
);
1188 return ERROR_OK
; /* Don't abort recursion */
1191 /* component may take multiple 4K pages */
1192 uint32_t size
= (pid
>> 36) & 0xf;
1194 command_print(cmd
, "\t\tStart address 0x%08" PRIx32
, (uint32_t)(base_addr
- 0x1000 * size
));
1196 command_print(cmd
, "\t\tPeripheral ID 0x%010" PRIx64
, pid
);
1198 uint8_t class = (cid
>> 12) & 0xf;
1199 uint16_t part_num
= pid
& 0xfff;
1200 uint16_t designer_id
= ((pid
>> 32) & 0xf) << 8 | ((pid
>> 12) & 0xff);
1202 if (designer_id
& 0x80) {
1204 command_print(cmd
, "\t\tDesigner is 0x%03" PRIx16
", %s",
1205 designer_id
, jep106_manufacturer(designer_id
>> 8, designer_id
& 0x7f));
1207 /* Legacy ASCII ID, clear invalid bits */
1208 designer_id
&= 0x7f;
1209 command_print(cmd
, "\t\tDesigner ASCII code 0x%02" PRIx16
", %s",
1210 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
1213 /* default values to be overwritten upon finding a match */
1214 const char *type
= "Unrecognized";
1215 const char *full
= "";
1217 /* search dap_partnums[] array for a match */
1218 for (unsigned entry
= 0; entry
< ARRAY_SIZE(dap_partnums
); entry
++) {
1220 if ((dap_partnums
[entry
].designer_id
!= designer_id
) && (dap_partnums
[entry
].designer_id
!= ANY_ID
))
1223 if (dap_partnums
[entry
].part_num
!= part_num
)
1226 type
= dap_partnums
[entry
].type
;
1227 full
= dap_partnums
[entry
].full
;
1231 command_print(cmd
, "\t\tPart is 0x%" PRIx16
", %s %s", part_num
, type
, full
);
1232 command_print(cmd
, "\t\tComponent class is 0x%" PRIx8
", %s", class, class_description
[class]);
1234 if (class == 1) { /* ROM Table */
1236 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &memtype
);
1237 if (retval
!= ERROR_OK
)
1241 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
1243 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1245 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1246 for (uint16_t entry_offset
= 0; entry_offset
< 0xF00; entry_offset
+= 4) {
1248 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| entry_offset
, &romentry
);
1249 if (retval
!= ERROR_OK
)
1251 command_print(cmd
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
1252 tabs
, entry_offset
, romentry
);
1253 if (romentry
& 0x01) {
1255 retval
= dap_rom_display(cmd
, ap
, base_addr
+ (romentry
& 0xFFFFF000), depth
+ 1);
1256 if (retval
!= ERROR_OK
)
1258 } else if (romentry
!= 0) {
1259 command_print(cmd
, "\t\tComponent not present");
1261 command_print(cmd
, "\t%s\tEnd of ROM table", tabs
);
1265 } else if (class == 9) { /* CoreSight component */
1266 const char *major
= "Reserved", *subtype
= "Reserved";
1269 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &devtype
);
1270 if (retval
!= ERROR_OK
)
1272 unsigned minor
= (devtype
>> 4) & 0x0f;
1273 switch (devtype
& 0x0f) {
1275 major
= "Miscellaneous";
1281 subtype
= "Validation component";
1286 major
= "Trace Sink";
1303 major
= "Trace Link";
1309 subtype
= "Funnel, router";
1315 subtype
= "FIFO, buffer";
1320 major
= "Trace Source";
1326 subtype
= "Processor";
1332 subtype
= "Engine/Coprocessor";
1338 subtype
= "Software";
1343 major
= "Debug Control";
1349 subtype
= "Trigger Matrix";
1352 subtype
= "Debug Auth";
1355 subtype
= "Power Requestor";
1360 major
= "Debug Logic";
1366 subtype
= "Processor";
1372 subtype
= "Engine/Coprocessor";
1383 major
= "Performance Monitor";
1389 subtype
= "Processor";
1395 subtype
= "Engine/Coprocessor";
1406 command_print(cmd
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1407 (uint8_t)(devtype
& 0xff),
1409 /* REVISIT also show 0xfc8 DevId */
1415 int dap_info_command(struct command_invocation
*cmd
,
1416 struct adiv5_ap
*ap
)
1419 uint32_t dbgbase
, apid
;
1422 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1423 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1424 if (retval
!= ERROR_OK
)
1427 command_print(cmd
, "AP ID register 0x%8.8" PRIx32
, apid
);
1429 command_print(cmd
, "No AP found at this ap 0x%x", ap
->ap_num
);
1433 switch (apid
& (IDR_JEP106
| IDR_TYPE
)) {
1434 case IDR_JEP106_ARM
| AP_TYPE_JTAG_AP
:
1435 command_print(cmd
, "\tType is JTAG-AP");
1437 case IDR_JEP106_ARM
| AP_TYPE_AHB3_AP
:
1438 command_print(cmd
, "\tType is MEM-AP AHB3");
1440 case IDR_JEP106_ARM
| AP_TYPE_AHB5_AP
:
1441 command_print(cmd
, "\tType is MEM-AP AHB5");
1443 case IDR_JEP106_ARM
| AP_TYPE_APB_AP
:
1444 command_print(cmd
, "\tType is MEM-AP APB");
1446 case IDR_JEP106_ARM
| AP_TYPE_AXI_AP
:
1447 command_print(cmd
, "\tType is MEM-AP AXI");
1450 command_print(cmd
, "\tUnknown AP type");
1454 /* NOTE: a MEM-AP may have a single CoreSight component that's
1455 * not a ROM table ... or have no such components at all.
1457 mem_ap
= (apid
& IDR_CLASS
) == AP_CLASS_MEM_AP
;
1459 command_print(cmd
, "MEM-AP BASE 0x%8.8" PRIx32
, dbgbase
);
1461 if (dbgbase
== 0xFFFFFFFF || (dbgbase
& 0x3) == 0x2) {
1462 command_print(cmd
, "\tNo ROM table present");
1465 command_print(cmd
, "\tValid ROM table present");
1467 command_print(cmd
, "\tROM table in legacy format");
1469 dap_rom_display(cmd
, ap
, dbgbase
& 0xFFFFF000, 0);
1476 enum adiv5_cfg_param
{
1481 static const Jim_Nvp nvp_config_opts
[] = {
1482 { .name
= "-dap", .value
= CFG_DAP
},
1483 { .name
= "-ap-num", .value
= CFG_AP_NUM
},
1484 { .name
= NULL
, .value
= -1 }
1487 int adiv5_jim_configure(struct target
*target
, Jim_GetOptInfo
*goi
)
1489 struct adiv5_private_config
*pc
;
1492 pc
= (struct adiv5_private_config
*)target
->private_config
;
1494 pc
= calloc(1, sizeof(struct adiv5_private_config
));
1495 pc
->ap_num
= DP_APSEL_INVALID
;
1496 target
->private_config
= pc
;
1499 target
->has_dap
= true;
1501 if (goi
->argc
> 0) {
1504 Jim_SetEmptyResult(goi
->interp
);
1506 /* check first if topmost item is for us */
1507 e
= Jim_Nvp_name2value_obj(goi
->interp
, nvp_config_opts
,
1510 return JIM_CONTINUE
;
1512 e
= Jim_GetOpt_Obj(goi
, NULL
);
1518 if (goi
->isconfigure
) {
1520 struct adiv5_dap
*dap
;
1521 e
= Jim_GetOpt_Obj(goi
, &o_t
);
1524 dap
= dap_instance_by_jim_obj(goi
->interp
, o_t
);
1526 Jim_SetResultString(goi
->interp
, "DAP name invalid!", -1);
1529 if (pc
->dap
!= NULL
&& pc
->dap
!= dap
) {
1530 Jim_SetResultString(goi
->interp
,
1531 "DAP assignment cannot be changed after target was created!", -1);
1534 if (target
->tap_configured
) {
1535 Jim_SetResultString(goi
->interp
,
1536 "-chain-position and -dap configparams are mutually exclusive!", -1);
1540 target
->tap
= dap
->tap
;
1541 target
->dap_configured
= true;
1543 if (goi
->argc
!= 0) {
1544 Jim_WrongNumArgs(goi
->interp
,
1545 goi
->argc
, goi
->argv
,
1550 if (pc
->dap
== NULL
) {
1551 Jim_SetResultString(goi
->interp
, "DAP not configured", -1);
1554 Jim_SetResultString(goi
->interp
, adiv5_dap_name(pc
->dap
), -1);
1559 if (goi
->isconfigure
) {
1561 e
= Jim_GetOpt_Wide(goi
, &ap_num
);
1564 if (ap_num
< 0 || ap_num
> DP_APSEL_MAX
) {
1565 Jim_SetResultString(goi
->interp
, "Invalid AP number!", -1);
1568 pc
->ap_num
= ap_num
;
1570 if (goi
->argc
!= 0) {
1571 Jim_WrongNumArgs(goi
->interp
,
1572 goi
->argc
, goi
->argv
,
1577 if (pc
->ap_num
== DP_APSEL_INVALID
) {
1578 Jim_SetResultString(goi
->interp
, "AP number not configured", -1);
1581 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, pc
->ap_num
));
1590 int adiv5_verify_config(struct adiv5_private_config
*pc
)
1595 if (pc
->dap
== NULL
)
1602 COMMAND_HANDLER(handle_dap_info_command
)
1604 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1612 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1613 if (apsel
> DP_APSEL_MAX
)
1614 return ERROR_COMMAND_SYNTAX_ERROR
;
1617 return ERROR_COMMAND_SYNTAX_ERROR
;
1620 return dap_info_command(CMD
, &dap
->ap
[apsel
]);
1623 COMMAND_HANDLER(dap_baseaddr_command
)
1625 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1626 uint32_t apsel
, baseaddr
;
1634 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1635 /* AP address is in bits 31:24 of DP_SELECT */
1636 if (apsel
> DP_APSEL_MAX
)
1637 return ERROR_COMMAND_SYNTAX_ERROR
;
1640 return ERROR_COMMAND_SYNTAX_ERROR
;
1643 /* NOTE: assumes we're talking to a MEM-AP, which
1644 * has a base address. There are other kinds of AP,
1645 * though they're not common for now. This should
1646 * use the ID register to verify it's a MEM-AP.
1648 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), MEM_AP_REG_BASE
, &baseaddr
);
1649 if (retval
!= ERROR_OK
)
1651 retval
= dap_run(dap
);
1652 if (retval
!= ERROR_OK
)
1655 command_print(CMD
, "0x%8.8" PRIx32
, baseaddr
);
1660 COMMAND_HANDLER(dap_memaccess_command
)
1662 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1663 uint32_t memaccess_tck
;
1667 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1670 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1673 return ERROR_COMMAND_SYNTAX_ERROR
;
1675 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1677 command_print(CMD
, "memory bus access delay set to %" PRIi32
" tck",
1678 dap
->ap
[dap
->apsel
].memaccess_tck
);
1683 COMMAND_HANDLER(dap_apsel_command
)
1685 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1690 command_print(CMD
, "%" PRIi32
, dap
->apsel
);
1693 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1694 /* AP address is in bits 31:24 of DP_SELECT */
1695 if (apsel
> DP_APSEL_MAX
)
1696 return ERROR_COMMAND_SYNTAX_ERROR
;
1699 return ERROR_COMMAND_SYNTAX_ERROR
;
1706 COMMAND_HANDLER(dap_apcsw_command
)
1708 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1709 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
;
1710 uint32_t csw_val
, csw_mask
;
1714 command_print(CMD
, "ap %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1718 if (strcmp(CMD_ARGV
[0], "default") == 0)
1719 csw_val
= CSW_AHB_DEFAULT
;
1721 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1723 if (csw_val
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1724 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1725 return ERROR_COMMAND_SYNTAX_ERROR
;
1730 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1731 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], csw_mask
);
1732 if (csw_mask
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1733 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1734 return ERROR_COMMAND_SYNTAX_ERROR
;
1736 apcsw
= (apcsw
& ~csw_mask
) | (csw_val
& csw_mask
);
1739 return ERROR_COMMAND_SYNTAX_ERROR
;
1741 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1748 COMMAND_HANDLER(dap_apid_command
)
1750 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1751 uint32_t apsel
, apid
;
1759 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1760 /* AP address is in bits 31:24 of DP_SELECT */
1761 if (apsel
> DP_APSEL_MAX
)
1762 return ERROR_COMMAND_SYNTAX_ERROR
;
1765 return ERROR_COMMAND_SYNTAX_ERROR
;
1768 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1769 if (retval
!= ERROR_OK
)
1771 retval
= dap_run(dap
);
1772 if (retval
!= ERROR_OK
)
1775 command_print(CMD
, "0x%8.8" PRIx32
, apid
);
1780 COMMAND_HANDLER(dap_apreg_command
)
1782 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1783 uint32_t apsel
, reg
, value
;
1784 struct adiv5_ap
*ap
;
1787 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
1788 return ERROR_COMMAND_SYNTAX_ERROR
;
1790 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1791 /* AP address is in bits 31:24 of DP_SELECT */
1792 if (apsel
> DP_APSEL_MAX
)
1793 return ERROR_COMMAND_SYNTAX_ERROR
;
1794 ap
= dap_ap(dap
, apsel
);
1796 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
1797 if (reg
>= 256 || (reg
& 3))
1798 return ERROR_COMMAND_SYNTAX_ERROR
;
1800 if (CMD_ARGC
== 3) {
1801 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1803 case MEM_AP_REG_CSW
:
1804 ap
->csw_value
= 0; /* invalid, in case write fails */
1805 retval
= dap_queue_ap_write(ap
, reg
, value
);
1806 if (retval
== ERROR_OK
)
1807 ap
->csw_value
= value
;
1809 case MEM_AP_REG_TAR
:
1810 ap
->tar_valid
= false; /* invalid, force write */
1811 retval
= mem_ap_setup_tar(ap
, value
);
1814 retval
= dap_queue_ap_write(ap
, reg
, value
);
1818 retval
= dap_queue_ap_read(ap
, reg
, &value
);
1820 if (retval
== ERROR_OK
)
1821 retval
= dap_run(dap
);
1823 if (retval
!= ERROR_OK
)
1827 command_print(CMD
, "0x%08" PRIx32
, value
);
1832 COMMAND_HANDLER(dap_dpreg_command
)
1834 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1835 uint32_t reg
, value
;
1838 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
1839 return ERROR_COMMAND_SYNTAX_ERROR
;
1841 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg
);
1842 if (reg
>= 256 || (reg
& 3))
1843 return ERROR_COMMAND_SYNTAX_ERROR
;
1845 if (CMD_ARGC
== 2) {
1846 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1847 retval
= dap_queue_dp_write(dap
, reg
, value
);
1849 retval
= dap_queue_dp_read(dap
, reg
, &value
);
1851 if (retval
== ERROR_OK
)
1852 retval
= dap_run(dap
);
1854 if (retval
!= ERROR_OK
)
1858 command_print(CMD
, "0x%08" PRIx32
, value
);
1863 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1865 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1866 uint32_t enable
= dap
->ti_be_32_quirks
;
1872 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1874 return ERROR_COMMAND_SYNTAX_ERROR
;
1877 return ERROR_COMMAND_SYNTAX_ERROR
;
1879 dap
->ti_be_32_quirks
= enable
;
1880 command_print(CMD
, "TI BE-32 quirks mode %s",
1881 enable
? "enabled" : "disabled");
1886 const struct command_registration dap_instance_commands
[] = {
1889 .handler
= handle_dap_info_command
,
1890 .mode
= COMMAND_EXEC
,
1891 .help
= "display ROM table for MEM-AP "
1892 "(default currently selected AP)",
1893 .usage
= "[ap_num]",
1897 .handler
= dap_apsel_command
,
1898 .mode
= COMMAND_ANY
,
1899 .help
= "Set the currently selected AP (default 0) "
1900 "and display the result",
1901 .usage
= "[ap_num]",
1905 .handler
= dap_apcsw_command
,
1906 .mode
= COMMAND_ANY
,
1907 .help
= "Set CSW default bits",
1908 .usage
= "[value [mask]]",
1913 .handler
= dap_apid_command
,
1914 .mode
= COMMAND_EXEC
,
1915 .help
= "return ID register from AP "
1916 "(default currently selected AP)",
1917 .usage
= "[ap_num]",
1921 .handler
= dap_apreg_command
,
1922 .mode
= COMMAND_EXEC
,
1923 .help
= "read/write a register from AP "
1924 "(reg is byte address of a word register, like 0 4 8...)",
1925 .usage
= "ap_num reg [value]",
1929 .handler
= dap_dpreg_command
,
1930 .mode
= COMMAND_EXEC
,
1931 .help
= "read/write a register from DP "
1932 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
1933 .usage
= "reg [value]",
1937 .handler
= dap_baseaddr_command
,
1938 .mode
= COMMAND_EXEC
,
1939 .help
= "return debug base address from MEM-AP "
1940 "(default currently selected AP)",
1941 .usage
= "[ap_num]",
1944 .name
= "memaccess",
1945 .handler
= dap_memaccess_command
,
1946 .mode
= COMMAND_EXEC
,
1947 .help
= "set/get number of extra tck for MEM-AP memory "
1948 "bus access [0-255]",
1949 .usage
= "[cycles]",
1952 .name
= "ti_be_32_quirks",
1953 .handler
= dap_ti_be_32_quirks_command
,
1954 .mode
= COMMAND_CONFIG
,
1955 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1956 .usage
= "[enable]",
1958 COMMAND_REGISTRATION_DONE
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