1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2006 by Magnus Lundin *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2019-2021, Ampere Computing LLC *
11 ***************************************************************************/
13 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
14 #define OPENOCD_TARGET_ARM_ADI_V5_H
18 * This defines formats and data structures used to talk to ADIv5 entities.
19 * Those include a DAP, different types of Debug Port (DP), and memory mapped
20 * resources accessed through a MEM-AP.
23 #include <helper/list.h>
25 #include "helper/bits.h"
27 /* JEP106 ID for ARM */
30 /* three-bit ACK values for SWD access (sent LSB first) */
31 #define SWD_ACK_OK 0x1
32 #define SWD_ACK_WAIT 0x2
33 #define SWD_ACK_FAULT 0x4
38 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
40 /* A[3:0] for DP registers; A[1:0] are always zero.
41 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
42 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
43 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
45 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
46 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
47 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
48 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
49 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
50 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
51 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
52 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
53 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
54 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
55 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
56 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
57 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
58 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
59 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
61 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
63 /* Fields of DP_DPIDR register */
64 #define DP_DPIDR_VERSION_SHIFT 12
65 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
67 /* Fields of the DP's AP ABORT register */
68 #define DAPABORT (1UL << 0)
69 #define STKCMPCLR (1UL << 1) /* SWD-only */
70 #define STKERRCLR (1UL << 2) /* SWD-only */
71 #define WDERRCLR (1UL << 3) /* SWD-only */
72 #define ORUNERRCLR (1UL << 4) /* SWD-only */
74 /* Fields of register DP_DPIDR1 */
75 #define DP_DPIDR1_ASIZE_MASK (0x7F)
76 #define DP_DPIDR1_ERRMODE BIT(7)
78 /* Fields of register DP_BASEPTR0 */
79 #define DP_BASEPTR0_VALID BIT(0)
81 /* Fields of the DP's CTRL/STAT register */
82 #define CORUNDETECT (1UL << 0)
83 #define SSTICKYORUN (1UL << 1)
84 /* 3:2 - transaction mode (e.g. pushed compare) */
85 #define SSTICKYCMP (1UL << 4)
86 #define SSTICKYERR (1UL << 5)
87 #define READOK (1UL << 6) /* SWD-only */
88 #define WDATAERR (1UL << 7) /* SWD-only */
89 /* 11:8 - mask lanes for pushed compare or verify ops */
90 /* 21:12 - transaction counter */
91 #define CDBGRSTREQ (1UL << 26)
92 #define CDBGRSTACK (1UL << 27)
93 #define CDBGPWRUPREQ (1UL << 28)
94 #define CDBGPWRUPACK (1UL << 29)
95 #define CSYSPWRUPREQ (1UL << 30)
96 #define CSYSPWRUPACK (1UL << 31)
98 #define DP_DLPIDR_PROTVSN 1u
100 #define ADIV5_DP_SELECT_APSEL 0xFF000000
101 #define ADIV5_DP_SELECT_APBANK 0x000000F0
102 #define DP_SELECT_DPBANK 0x0000000F
104 * Mask of AP ADDR in select cache, concatenating DP SELECT and DP_SELECT1.
105 * In case of ADIv5, the mask contains both APSEL and APBANKSEL fields.
107 #define SELECT_AP_MASK (~(uint64_t)DP_SELECT_DPBANK)
109 #define DP_APSEL_MAX (255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */
110 #define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
112 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
113 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
114 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
115 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
118 /* MEM-AP register addresses */
119 #define ADIV5_MEM_AP_REG_CSW (0x00)
120 #define ADIV5_MEM_AP_REG_TAR (0x04)
121 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
122 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
123 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
124 #define ADIV5_MEM_AP_REG_BD1 (0x14)
125 #define ADIV5_MEM_AP_REG_BD2 (0x18)
126 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
127 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
128 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
129 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
130 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
132 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
133 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
134 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
135 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
136 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
137 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
138 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
139 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
140 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
141 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
142 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
143 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
145 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
146 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
147 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
148 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
149 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
150 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
151 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
152 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
153 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
154 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
155 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
156 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
158 /* Generic AP register address */
159 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
160 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
161 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
163 /* Fields of the MEM-AP's CSW register */
164 #define CSW_SIZE_MASK 7
168 #define CSW_ADDRINC_MASK (3UL << 4)
169 #define CSW_ADDRINC_OFF 0UL
170 #define CSW_ADDRINC_SINGLE (1UL << 4)
171 #define CSW_ADDRINC_PACKED (2UL << 4)
172 #define CSW_DEVICE_EN (1UL << 6)
173 #define CSW_TRIN_PROG (1UL << 7)
175 /* All fields in bits 12 and above are implementation-defined
176 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
177 * Some bits are shared between buses
179 #define CSW_SPIDEN (1UL << 23)
180 #define CSW_DBGSWENABLE (1UL << 31)
182 /* AHB: Privileged */
183 #define CSW_AHB_HPROT1 (1UL << 25)
184 /* AHB: set HMASTER signals to AHB-AP ID */
185 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
186 /* AHB5: non-secure access via HNONSEC
187 * AHB3: SBO, UNPREDICTABLE if zero */
188 #define CSW_AHB_SPROT (1UL << 30)
189 /* AHB: initial value of csw_default */
190 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
192 /* AXI: Privileged */
193 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
194 /* AXI: Non-secure */
195 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
196 /* AXI: initial value of csw_default */
197 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
199 /* APB: initial value of csw_default */
200 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
202 /* Fields of the MEM-AP's CFG register */
203 #define MEM_AP_REG_CFG_BE BIT(0)
204 #define MEM_AP_REG_CFG_LA BIT(1)
205 #define MEM_AP_REG_CFG_LD BIT(2)
206 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
208 /* Fields of the MEM-AP's IDR register */
209 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
210 #define AP_REG_IDR_REVISION_SHIFT (28)
211 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
212 #define AP_REG_IDR_DESIGNER_SHIFT (17)
213 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
214 #define AP_REG_IDR_CLASS_SHIFT (13)
215 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
216 #define AP_REG_IDR_VARIANT_SHIFT (4)
217 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
218 #define AP_REG_IDR_TYPE_SHIFT (0)
220 #define AP_REG_IDR_CLASS_NONE (0x0)
221 #define AP_REG_IDR_CLASS_COM (0x1)
222 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
224 #define AP_REG_IDR_VALUE(d, c, t) (\
225 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
226 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
227 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
230 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
232 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
233 enum swd_special_seq
{
244 * This represents an ARM Debug Interface (v5) Access Port (AP).
245 * Most common is a MEM-AP, for memory access.
249 * DAP this AP belongs to.
251 struct adiv5_dap
*dap
;
254 * ADIv5: Number of this AP (0~255)
255 * ADIv6: Base address of this AP (4k aligned)
256 * TODO: to be more coherent, it should be renamed apsel
261 * Default value for (MEM-AP) AP_REG_CSW register.
263 uint32_t csw_default
;
266 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
267 * configure an access mode, such as autoincrementing AP_REG_TAR during
268 * word access. "-1" indicates no cached value.
273 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
274 * configure the address being read or written
275 * "-1" indicates no cached value.
277 target_addr_t tar_value
;
280 * Configures how many extra tck clocks are added after starting a
281 * MEM-AP access before we try to read its status (and/or result).
283 uint32_t memaccess_tck
;
285 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
286 uint32_t tar_autoincr_block
;
288 /* true if packed transfers are supported by the MEM-AP */
289 bool packed_transfers
;
291 /* true if unaligned memory access is not supported by the MEM-AP */
292 bool unaligned_access_bad
;
294 /* true if tar_value is in sync with TAR register */
297 /* MEM AP configuration register indicating LPAE support */
300 /* references counter */
301 unsigned int refcount
;
303 /* AP referenced during config. Never put it, even when refcount reaches zero */
304 bool config_ap_never_release
;
309 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
310 * A DAP has two types of component: one Debug Port (DP), which is a
311 * transport agent; and at least one Access Port (AP), controlling
314 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
315 * Accordingly, this interface is responsible for hiding the transport
316 * differences so upper layer code can largely ignore them.
318 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
319 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
320 * a choice made at board design time (by only using the SWD pins), or
321 * as part of setting up a debug session (if all the dual-role JTAG/SWD
322 * signals are available).
325 const struct dap_ops
*ops
;
327 /* dap transaction list for WAIT support */
328 struct list_head cmd_journal
;
330 /* pool for dap_cmd objects */
331 struct list_head cmd_pool
;
333 /* number of dap_cmd objects in the pool */
334 size_t cmd_pool_size
;
336 struct jtag_tap
*tap
;
338 uint32_t dp_ctrl_stat
;
340 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
342 /* The current manually selected AP by the "dap apsel" command */
345 /** Cache for DP SELECT and SELECT1 (ADIv6) register. */
347 /** Validity of DP SELECT cache. false will force register rewrite */
349 bool select1_valid
; /* ADIv6 only */
351 * Partial DPBANKSEL validity for SWD only.
352 * ADIv6 line reset sets DP SELECT DPBANKSEL to zero,
354 * We can rely on it for the banked DP register 0 also on ADIv5
355 * as ADIv5 has no mapping for DP reg 0 - it is always DPIDR.
356 * It is important to avoid setting DP SELECT in connection
357 * reset state before reading DPIDR.
359 bool select_dpbanksel_valid
;
361 /* information about current pending SWjDP-AHBAP transaction */
365 * Holds the pointer to the destination word for the last queued read,
366 * for use with posted AP read sequence optimization.
370 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
371 * despite lack of support in the ARMv7 architecture. Memory access through
372 * the AHB-AP has strange byte ordering these processors, and we need to
373 * swizzle appropriately. */
374 bool ti_be_32_quirks
;
376 /* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios.
377 * The work around is to repeat the data in all 4 bytes of DRW */
381 * STLINK adapter need to know if last AP operation was read or write, and
382 * in case of write has to flush it with a dummy read from DP_RDBUFF
384 bool stlink_flush_ap_write
;
387 * Signals that an attempt to reestablish communication afresh
388 * should be performed before the next access.
392 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
393 * do not set this bit until later in the bringup sequence */
394 bool ignore_syspwrupack
;
396 /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
397 uint32_t multidrop_targetsel
;
398 /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
399 bool multidrop_dp_id_valid
;
400 /** TINSTANCE field of multidrop_targetsel has been configured */
401 bool multidrop_instance_id_valid
;
404 * Record if enter in SWD required passing through DORMANT
406 bool switch_through_dormant
;
408 /** Indicates ADI version (5, 6 or 0 for unknown) being used */
409 unsigned int adi_version
;
411 /* ADIv6 only field indicating ROM Table address size */
416 * Transport-neutral representation of queued DAP transactions, supporting
417 * both JTAG and SWD transports. All submitted transactions are logically
418 * queued, until the queue is executed by run(). Some implementations might
419 * execute transactions as soon as they're submitted, but no status is made
420 * available until run().
423 /** Optional; called once on the first enabled dap before connecting */
424 int (*pre_connect_init
)(struct adiv5_dap
*dap
);
426 /** connect operation for SWD */
427 int (*connect
)(struct adiv5_dap
*dap
);
429 /** send a sequence to the DAP */
430 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
432 /** DP register read. */
433 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
435 /** DP register write. */
436 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
439 /** AP register read. */
440 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
442 /** AP register write. */
443 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
446 /** AP operation abort. */
447 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
449 /** Executes all queued DAP operations. */
450 int (*run
)(struct adiv5_dap
*dap
);
452 /** Executes all queued DAP operations but doesn't check
453 * sticky error conditions */
454 int (*sync
)(struct adiv5_dap
*dap
);
456 /** Optional; called at OpenOCD exit */
457 void (*quit
)(struct adiv5_dap
*dap
);
464 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
465 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
466 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
467 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
468 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
469 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
470 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
471 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
472 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
475 extern const struct dap_ops jtag_dp_ops
;
476 extern const struct dap_ops swd_dap_ops
;
478 /* Check the ap->cfg_reg Long Address field (bit 1)
480 * 0b0: The AP only supports physical addresses 32 bits or smaller
481 * 0b1: The AP supports physical addresses larger than 32 bits
483 * @param ap The AP used for reading.
485 * @return true for 64 bit, false for 32 bit
487 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
489 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
493 * Check if DAP is ADIv6
495 * @param dap The DAP to test
497 * @return true for ADIv6, false for either ADIv5 or unknown version
499 static inline bool is_adiv6(const struct adiv5_dap
*dap
)
501 return dap
->adi_version
== 6;
505 * Send an adi-v5 sequence to the DAP.
507 * @param dap The DAP used for reading.
508 * @param seq The sequence to send.
510 * @return ERROR_OK for success, else a fault code.
512 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
513 enum swd_special_seq seq
)
516 return dap
->ops
->send_sequence(dap
, seq
);
520 * Queue a DP register read.
521 * Note that not all DP registers are readable; also, that JTAG and SWD
522 * have slight differences in DP register support.
524 * @param dap The DAP used for reading.
525 * @param reg The two-bit number of the DP register being read.
526 * @param data Pointer saying where to store the register's value
527 * (in host endianness).
529 * @return ERROR_OK for success, else a fault code.
531 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
532 unsigned reg
, uint32_t *data
)
535 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
539 * Queue a DP register write.
540 * Note that not all DP registers are writable; also, that JTAG and SWD
541 * have slight differences in DP register support.
543 * @param dap The DAP used for writing.
544 * @param reg The two-bit number of the DP register being written.
545 * @param data Value being written (host endianness)
547 * @return ERROR_OK for success, else a fault code.
549 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
550 unsigned reg
, uint32_t data
)
553 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
557 * Queue an AP register read.
559 * @param ap The AP used for reading.
560 * @param reg The number of the AP register being read.
561 * @param data Pointer saying where to store the register's value
562 * (in host endianness).
564 * @return ERROR_OK for success, else a fault code.
566 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
567 unsigned reg
, uint32_t *data
)
569 assert(ap
->dap
->ops
);
570 if (ap
->refcount
== 0) {
572 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
574 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
578 * Queue an AP register write.
580 * @param ap The AP used for writing.
581 * @param reg The number of the AP register being written.
582 * @param data Value being written (host endianness)
584 * @return ERROR_OK for success, else a fault code.
586 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
587 unsigned reg
, uint32_t data
)
589 assert(ap
->dap
->ops
);
590 if (ap
->refcount
== 0) {
592 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" used without get", ap
->ap_num
);
594 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
598 * Queue an AP abort operation. The current AP transaction is aborted,
599 * including any update of the transaction counter. The AP is left in
600 * an unknown state (so it must be re-initialized). For use only after
601 * the AP has reported WAIT status for an extended period.
603 * @param dap The DAP used for writing.
604 * @param ack Pointer to where transaction status will be stored.
606 * @return ERROR_OK for success, else a fault code.
608 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
611 return dap
->ops
->queue_ap_abort(dap
, ack
);
615 * Perform all queued DAP operations, and clear any errors posted in the
616 * CTRL_STAT register when they are done. Note that if more than one AP
617 * operation will be queued, one of the first operations in the queue
618 * should probably enable CORUNDETECT in the CTRL/STAT register.
620 * @param dap The DAP used.
622 * @return ERROR_OK for success, else a fault code.
624 static inline int dap_run(struct adiv5_dap
*dap
)
627 return dap
->ops
->run(dap
);
630 static inline int dap_sync(struct adiv5_dap
*dap
)
634 return dap
->ops
->sync(dap
);
638 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
643 retval
= dap_queue_dp_read(dap
, reg
, value
);
644 if (retval
!= ERROR_OK
)
650 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
651 uint32_t mask
, uint32_t value
, int timeout
)
654 assert((value
& mask
) == value
);
658 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
661 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
665 if ((regval
& mask
) == value
)
672 LOG_DEBUG("DAP: poll %x timeout", reg
);
679 /* Queued MEM-AP memory mapped single word transfers. */
680 int mem_ap_read_u32(struct adiv5_ap
*ap
,
681 target_addr_t address
, uint32_t *value
);
682 int mem_ap_write_u32(struct adiv5_ap
*ap
,
683 target_addr_t address
, uint32_t value
);
685 /* Synchronous MEM-AP memory mapped single word transfers. */
686 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
687 target_addr_t address
, uint32_t *value
);
688 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
689 target_addr_t address
, uint32_t value
);
691 /* Synchronous MEM-AP memory mapped bus block transfers. */
692 int mem_ap_read_buf(struct adiv5_ap
*ap
,
693 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
694 int mem_ap_write_buf(struct adiv5_ap
*ap
,
695 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
697 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
698 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
699 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
700 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
701 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
703 /* Initialisation of the debug system, power domains and registers */
704 int dap_dp_init(struct adiv5_dap
*dap
);
705 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
706 int mem_ap_init(struct adiv5_ap
*ap
);
708 /* Invalidate cached DP select and cached TAR and CSW of all APs */
709 void dap_invalidate_cache(struct adiv5_dap
*dap
);
711 /* read ADIv6 baseptr register */
712 int adiv6_dap_read_baseptr(struct command_invocation
*cmd
, struct adiv5_dap
*dap
, target_addr_t
*baseptr
);
714 /* test if ap_num is valid, based on current knowledge of dap */
715 bool is_ap_num_valid(struct adiv5_dap
*dap
, uint64_t ap_num
);
717 /* Probe Access Ports to find a particular type. Increment AP refcount */
718 int dap_find_get_ap(struct adiv5_dap
*dap
,
719 enum ap_type type_to_find
,
720 struct adiv5_ap
**ap_out
);
722 /* Return AP with specified ap_num. Increment AP refcount */
723 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
725 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
726 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, uint64_t ap_num
);
728 /* Decrement AP refcount and release the AP when refcount reaches zero */
729 int dap_put_ap(struct adiv5_ap
*ap
);
731 /** Check if SWD multidrop configuration is valid */
732 static inline bool dap_is_multidrop(struct adiv5_dap
*dap
)
734 return dap
->multidrop_dp_id_valid
&& dap
->multidrop_instance_id_valid
;
737 /* Lookup CoreSight component */
738 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
739 uint8_t type
, target_addr_t
*addr
, int32_t idx
);
743 /* Put debug link into SWD mode */
744 int dap_to_swd(struct adiv5_dap
*dap
);
746 /* Put debug link into JTAG mode */
747 int dap_to_jtag(struct adiv5_dap
*dap
);
749 extern const struct command_registration dap_instance_commands
[];
751 struct arm_dap_object
;
752 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
753 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
754 extern int dap_info_command(struct command_invocation
*cmd
,
755 struct adiv5_ap
*ap
);
756 extern int dap_register_commands(struct command_context
*cmd_ctx
);
757 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
758 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
759 extern int dap_cleanup_all(void);
761 struct adiv5_private_config
{
763 struct adiv5_dap
*dap
;
766 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
767 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
769 struct adiv5_mem_ap_spot
{
770 struct adiv5_dap
*dap
;
775 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
776 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
777 struct jim_getopt_info
*goi
);
779 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)