1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "armv4_5_mmu.h"
28 uint32_t armv4mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, uint32_t va
, int *type
, uint32_t *cb
, int *domain
, uint32_t *ap
);
30 char* armv4_5_mmu_page_type_names
[] =
32 "section", "large page", "small page", "tiny page"
35 uint32_t armv4_5_mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, uint32_t va
, int *type
, uint32_t *cb
, int *domain
, uint32_t *ap
)
37 uint32_t first_lvl_descriptor
= 0x0;
38 uint32_t second_lvl_descriptor
= 0x0;
39 uint32_t ttb
= armv4_5_mmu
->get_ttb(target
);
41 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
42 (ttb
& 0xffffc000) | ((va
& 0xfff00000) >> 18),
43 4, 1, (uint8_t*)&first_lvl_descriptor
);
44 first_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t*)&first_lvl_descriptor
);
46 LOG_DEBUG("1st lvl desc: %8.8" PRIx32
"", first_lvl_descriptor
);
48 if ((first_lvl_descriptor
& 0x3) == 0)
51 LOG_ERROR("Address translation failure");
52 return ERROR_TARGET_TRANSLATION_FAULT
;
55 if (!armv4_5_mmu
->has_tiny_pages
&& ((first_lvl_descriptor
& 0x3) == 3))
58 LOG_ERROR("Address translation failure");
59 return ERROR_TARGET_TRANSLATION_FAULT
;
62 /* domain is always specified in bits 8-5 */
63 *domain
= (first_lvl_descriptor
& 0x1e0) >> 5;
65 if ((first_lvl_descriptor
& 0x3) == 2)
67 /* section descriptor */
68 *type
= ARMV4_5_SECTION
;
69 *cb
= (first_lvl_descriptor
& 0xc) >> 2;
70 *ap
= (first_lvl_descriptor
& 0xc00) >> 10;
71 return (first_lvl_descriptor
& 0xfff00000) | (va
& 0x000fffff);
74 if ((first_lvl_descriptor
& 0x3) == 1)
76 /* coarse page table */
77 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
78 (first_lvl_descriptor
& 0xfffffc00) | ((va
& 0x000ff000) >> 10),
79 4, 1, (uint8_t*)&second_lvl_descriptor
);
81 else if ((first_lvl_descriptor
& 0x3) == 3)
84 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
85 (first_lvl_descriptor
& 0xfffff000) | ((va
& 0x000ffc00) >> 8),
86 4, 1, (uint8_t*)&second_lvl_descriptor
);
89 second_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t*)&second_lvl_descriptor
);
91 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32
"", second_lvl_descriptor
);
93 if ((second_lvl_descriptor
& 0x3) == 0)
96 LOG_ERROR("Address translation failure");
97 return ERROR_TARGET_TRANSLATION_FAULT
;
100 /* cacheable/bufferable is always specified in bits 3-2 */
101 *cb
= (second_lvl_descriptor
& 0xc) >> 2;
103 if ((second_lvl_descriptor
& 0x3) == 1)
105 /* large page descriptor */
106 *type
= ARMV4_5_LARGE_PAGE
;
107 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
108 return (second_lvl_descriptor
& 0xffff0000) | (va
& 0x0000ffff);
111 if ((second_lvl_descriptor
& 0x3) == 2)
113 /* small page descriptor */
114 *type
= ARMV4_5_SMALL_PAGE
;
115 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
116 return (second_lvl_descriptor
& 0xfffff000) | (va
& 0x00000fff);
119 if ((second_lvl_descriptor
& 0x3) == 3)
121 /* tiny page descriptor */
122 *type
= ARMV4_5_TINY_PAGE
;
123 *ap
= (second_lvl_descriptor
& 0x30) >> 4;
124 return (second_lvl_descriptor
& 0xfffffc00) | (va
& 0x000003ff);
127 /* should not happen */
129 LOG_ERROR("Address translation failure");
130 return ERROR_TARGET_TRANSLATION_FAULT
;
133 int armv4_5_mmu_read_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
137 if (target
->state
!= TARGET_HALTED
)
138 return ERROR_TARGET_NOT_HALTED
;
140 /* disable MMU and data (or unified) cache */
141 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
143 retval
= armv4_5_mmu
->read_memory(target
, address
, size
, count
, buffer
);
145 /* reenable MMU / cache */
146 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
147 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
148 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
153 int armv4_5_mmu_write_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
157 if (target
->state
!= TARGET_HALTED
)
158 return ERROR_TARGET_NOT_HALTED
;
160 /* disable MMU and data (or unified) cache */
161 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
163 retval
= armv4_5_mmu
->write_memory(target
, address
, size
, count
, buffer
);
165 /* reenable MMU / cache */
166 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
167 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
168 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
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