1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2006 by Magnus Lundin *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "replacements.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 char* armv7m_mode_strings
[] =
47 char* armv7m_state_strings
[] =
52 char* armv7m_exception_strings
[] =
54 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
55 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 char* armv7m_core_reg_list
[] =
60 /* Registers accessed through core debug */
61 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 /* Registers accessed through MSR instructions */
65 // "apsr", "iapsr", "ipsr", "epsr",
66 "primask", "basepri", "faultmask", "control"
69 char* armv7m_core_dbgreg_list
[] =
71 /* Registers accessed through core debug */
72 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
75 /* Registers accessed through MSR instructions */
76 // "dbg_apsr", "iapsr", "ipsr", "epsr",
77 "primask", "basepri", "faultmask", "dbg_control"
80 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
82 reg_t armv7m_gdb_dummy_fp_reg
=
84 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
87 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
89 /* CORE_GP are accesible using the core debug registers */
90 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
91 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
107 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
108 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
109 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
111 /* CORE_SP are accesible using MSR and MRS instructions */
112 // {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
113 // {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
114 // {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
115 // {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
117 {0x10, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
118 {0x11, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
119 {0x13, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
120 {0x14, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
123 int armv7m_core_reg_arch_type
= -1;
125 /* Keep different contexts for the process being debugged and debug algorithms */
126 enum armv7m_runcontext
armv7m_get_context(target_t
*target
)
128 /* get pointers to arch-specific information */
129 armv7m_common_t
*armv7m
= target
->arch_info
;
131 if (armv7m
->process_context
== armv7m
->core_cache
)
132 return ARMV7M_PROCESS_CONTEXT
;
133 if (armv7m
->debug_context
== armv7m
->core_cache
)
134 return ARMV7M_DEBUG_CONTEXT
;
136 ERROR("Invalid runcontext");
140 int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
)
143 /* get pointers to arch-specific information */
144 armv7m_common_t
*armv7m
= target
->arch_info
;
146 if ((target
->state
!= TARGET_HALTED
) && (target
->state
!= TARGET_RESET
))
148 WARNING("target not halted, switch context ");
149 return ERROR_TARGET_NOT_HALTED
;
152 if (new_ctx
== armv7m_get_context(target
))
157 case ARMV7M_PROCESS_CONTEXT
:
158 armv7m
->core_cache
= armv7m
->process_context
;
160 case ARMV7M_DEBUG_CONTEXT
:
161 armv7m
->core_cache
= armv7m
->debug_context
;
164 ERROR("Invalid runcontext");
167 /* Mark registers in new context as dirty to force reload when run */
169 for (i
= 0; i
< armv7m
->core_cache
->num_regs
-1; i
++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
171 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
177 int armv7m_restore_context(target_t
*target
)
181 /* get pointers to arch-specific information */
182 armv7m_common_t
*armv7m
= target
->arch_info
;
186 if (armv7m
->pre_restore_context
)
187 armv7m
->pre_restore_context(target
);
189 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
191 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
193 armv7m
->write_core_reg(target
, i
);
197 if (armv7m
->post_restore_context
)
198 armv7m
->post_restore_context(target
);
204 /* Core state functions */
206 char *armv7m_exception_string(int number
)
208 if ((number
< 0) | (number
> 511))
209 return "Invalid exception";
211 return armv7m_exception_strings
[number
];
212 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
216 int armv7m_get_core_reg(reg_t
*reg
)
219 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
220 target_t
*target
= armv7m_reg
->target
;
221 armv7m_common_t
*armv7m_target
= target
->arch_info
;
223 if (target
->state
!= TARGET_HALTED
)
225 return ERROR_TARGET_NOT_HALTED
;
228 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
233 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
235 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
236 target_t
*target
= armv7m_reg
->target
;
237 u32 value
= buf_get_u32(buf
, 0, 32);
239 if (target
->state
!= TARGET_HALTED
)
241 return ERROR_TARGET_NOT_HALTED
;
244 buf_set_u32(reg
->value
, 0, 32, value
);
251 int armv7m_read_core_reg(struct target_s
*target
, int num
)
255 armv7m_core_reg_t
* armv7m_core_reg
;
257 /* get pointers to arch-specific information */
258 armv7m_common_t
*armv7m
= target
->arch_info
;
260 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
261 return ERROR_INVALID_ARGUMENTS
;
263 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
264 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
265 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
266 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
267 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
272 int armv7m_write_core_reg(struct target_s
*target
, int num
)
276 armv7m_core_reg_t
*armv7m_core_reg
;
278 /* get pointers to arch-specific information */
279 armv7m_common_t
*armv7m
= target
->arch_info
;
281 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
282 return ERROR_INVALID_ARGUMENTS
;
284 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
285 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
286 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
287 if (retval
!= ERROR_OK
)
289 ERROR("JTAG failure");
290 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
291 return ERROR_JTAG_DEVICE_ERROR
;
293 DEBUG("write core reg %i value 0x%x", num
, reg_value
);
294 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
295 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
300 int armv7m_invalidate_core_regs(target_t
*target
)
302 /* get pointers to arch-specific information */
303 armv7m_common_t
*armv7m
= target
->arch_info
;
306 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
308 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
309 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
315 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
317 /* get pointers to arch-specific information */
318 armv7m_common_t
*armv7m
= target
->arch_info
;
321 if (target
->state
!= TARGET_HALTED
)
323 return ERROR_TARGET_NOT_HALTED
;
327 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
329 /* TODOLATER correct list of registers, names ? */
330 for (i
= 0; i
< *reg_list_size
; i
++)
332 if (i
< ARMV7NUMCOREREGS
)
333 (*reg_list
)[i
] = &armv7m
->process_context
->reg_list
[i
];
334 //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
336 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
338 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
339 armv7m
->process_context
->reg_list
[15].value
[0] |= 1;
340 (*reg_list
)[25] = &armv7m
->process_context
->reg_list
[ARMV7M_xPSR
];
344 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
346 // get pointers to arch-specific information
347 armv7m_common_t
*armv7m
= target
->arch_info
;
348 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
349 enum armv7m_state core_state
= armv7m
->core_state
;
350 enum armv7m_mode core_mode
= armv7m
->core_mode
;
351 int retval
= ERROR_OK
;
353 int exit_breakpoint_size
= 0;
356 armv7m
->core_state
= core_state
;
357 armv7m
->core_mode
= core_mode
;
359 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
361 ERROR("current target isn't an ARMV7M target");
362 return ERROR_TARGET_INVALID
;
365 if (target
->state
!= TARGET_HALTED
)
367 WARNING("target not halted");
368 return ERROR_TARGET_NOT_HALTED
;
371 /* refresh core register cache */
372 /* Not needed if core register cache is always consistent with target process state */
373 armv7m_use_context(target
, ARMV7M_DEBUG_CONTEXT
);
375 for (i
= 0; i
< num_mem_params
; i
++)
377 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
380 for (i
= 0; i
< num_reg_params
; i
++)
382 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
387 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
391 if (reg
->size
!= reg_params
[i
].size
)
393 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
397 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
398 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
401 /* ARMV7M always runs in Thumb state */
402 exit_breakpoint_size
= 2;
403 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_SOFT
)) != ERROR_OK
)
405 ERROR("can't add breakpoint to finish algorithm execution");
406 return ERROR_TARGET_FAILURE
;
409 /* This code relies on the target specific resume() and poll()->debug_entry()
410 sequence to write register values to the processor and the read them back */
411 target
->type
->resume(target
, 0, entry_point
, 1, 1);
412 target
->type
->poll(target
);
414 while (target
->state
!= TARGET_HALTED
)
417 target
->type
->poll(target
);
418 if ((timeout_ms
-= 5) <= 0)
420 ERROR("timeout waiting for algorithm to complete, trying to halt target");
421 target
->type
->halt(target
);
423 while (target
->state
!= TARGET_HALTED
)
426 target
->type
->poll(target
);
427 if ((timeout_ms
-= 10) <= 0)
429 ERROR("target didn't reenter debug state, exiting");
433 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
434 DEBUG("failed algoritm halted at 0x%x ", pc
);
435 retval
= ERROR_TARGET_TIMEOUT
;
439 breakpoint_remove(target
, exit_point
);
441 /* Read memory values to mem_params[] */
442 for (i
= 0; i
< num_mem_params
; i
++)
444 if (mem_params
[i
].direction
!= PARAM_OUT
)
445 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
448 /* Copy core register values to reg_params[] */
449 for (i
= 0; i
< num_reg_params
; i
++)
451 if (reg_params
[i
].direction
!= PARAM_OUT
)
453 reg_t
*reg
= register_get_by_name(armv7m
->debug_context
, reg_params
[i
].reg_name
, 0);
457 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
461 if (reg
->size
!= reg_params
[i
].size
)
463 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
467 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
474 int armv7m_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
476 /* get pointers to arch-specific information */
477 armv7m_common_t
*armv7m
= target
->arch_info
;
479 snprintf(buf
, buf_size
,
480 "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
481 armv7m_state_strings
[armv7m
->core_state
],
482 target_debug_reason_strings
[target
->debug_reason
],
483 armv7m_mode_strings
[armv7m
->core_mode
],
484 armv7m_exception_string(armv7m
->exception_number
),
485 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
486 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
491 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
493 /* get pointers to arch-specific information */
494 armv7m_common_t
*armv7m
= target
->arch_info
;
496 int num_regs
= ARMV7NUMCOREREGS
;
497 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
498 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
499 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
500 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
503 if (armv7m_core_reg_arch_type
== -1)
504 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
506 /* Build the process context cache */
507 cache
->name
= "arm v7m registers";
509 cache
->reg_list
= reg_list
;
510 cache
->num_regs
= num_regs
;
512 armv7m
->core_cache
= cache
;
513 armv7m
->process_context
= cache
;
515 for (i
= 0; i
< num_regs
; i
++)
517 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
518 arch_info
[i
].target
= target
;
519 arch_info
[i
].armv7m_common
= armv7m
;
520 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
521 reg_list
[i
].size
= 32;
522 reg_list
[i
].value
= calloc(1, 4);
523 reg_list
[i
].dirty
= 0;
524 reg_list
[i
].valid
= 0;
525 reg_list
[i
].bitfield_desc
= NULL
;
526 reg_list
[i
].num_bitfields
= 0;
527 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
528 reg_list
[i
].arch_info
= &arch_info
[i
];
531 /* Build the debug context cache*/
532 cache
= malloc(sizeof(reg_cache_t
));
533 reg_list
= malloc(sizeof(reg_t
) * num_regs
);
535 cache
->name
= "arm v7m debug registers";
537 cache
->reg_list
= reg_list
;
538 cache
->num_regs
= num_regs
;
539 armv7m
->debug_context
= cache
;
540 armv7m
->process_context
->next
= cache
;
542 for (i
= 0; i
< num_regs
; i
++)
544 reg_list
[i
].name
= armv7m_core_dbgreg_list
[i
];
545 reg_list
[i
].size
= 32;
546 reg_list
[i
].value
= calloc(1, 4);
547 reg_list
[i
].dirty
= 0;
548 reg_list
[i
].valid
= 0;
549 reg_list
[i
].bitfield_desc
= NULL
;
550 reg_list
[i
].num_bitfields
= 0;
551 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
552 reg_list
[i
].arch_info
= &arch_info
[i
];
558 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
560 armv7m_build_reg_cache(target
);
565 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
567 /* register arch-specific functions */
569 target
->arch_info
= armv7m
;
570 armv7m
->core_state
= ARMV7M_STATE_THUMB
;
571 armv7m
->read_core_reg
= armv7m_read_core_reg
;
572 armv7m
->write_core_reg
= armv7m_write_core_reg
;
577 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
582 int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
584 working_area_t
*crc_algorithm
;
585 armv7m_algorithm_t armv7m_info
;
586 reg_param_t reg_params
[2];
589 u16 cortex_m3_crc_code
[] = {
590 0x4602, /* mov r2, r0 */
591 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
592 0x460B, /* mov r3, r1 */
593 0xF04F, 0x0400, /* mov r4, #0 */
594 0xE013, /* b ncomp */
596 0x5D11, /* ldrb r1, [r2, r4] */
597 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
598 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
600 0xF04F, 0x0500, /* mov r5, #0 */
602 0x2800, /* cmp r0, #0 */
603 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
604 0xF105, 0x0501, /* add r5, r5, #1 */
605 0x4630, /* mov r0, r6 */
607 0xEA86, 0x0007, /* eor r0, r6, r7 */
608 0x2D08, /* cmp r5, #8 */
609 0xD1F4, /* bne loop */
611 0xF104, 0x0401, /* add r4, r4, #1 */
613 0x429C, /* cmp r4, r3 */
614 0xD1E9, /* bne nbyte */
617 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
622 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
624 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
627 /* convert flash writing code into a buffer in target endianness */
628 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(u16
)); i
++)
629 target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(u16
), cortex_m3_crc_code
[i
]);
631 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
632 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
633 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
635 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
636 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
638 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
639 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
641 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
642 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
644 ERROR("error executing cortex_m3 crc algorithm");
645 destroy_reg_param(®_params
[0]);
646 destroy_reg_param(®_params
[1]);
647 target_free_working_area(target
, crc_algorithm
);
651 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
653 destroy_reg_param(®_params
[0]);
654 destroy_reg_param(®_params
[1]);
656 target_free_working_area(target
, crc_algorithm
);
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