1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program; if not, write to the *
38 * Free Software Foundation, Inc., *
39 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
41 * Cortex-A8(tm) TRM, ARM DDI 0344H *
42 * Cortex-A9(tm) TRM, ARM DDI 0407F *
43 * Cortex-A4(tm) TRM, ARM DDI 0363E *
44 * Cortex-A15(tm)TRM, ARM DDI 0438C *
46 ***************************************************************************/
52 #include "breakpoints.h"
55 #include "target_request.h"
56 #include "target_type.h"
57 #include "arm_opcodes.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
77 static int cortex_a_virt2phys(struct target
*target
,
78 uint32_t virt
, uint32_t *phys
);
79 static int cortex_a_read_apb_ab_memory(struct target
*target
,
80 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
83 /* restore cp15_control_reg at resume */
84 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
86 int retval
= ERROR_OK
;
87 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
88 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
90 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
91 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
92 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
93 retval
= armv7a
->arm
.mcr(target
, 15,
96 cortex_a
->cp15_control_reg
);
102 * Set up ARM core for memory access.
103 * If !phys_access, switch to SVC mode and make sure MMU is on
104 * If phys_access, switch off mmu
106 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
108 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
111 if (phys_access
== 0) {
112 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
113 cortex_a_mmu(target
, &mmu_enabled
);
115 cortex_a_mmu_modify(target
, 1);
117 cortex_a_mmu(target
, &mmu_enabled
);
119 cortex_a_mmu_modify(target
, 0);
125 * Restore ARM core after memory access.
126 * If !phys_access, switch to previous mode
127 * If phys_access, restore MMU setting
129 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
131 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
133 if (phys_access
== 0) {
134 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
137 cortex_a_mmu(target
, &mmu_enabled
);
139 cortex_a_mmu_modify(target
, 1);
145 /* modify cp15_control_reg in order to enable or disable mmu for :
146 * - virt2phys address conversion
147 * - read or write memory in phys or virt address */
148 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
150 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
151 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
152 int retval
= ERROR_OK
;
156 /* if mmu enabled at target stop and mmu not enable */
157 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
158 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
161 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
162 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
166 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
167 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
173 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
174 enable
? "enable mmu" : "disable mmu",
175 cortex_a
->cp15_control_reg_curr
);
177 retval
= armv7a
->arm
.mcr(target
, 15,
180 cortex_a
->cp15_control_reg_curr
);
186 * Cortex-A Basic debug access, very low level assumes state is saved
188 static int cortex_a8_init_debug_access(struct target
*target
)
190 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
191 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
196 /* Unlocking the debug registers for modification
197 * The debugport might be uninitialised so try twice */
198 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
199 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
200 if (retval
!= ERROR_OK
) {
202 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
203 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
204 if (retval
== ERROR_OK
)
206 "Locking debug access failed on first, but succeeded on second try.");
213 * Cortex-A Basic debug access, very low level assumes state is saved
215 static int cortex_a_init_debug_access(struct target
*target
)
217 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
218 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
221 uint32_t cortex_part_num
;
222 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
225 cortex_part_num
= (cortex_a
->cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >>
226 CORTEX_A_MIDR_PARTNUM_SHIFT
;
228 switch (cortex_part_num
) {
229 case CORTEX_A7_PARTNUM
:
230 case CORTEX_A15_PARTNUM
:
231 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
232 armv7a
->debug_base
+ CPUDBG_OSLSR
,
234 if (retval
!= ERROR_OK
)
237 LOG_DEBUG("DBGOSLSR 0x%" PRIx32
, dbg_osreg
);
239 if (dbg_osreg
& CPUDBG_OSLAR_LK_MASK
)
240 /* Unlocking the DEBUG OS registers for modification */
241 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
242 armv7a
->debug_base
+ CPUDBG_OSLAR
,
246 case CORTEX_A5_PARTNUM
:
247 case CORTEX_A8_PARTNUM
:
248 case CORTEX_A9_PARTNUM
:
250 retval
= cortex_a8_init_debug_access(target
);
253 if (retval
!= ERROR_OK
)
255 /* Clear Sticky Power Down status Bit in PRSR to enable access to
256 the registers in the Core Power Domain */
257 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
258 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
259 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
261 if (retval
!= ERROR_OK
)
264 /* Disable cacheline fills and force cache write-through in debug state */
265 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
266 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
267 if (retval
!= ERROR_OK
)
270 /* Disable TLB lookup and refill/eviction in debug state */
271 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
272 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
273 if (retval
!= ERROR_OK
)
276 /* Enabling of instruction execution in debug mode is done in debug_entry code */
278 /* Resync breakpoint registers */
280 /* Since this is likely called from init or reset, update target state information*/
281 return cortex_a_poll(target
);
284 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
286 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
287 * Writes final value of DSCR into *dscr. Pass force to force always
288 * reading DSCR at least once. */
289 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
290 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
291 long long then
= timeval_ms();
292 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
294 int retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
295 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
296 if (retval
!= ERROR_OK
) {
297 LOG_ERROR("Could not read DSCR register");
300 if (timeval_ms() > then
+ 1000) {
301 LOG_ERROR("Timeout waiting for InstrCompl=1");
308 /* To reduce needless round-trips, pass in a pointer to the current
309 * DSCR value. Initialize it to zero if you just need to know the
310 * value on return from this function; or DSCR_INSTR_COMP if you
311 * happen to know that no instruction is pending.
313 static int cortex_a_exec_opcode(struct target
*target
,
314 uint32_t opcode
, uint32_t *dscr_p
)
318 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
319 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
321 dscr
= dscr_p
? *dscr_p
: 0;
323 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
325 /* Wait for InstrCompl bit to be set */
326 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
327 if (retval
!= ERROR_OK
)
330 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
331 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
332 if (retval
!= ERROR_OK
)
335 long long then
= timeval_ms();
337 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
338 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
339 if (retval
!= ERROR_OK
) {
340 LOG_ERROR("Could not read DSCR register");
343 if (timeval_ms() > then
+ 1000) {
344 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
347 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
355 /**************************************************************************
356 Read core register with very few exec_opcode, fast but needs work_area.
357 This can cause problems with MMU active.
358 **************************************************************************/
359 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
362 int retval
= ERROR_OK
;
363 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
364 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
366 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
367 if (retval
!= ERROR_OK
)
369 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
370 if (retval
!= ERROR_OK
)
372 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
373 if (retval
!= ERROR_OK
)
376 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
,
377 (uint8_t *)(®file
[1]), 4, 15, address
);
382 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
383 uint32_t *value
, int regnum
)
385 int retval
= ERROR_OK
;
386 uint8_t reg
= regnum
&0xFF;
388 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
389 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
395 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
396 retval
= cortex_a_exec_opcode(target
,
397 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
399 if (retval
!= ERROR_OK
)
401 } else if (reg
== 15) {
402 /* "MOV r0, r15"; then move r0 to DCCTX */
403 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
404 if (retval
!= ERROR_OK
)
406 retval
= cortex_a_exec_opcode(target
,
407 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
409 if (retval
!= ERROR_OK
)
412 /* "MRS r0, CPSR" or "MRS r0, SPSR"
413 * then move r0 to DCCTX
415 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
416 if (retval
!= ERROR_OK
)
418 retval
= cortex_a_exec_opcode(target
,
419 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
421 if (retval
!= ERROR_OK
)
425 /* Wait for DTRRXfull then read DTRRTX */
426 long long then
= timeval_ms();
427 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
428 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
429 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
430 if (retval
!= ERROR_OK
)
432 if (timeval_ms() > then
+ 1000) {
433 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
438 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
439 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
440 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
445 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
446 uint32_t value
, int regnum
)
448 int retval
= ERROR_OK
;
449 uint8_t Rd
= regnum
&0xFF;
451 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
452 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
454 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
456 /* Check that DCCRX is not full */
457 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
458 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
459 if (retval
!= ERROR_OK
)
461 if (dscr
& DSCR_DTR_RX_FULL
) {
462 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
463 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
464 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
466 if (retval
!= ERROR_OK
)
473 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
474 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
475 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
476 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
477 if (retval
!= ERROR_OK
)
481 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
482 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
485 if (retval
!= ERROR_OK
)
487 } else if (Rd
== 15) {
488 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
491 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
493 if (retval
!= ERROR_OK
)
495 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
496 if (retval
!= ERROR_OK
)
499 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
500 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
502 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
504 if (retval
!= ERROR_OK
)
506 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
508 if (retval
!= ERROR_OK
)
511 /* "Prefetch flush" after modifying execution status in CPSR */
513 retval
= cortex_a_exec_opcode(target
,
514 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
516 if (retval
!= ERROR_OK
)
524 /* Write to memory mapped registers directly with no cache or mmu handling */
525 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
530 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
531 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
533 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, address
, value
);
539 * Cortex-A implementation of Debug Programmer's Model
541 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
542 * so there's no need to poll for it before executing an instruction.
544 * NOTE that in several of these cases the "stall" mode might be useful.
545 * It'd let us queue a few operations together... prepare/finish might
546 * be the places to enable/disable that mode.
549 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
551 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
554 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
556 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
557 return mem_ap_sel_write_u32(a
->armv7a_common
.arm
.dap
,
558 a
->armv7a_common
.debug_ap
, a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
561 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
564 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
565 uint32_t dscr
= DSCR_INSTR_COMP
;
571 /* Wait for DTRRXfull */
572 long long then
= timeval_ms();
573 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
574 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
575 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
577 if (retval
!= ERROR_OK
)
579 if (timeval_ms() > then
+ 1000) {
580 LOG_ERROR("Timeout waiting for read dcc");
585 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
586 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
587 if (retval
!= ERROR_OK
)
589 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
597 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
599 struct cortex_a_common
*a
= dpm_to_a(dpm
);
600 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
604 /* set up invariant: INSTR_COMP is set after ever DPM operation */
605 long long then
= timeval_ms();
607 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
608 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
610 if (retval
!= ERROR_OK
)
612 if ((dscr
& DSCR_INSTR_COMP
) != 0)
614 if (timeval_ms() > then
+ 1000) {
615 LOG_ERROR("Timeout waiting for dpm prepare");
620 /* this "should never happen" ... */
621 if (dscr
& DSCR_DTR_RX_FULL
) {
622 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
624 retval
= cortex_a_exec_opcode(
625 a
->armv7a_common
.arm
.target
,
626 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
628 if (retval
!= ERROR_OK
)
635 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
637 /* REVISIT what could be done here? */
641 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
642 uint32_t opcode
, uint32_t data
)
644 struct cortex_a_common
*a
= dpm_to_a(dpm
);
646 uint32_t dscr
= DSCR_INSTR_COMP
;
648 retval
= cortex_a_write_dcc(a
, data
);
649 if (retval
!= ERROR_OK
)
652 return cortex_a_exec_opcode(
653 a
->armv7a_common
.arm
.target
,
658 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
659 uint32_t opcode
, uint32_t data
)
661 struct cortex_a_common
*a
= dpm_to_a(dpm
);
662 uint32_t dscr
= DSCR_INSTR_COMP
;
665 retval
= cortex_a_write_dcc(a
, data
);
666 if (retval
!= ERROR_OK
)
669 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
670 retval
= cortex_a_exec_opcode(
671 a
->armv7a_common
.arm
.target
,
672 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
674 if (retval
!= ERROR_OK
)
677 /* then the opcode, taking data from R0 */
678 retval
= cortex_a_exec_opcode(
679 a
->armv7a_common
.arm
.target
,
686 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
688 struct target
*target
= dpm
->arm
->target
;
689 uint32_t dscr
= DSCR_INSTR_COMP
;
691 /* "Prefetch flush" after modifying execution status in CPSR */
692 return cortex_a_exec_opcode(target
,
693 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
697 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
698 uint32_t opcode
, uint32_t *data
)
700 struct cortex_a_common
*a
= dpm_to_a(dpm
);
702 uint32_t dscr
= DSCR_INSTR_COMP
;
704 /* the opcode, writing data to DCC */
705 retval
= cortex_a_exec_opcode(
706 a
->armv7a_common
.arm
.target
,
709 if (retval
!= ERROR_OK
)
712 return cortex_a_read_dcc(a
, data
, &dscr
);
716 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
717 uint32_t opcode
, uint32_t *data
)
719 struct cortex_a_common
*a
= dpm_to_a(dpm
);
720 uint32_t dscr
= DSCR_INSTR_COMP
;
723 /* the opcode, writing data to R0 */
724 retval
= cortex_a_exec_opcode(
725 a
->armv7a_common
.arm
.target
,
728 if (retval
!= ERROR_OK
)
731 /* write R0 to DCC */
732 retval
= cortex_a_exec_opcode(
733 a
->armv7a_common
.arm
.target
,
734 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
736 if (retval
!= ERROR_OK
)
739 return cortex_a_read_dcc(a
, data
, &dscr
);
742 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
743 uint32_t addr
, uint32_t control
)
745 struct cortex_a_common
*a
= dpm_to_a(dpm
);
746 uint32_t vr
= a
->armv7a_common
.debug_base
;
747 uint32_t cr
= a
->armv7a_common
.debug_base
;
751 case 0 ... 15: /* breakpoints */
752 vr
+= CPUDBG_BVR_BASE
;
753 cr
+= CPUDBG_BCR_BASE
;
755 case 16 ... 31: /* watchpoints */
756 vr
+= CPUDBG_WVR_BASE
;
757 cr
+= CPUDBG_WCR_BASE
;
766 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
767 (unsigned) vr
, (unsigned) cr
);
769 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
771 if (retval
!= ERROR_OK
)
773 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
778 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
780 struct cortex_a_common
*a
= dpm_to_a(dpm
);
785 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
788 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
796 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
798 /* clear control register */
799 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
802 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
804 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
807 dpm
->arm
= &a
->armv7a_common
.arm
;
810 dpm
->prepare
= cortex_a_dpm_prepare
;
811 dpm
->finish
= cortex_a_dpm_finish
;
813 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
814 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
815 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
817 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
818 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
820 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
821 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
823 retval
= arm_dpm_setup(dpm
);
824 if (retval
== ERROR_OK
)
825 retval
= arm_dpm_initialize(dpm
);
829 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
831 struct target_list
*head
;
835 while (head
!= (struct target_list
*)NULL
) {
837 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
843 static int cortex_a_halt(struct target
*target
);
845 static int cortex_a_halt_smp(struct target
*target
)
848 struct target_list
*head
;
851 while (head
!= (struct target_list
*)NULL
) {
853 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
854 retval
+= cortex_a_halt(curr
);
860 static int update_halt_gdb(struct target
*target
)
863 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
864 target
->gdb_service
->target
= target
;
865 target
->gdb_service
->core
[0] = target
->coreid
;
866 retval
+= cortex_a_halt_smp(target
);
872 * Cortex-A Run control
875 static int cortex_a_poll(struct target
*target
)
877 int retval
= ERROR_OK
;
879 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
880 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
881 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
882 enum target_state prev_target_state
= target
->state
;
883 /* toggle to another core is done by gdb as follow */
884 /* maint packet J core_id */
886 /* the next polling trigger an halt event sent to gdb */
887 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
888 (target
->gdb_service
) &&
889 (target
->gdb_service
->target
== NULL
)) {
890 target
->gdb_service
->target
=
891 get_cortex_a(target
, target
->gdb_service
->core
[1]);
892 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
895 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
896 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
897 if (retval
!= ERROR_OK
)
899 cortex_a
->cpudbg_dscr
= dscr
;
901 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
902 if (prev_target_state
!= TARGET_HALTED
) {
903 /* We have a halting debug event */
904 LOG_DEBUG("Target halted");
905 target
->state
= TARGET_HALTED
;
906 if ((prev_target_state
== TARGET_RUNNING
)
907 || (prev_target_state
== TARGET_UNKNOWN
)
908 || (prev_target_state
== TARGET_RESET
)) {
909 retval
= cortex_a_debug_entry(target
);
910 if (retval
!= ERROR_OK
)
913 retval
= update_halt_gdb(target
);
914 if (retval
!= ERROR_OK
)
917 target_call_event_callbacks(target
,
918 TARGET_EVENT_HALTED
);
920 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
923 retval
= cortex_a_debug_entry(target
);
924 if (retval
!= ERROR_OK
)
927 retval
= update_halt_gdb(target
);
928 if (retval
!= ERROR_OK
)
932 target_call_event_callbacks(target
,
933 TARGET_EVENT_DEBUG_HALTED
);
936 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
937 target
->state
= TARGET_RUNNING
;
939 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
940 target
->state
= TARGET_UNKNOWN
;
946 static int cortex_a_halt(struct target
*target
)
948 int retval
= ERROR_OK
;
950 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
951 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
954 * Tell the core to be halted by writing DRCR with 0x1
955 * and then wait for the core to be halted.
957 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
958 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
959 if (retval
!= ERROR_OK
)
963 * enter halting debug mode
965 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
966 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
967 if (retval
!= ERROR_OK
)
970 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
971 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
972 if (retval
!= ERROR_OK
)
975 long long then
= timeval_ms();
977 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
978 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
979 if (retval
!= ERROR_OK
)
981 if ((dscr
& DSCR_CORE_HALTED
) != 0)
983 if (timeval_ms() > then
+ 1000) {
984 LOG_ERROR("Timeout waiting for halt");
989 target
->debug_reason
= DBG_REASON_DBGRQ
;
994 static int cortex_a_internal_restore(struct target
*target
, int current
,
995 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
997 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
998 struct arm
*arm
= &armv7a
->arm
;
1002 if (!debug_execution
)
1003 target_free_all_working_areas(target
);
1006 if (debug_execution
) {
1007 /* Disable interrupts */
1008 /* We disable interrupts in the PRIMASK register instead of
1009 * masking with C_MASKINTS,
1010 * This is probably the same issue as Cortex-M3 Errata 377493:
1011 * C_MASKINTS in parallel with disabled interrupts can cause
1012 * local faults to not be taken. */
1013 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
1014 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
1015 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
1017 /* Make sure we are in Thumb mode */
1018 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
1019 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
1021 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
1022 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
1026 /* current = 1: continue on current pc, otherwise continue at <address> */
1027 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1029 resume_pc
= *address
;
1031 *address
= resume_pc
;
1033 /* Make sure that the Armv7 gdb thumb fixups does not
1034 * kill the return address
1036 switch (arm
->core_state
) {
1038 resume_pc
&= 0xFFFFFFFC;
1040 case ARM_STATE_THUMB
:
1041 case ARM_STATE_THUMB_EE
:
1042 /* When the return address is loaded into PC
1043 * bit 0 must be 1 to stay in Thumb state
1047 case ARM_STATE_JAZELLE
:
1048 LOG_ERROR("How do I resume into Jazelle state??");
1051 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1052 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1055 /* restore dpm_mode at system halt */
1056 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1057 /* called it now before restoring context because it uses cpu
1058 * register r0 for restoring cp15 control register */
1059 retval
= cortex_a_restore_cp15_control_reg(target
);
1060 if (retval
!= ERROR_OK
)
1062 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1063 if (retval
!= ERROR_OK
)
1065 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1066 target
->state
= TARGET_RUNNING
;
1068 /* registers are now invalid */
1069 register_cache_invalidate(arm
->core_cache
);
1072 /* the front-end may request us not to handle breakpoints */
1073 if (handle_breakpoints
) {
1074 /* Single step past breakpoint at current address */
1075 breakpoint
= breakpoint_find(target
, resume_pc
);
1077 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1078 cortex_m3_unset_breakpoint(target
, breakpoint
);
1079 cortex_m3_single_step_core(target
);
1080 cortex_m3_set_breakpoint(target
, breakpoint
);
1088 static int cortex_a_internal_restart(struct target
*target
)
1090 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1091 struct arm
*arm
= &armv7a
->arm
;
1092 struct adiv5_dap
*swjdp
= arm
->dap
;
1096 * * Restart core and wait for it to be started. Clear ITRen and sticky
1097 * * exception flags: see ARMv7 ARM, C5.9.
1099 * REVISIT: for single stepping, we probably want to
1100 * disable IRQs by default, with optional override...
1103 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1104 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1105 if (retval
!= ERROR_OK
)
1108 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1109 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1111 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1112 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1113 if (retval
!= ERROR_OK
)
1116 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1117 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1118 DRCR_CLEAR_EXCEPTIONS
);
1119 if (retval
!= ERROR_OK
)
1122 long long then
= timeval_ms();
1124 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1125 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1126 if (retval
!= ERROR_OK
)
1128 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1130 if (timeval_ms() > then
+ 1000) {
1131 LOG_ERROR("Timeout waiting for resume");
1136 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1137 target
->state
= TARGET_RUNNING
;
1139 /* registers are now invalid */
1140 register_cache_invalidate(arm
->core_cache
);
1145 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1148 struct target_list
*head
;
1149 struct target
*curr
;
1151 head
= target
->head
;
1152 while (head
!= (struct target_list
*)NULL
) {
1153 curr
= head
->target
;
1154 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
1155 /* resume current address , not in step mode */
1156 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1157 handle_breakpoints
, 0);
1158 retval
+= cortex_a_internal_restart(curr
);
1166 static int cortex_a_resume(struct target
*target
, int current
,
1167 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1170 /* dummy resume for smp toggle in order to reduce gdb impact */
1171 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1172 /* simulate a start and halt of target */
1173 target
->gdb_service
->target
= NULL
;
1174 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1175 /* fake resume at next poll we play the target core[1], see poll*/
1176 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1179 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1181 target
->gdb_service
->core
[0] = -1;
1182 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1183 if (retval
!= ERROR_OK
)
1186 cortex_a_internal_restart(target
);
1188 if (!debug_execution
) {
1189 target
->state
= TARGET_RUNNING
;
1190 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1191 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1193 target
->state
= TARGET_DEBUG_RUNNING
;
1194 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1195 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1201 static int cortex_a_debug_entry(struct target
*target
)
1204 uint32_t regfile
[16], cpsr
, dscr
;
1205 int retval
= ERROR_OK
;
1206 struct working_area
*regfile_working_area
= NULL
;
1207 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1208 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1209 struct arm
*arm
= &armv7a
->arm
;
1210 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1213 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1215 /* REVISIT surely we should not re-read DSCR !! */
1216 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1217 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1218 if (retval
!= ERROR_OK
)
1221 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1222 * imprecise data aborts get discarded by issuing a Data
1223 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1226 /* Enable the ITR execution once we are in debug mode */
1227 dscr
|= DSCR_ITR_EN
;
1228 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1229 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1230 if (retval
!= ERROR_OK
)
1233 /* Examine debug reason */
1234 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1236 /* save address of instruction that triggered the watchpoint? */
1237 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1240 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1241 armv7a
->debug_base
+ CPUDBG_WFAR
,
1243 if (retval
!= ERROR_OK
)
1245 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1248 /* REVISIT fast_reg_read is never set ... */
1250 /* Examine target state and mode */
1251 if (cortex_a
->fast_reg_read
)
1252 target_alloc_working_area(target
, 64, ®file_working_area
);
1254 /* First load register acessible through core debug port*/
1255 if (!regfile_working_area
)
1256 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1258 retval
= cortex_a_read_regs_through_mem(target
,
1259 regfile_working_area
->address
, regfile
);
1261 target_free_working_area(target
, regfile_working_area
);
1262 if (retval
!= ERROR_OK
)
1265 /* read Current PSR */
1266 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1267 /* store current cpsr */
1268 if (retval
!= ERROR_OK
)
1271 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1273 arm_set_cpsr(arm
, cpsr
);
1276 for (i
= 0; i
<= ARM_PC
; i
++) {
1277 reg
= arm_reg_current(arm
, i
);
1279 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1284 /* Fixup PC Resume Address */
1285 if (cpsr
& (1 << 5)) {
1286 /* T bit set for Thumb or ThumbEE state */
1287 regfile
[ARM_PC
] -= 4;
1290 regfile
[ARM_PC
] -= 8;
1294 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1295 reg
->dirty
= reg
->valid
;
1299 /* TODO, Move this */
1300 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1301 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1302 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1304 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1305 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1307 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1308 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1311 /* Are we in an exception handler */
1312 /* armv4_5->exception_number = 0; */
1313 if (armv7a
->post_debug_entry
) {
1314 retval
= armv7a
->post_debug_entry(target
);
1315 if (retval
!= ERROR_OK
)
1322 static int cortex_a_post_debug_entry(struct target
*target
)
1324 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1325 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1328 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1329 retval
= armv7a
->arm
.mrc(target
, 15,
1330 0, 0, /* op1, op2 */
1331 1, 0, /* CRn, CRm */
1332 &cortex_a
->cp15_control_reg
);
1333 if (retval
!= ERROR_OK
)
1335 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1336 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1338 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1339 armv7a_identify_cache(target
);
1341 if (armv7a
->is_armv7r
) {
1342 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1344 armv7a
->armv7a_mmu
.mmu_enabled
=
1345 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1347 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1348 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1349 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1350 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1351 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1356 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1358 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1359 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1363 int retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1364 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1365 if (ERROR_OK
!= retval
)
1368 /* clear bitfield */
1371 dscr
|= value
& bit_mask
;
1373 /* write new DSCR */
1374 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1375 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1379 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1380 int handle_breakpoints
)
1382 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1383 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1384 struct arm
*arm
= &armv7a
->arm
;
1385 struct breakpoint
*breakpoint
= NULL
;
1386 struct breakpoint stepbreakpoint
;
1390 if (target
->state
!= TARGET_HALTED
) {
1391 LOG_WARNING("target not halted");
1392 return ERROR_TARGET_NOT_HALTED
;
1395 /* current = 1: continue on current pc, otherwise continue at <address> */
1398 buf_set_u32(r
->value
, 0, 32, address
);
1400 address
= buf_get_u32(r
->value
, 0, 32);
1402 /* The front-end may request us not to handle breakpoints.
1403 * But since Cortex-A uses breakpoint for single step,
1404 * we MUST handle breakpoints.
1406 handle_breakpoints
= 1;
1407 if (handle_breakpoints
) {
1408 breakpoint
= breakpoint_find(target
, address
);
1410 cortex_a_unset_breakpoint(target
, breakpoint
);
1413 /* Setup single step breakpoint */
1414 stepbreakpoint
.address
= address
;
1415 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1417 stepbreakpoint
.type
= BKPT_HARD
;
1418 stepbreakpoint
.set
= 0;
1420 /* Disable interrupts during single step if requested */
1421 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1422 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1423 if (ERROR_OK
!= retval
)
1427 /* Break on IVA mismatch */
1428 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1430 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1432 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1433 if (retval
!= ERROR_OK
)
1436 long long then
= timeval_ms();
1437 while (target
->state
!= TARGET_HALTED
) {
1438 retval
= cortex_a_poll(target
);
1439 if (retval
!= ERROR_OK
)
1441 if (timeval_ms() > then
+ 1000) {
1442 LOG_ERROR("timeout waiting for target halt");
1447 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1449 /* Re-enable interrupts if they were disabled */
1450 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1451 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1452 if (ERROR_OK
!= retval
)
1457 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1460 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1462 if (target
->state
!= TARGET_HALTED
)
1463 LOG_DEBUG("target stepped");
1468 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1470 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1474 if (armv7a
->pre_restore_context
)
1475 armv7a
->pre_restore_context(target
);
1477 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1481 * Cortex-A Breakpoint and watchpoint functions
1484 /* Setup hardware Breakpoint Register Pair */
1485 static int cortex_a_set_breakpoint(struct target
*target
,
1486 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1491 uint8_t byte_addr_select
= 0x0F;
1492 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1493 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1494 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1496 if (breakpoint
->set
) {
1497 LOG_WARNING("breakpoint already set");
1501 if (breakpoint
->type
== BKPT_HARD
) {
1502 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1504 if (brp_i
>= cortex_a
->brp_num
) {
1505 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1506 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1508 breakpoint
->set
= brp_i
+ 1;
1509 if (breakpoint
->length
== 2)
1510 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1511 control
= ((matchmode
& 0x7) << 20)
1512 | (byte_addr_select
<< 5)
1514 brp_list
[brp_i
].used
= 1;
1515 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1516 brp_list
[brp_i
].control
= control
;
1517 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1518 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1519 brp_list
[brp_i
].value
);
1520 if (retval
!= ERROR_OK
)
1522 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1523 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1524 brp_list
[brp_i
].control
);
1525 if (retval
!= ERROR_OK
)
1527 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1528 brp_list
[brp_i
].control
,
1529 brp_list
[brp_i
].value
);
1530 } else if (breakpoint
->type
== BKPT_SOFT
) {
1532 if (breakpoint
->length
== 2)
1533 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1535 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1536 retval
= target_read_memory(target
,
1537 breakpoint
->address
& 0xFFFFFFFE,
1538 breakpoint
->length
, 1,
1539 breakpoint
->orig_instr
);
1540 if (retval
!= ERROR_OK
)
1543 /* make sure data cache is cleaned & invalidated down to PoC */
1544 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1545 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1546 breakpoint
->length
);
1549 retval
= target_write_memory(target
,
1550 breakpoint
->address
& 0xFFFFFFFE,
1551 breakpoint
->length
, 1, code
);
1552 if (retval
!= ERROR_OK
)
1555 /* update i-cache at breakpoint location */
1556 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1557 breakpoint
->length
);
1558 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1559 breakpoint
->length
);
1561 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1567 static int cortex_a_set_context_breakpoint(struct target
*target
,
1568 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1570 int retval
= ERROR_FAIL
;
1573 uint8_t byte_addr_select
= 0x0F;
1574 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1575 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1576 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1578 if (breakpoint
->set
) {
1579 LOG_WARNING("breakpoint already set");
1582 /*check available context BRPs*/
1583 while ((brp_list
[brp_i
].used
||
1584 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1587 if (brp_i
>= cortex_a
->brp_num
) {
1588 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1592 breakpoint
->set
= brp_i
+ 1;
1593 control
= ((matchmode
& 0x7) << 20)
1594 | (byte_addr_select
<< 5)
1596 brp_list
[brp_i
].used
= 1;
1597 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1598 brp_list
[brp_i
].control
= control
;
1599 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1600 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1601 brp_list
[brp_i
].value
);
1602 if (retval
!= ERROR_OK
)
1604 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1605 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1606 brp_list
[brp_i
].control
);
1607 if (retval
!= ERROR_OK
)
1609 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1610 brp_list
[brp_i
].control
,
1611 brp_list
[brp_i
].value
);
1616 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1618 int retval
= ERROR_FAIL
;
1619 int brp_1
= 0; /* holds the contextID pair */
1620 int brp_2
= 0; /* holds the IVA pair */
1621 uint32_t control_CTX
, control_IVA
;
1622 uint8_t CTX_byte_addr_select
= 0x0F;
1623 uint8_t IVA_byte_addr_select
= 0x0F;
1624 uint8_t CTX_machmode
= 0x03;
1625 uint8_t IVA_machmode
= 0x01;
1626 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1627 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1628 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1630 if (breakpoint
->set
) {
1631 LOG_WARNING("breakpoint already set");
1634 /*check available context BRPs*/
1635 while ((brp_list
[brp_1
].used
||
1636 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1639 printf("brp(CTX) found num: %d\n", brp_1
);
1640 if (brp_1
>= cortex_a
->brp_num
) {
1641 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1645 while ((brp_list
[brp_2
].used
||
1646 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1649 printf("brp(IVA) found num: %d\n", brp_2
);
1650 if (brp_2
>= cortex_a
->brp_num
) {
1651 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1655 breakpoint
->set
= brp_1
+ 1;
1656 breakpoint
->linked_BRP
= brp_2
;
1657 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1660 | (CTX_byte_addr_select
<< 5)
1662 brp_list
[brp_1
].used
= 1;
1663 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1664 brp_list
[brp_1
].control
= control_CTX
;
1665 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1666 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1667 brp_list
[brp_1
].value
);
1668 if (retval
!= ERROR_OK
)
1670 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1671 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1672 brp_list
[brp_1
].control
);
1673 if (retval
!= ERROR_OK
)
1676 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1678 | (IVA_byte_addr_select
<< 5)
1680 brp_list
[brp_2
].used
= 1;
1681 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1682 brp_list
[brp_2
].control
= control_IVA
;
1683 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1684 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1685 brp_list
[brp_2
].value
);
1686 if (retval
!= ERROR_OK
)
1688 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1689 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1690 brp_list
[brp_2
].control
);
1691 if (retval
!= ERROR_OK
)
1697 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1700 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1701 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1702 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1704 if (!breakpoint
->set
) {
1705 LOG_WARNING("breakpoint not set");
1709 if (breakpoint
->type
== BKPT_HARD
) {
1710 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1711 int brp_i
= breakpoint
->set
- 1;
1712 int brp_j
= breakpoint
->linked_BRP
;
1713 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1714 LOG_DEBUG("Invalid BRP number in breakpoint");
1717 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1718 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1719 brp_list
[brp_i
].used
= 0;
1720 brp_list
[brp_i
].value
= 0;
1721 brp_list
[brp_i
].control
= 0;
1722 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1723 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1724 brp_list
[brp_i
].control
);
1725 if (retval
!= ERROR_OK
)
1727 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1728 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1729 brp_list
[brp_i
].value
);
1730 if (retval
!= ERROR_OK
)
1732 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1733 LOG_DEBUG("Invalid BRP number in breakpoint");
1736 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1737 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1738 brp_list
[brp_j
].used
= 0;
1739 brp_list
[brp_j
].value
= 0;
1740 brp_list
[brp_j
].control
= 0;
1741 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1742 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1743 brp_list
[brp_j
].control
);
1744 if (retval
!= ERROR_OK
)
1746 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1747 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1748 brp_list
[brp_j
].value
);
1749 if (retval
!= ERROR_OK
)
1751 breakpoint
->linked_BRP
= 0;
1752 breakpoint
->set
= 0;
1756 int brp_i
= breakpoint
->set
- 1;
1757 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1758 LOG_DEBUG("Invalid BRP number in breakpoint");
1761 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1762 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1763 brp_list
[brp_i
].used
= 0;
1764 brp_list
[brp_i
].value
= 0;
1765 brp_list
[brp_i
].control
= 0;
1766 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1767 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1768 brp_list
[brp_i
].control
);
1769 if (retval
!= ERROR_OK
)
1771 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1772 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1773 brp_list
[brp_i
].value
);
1774 if (retval
!= ERROR_OK
)
1776 breakpoint
->set
= 0;
1781 /* make sure data cache is cleaned & invalidated down to PoC */
1782 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1783 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1784 breakpoint
->length
);
1787 /* restore original instruction (kept in target endianness) */
1788 if (breakpoint
->length
== 4) {
1789 retval
= target_write_memory(target
,
1790 breakpoint
->address
& 0xFFFFFFFE,
1791 4, 1, breakpoint
->orig_instr
);
1792 if (retval
!= ERROR_OK
)
1795 retval
= target_write_memory(target
,
1796 breakpoint
->address
& 0xFFFFFFFE,
1797 2, 1, breakpoint
->orig_instr
);
1798 if (retval
!= ERROR_OK
)
1802 /* update i-cache at breakpoint location */
1803 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1804 breakpoint
->length
);
1805 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1806 breakpoint
->length
);
1808 breakpoint
->set
= 0;
1813 static int cortex_a_add_breakpoint(struct target
*target
,
1814 struct breakpoint
*breakpoint
)
1816 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1818 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1819 LOG_INFO("no hardware breakpoint available");
1820 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1823 if (breakpoint
->type
== BKPT_HARD
)
1824 cortex_a
->brp_num_available
--;
1826 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1829 static int cortex_a_add_context_breakpoint(struct target
*target
,
1830 struct breakpoint
*breakpoint
)
1832 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1834 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1835 LOG_INFO("no hardware breakpoint available");
1836 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1839 if (breakpoint
->type
== BKPT_HARD
)
1840 cortex_a
->brp_num_available
--;
1842 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1845 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1846 struct breakpoint
*breakpoint
)
1848 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1850 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1851 LOG_INFO("no hardware breakpoint available");
1852 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1855 if (breakpoint
->type
== BKPT_HARD
)
1856 cortex_a
->brp_num_available
--;
1858 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1862 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1864 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1867 /* It is perfectly possible to remove breakpoints while the target is running */
1868 if (target
->state
!= TARGET_HALTED
) {
1869 LOG_WARNING("target not halted");
1870 return ERROR_TARGET_NOT_HALTED
;
1874 if (breakpoint
->set
) {
1875 cortex_a_unset_breakpoint(target
, breakpoint
);
1876 if (breakpoint
->type
== BKPT_HARD
)
1877 cortex_a
->brp_num_available
++;
1885 * Cortex-A Reset functions
1888 static int cortex_a_assert_reset(struct target
*target
)
1890 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1894 /* FIXME when halt is requested, make it work somehow... */
1896 /* Issue some kind of warm reset. */
1897 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1898 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1899 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1900 /* REVISIT handle "pulls" cases, if there's
1901 * hardware that needs them to work.
1903 jtag_add_reset(0, 1);
1905 LOG_ERROR("%s: how to reset?", target_name(target
));
1909 /* registers are now invalid */
1910 register_cache_invalidate(armv7a
->arm
.core_cache
);
1912 target
->state
= TARGET_RESET
;
1917 static int cortex_a_deassert_reset(struct target
*target
)
1923 /* be certain SRST is off */
1924 jtag_add_reset(0, 0);
1926 retval
= cortex_a_poll(target
);
1927 if (retval
!= ERROR_OK
)
1930 if (target
->reset_halt
) {
1931 if (target
->state
!= TARGET_HALTED
) {
1932 LOG_WARNING("%s: ran after reset and before halt ...",
1933 target_name(target
));
1934 retval
= target_halt(target
);
1935 if (retval
!= ERROR_OK
)
1943 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1945 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1946 * New desired mode must be in mode. Current value of DSCR must be in
1947 * *dscr, which is updated with new value.
1949 * This function elides actually sending the mode-change over the debug
1950 * interface if the mode is already set as desired.
1952 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1953 if (new_dscr
!= *dscr
) {
1954 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1955 int retval
= mem_ap_sel_write_atomic_u32(armv7a
->arm
.dap
,
1956 armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1957 if (retval
== ERROR_OK
)
1965 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1966 uint32_t value
, uint32_t *dscr
)
1968 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1969 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1970 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1971 long long then
= timeval_ms();
1974 while ((*dscr
& mask
) != value
) {
1975 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1976 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1977 if (retval
!= ERROR_OK
)
1979 if (timeval_ms() > then
+ 1000) {
1980 LOG_ERROR("timeout waiting for DSCR bit change");
1987 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1988 uint32_t *data
, uint32_t *dscr
)
1991 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1992 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1994 /* Move from coprocessor to R0. */
1995 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1996 if (retval
!= ERROR_OK
)
1999 /* Move from R0 to DTRTX. */
2000 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
2001 if (retval
!= ERROR_OK
)
2004 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2005 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2006 * must also check TXfull_l). Most of the time this will be free
2007 * because TXfull_l will be set immediately and cached in dscr. */
2008 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2009 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2010 if (retval
!= ERROR_OK
)
2013 /* Read the value transferred to DTRTX. */
2014 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2015 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
2016 if (retval
!= ERROR_OK
)
2022 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
2023 uint32_t *dfsr
, uint32_t *dscr
)
2028 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2029 if (retval
!= ERROR_OK
)
2034 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2035 if (retval
!= ERROR_OK
)
2042 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2043 uint32_t data
, uint32_t *dscr
)
2046 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2047 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2049 /* Write the value into DTRRX. */
2050 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2051 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2052 if (retval
!= ERROR_OK
)
2055 /* Move from DTRRX to R0. */
2056 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2057 if (retval
!= ERROR_OK
)
2060 /* Move from R0 to coprocessor. */
2061 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2062 if (retval
!= ERROR_OK
)
2065 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2066 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2067 * check RXfull_l). Most of the time this will be free because RXfull_l
2068 * will be cleared immediately and cached in dscr. */
2069 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2070 if (retval
!= ERROR_OK
)
2076 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2077 uint32_t dfsr
, uint32_t *dscr
)
2081 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2082 if (retval
!= ERROR_OK
)
2085 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2086 if (retval
!= ERROR_OK
)
2092 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2094 uint32_t status
, upper4
;
2096 if (dfsr
& (1 << 9)) {
2098 status
= dfsr
& 0x3f;
2099 upper4
= status
>> 2;
2100 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2101 return ERROR_TARGET_TRANSLATION_FAULT
;
2102 else if (status
== 33)
2103 return ERROR_TARGET_UNALIGNED_ACCESS
;
2105 return ERROR_TARGET_DATA_ABORT
;
2107 /* Normal format. */
2108 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2110 return ERROR_TARGET_UNALIGNED_ACCESS
;
2111 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2112 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2113 return ERROR_TARGET_TRANSLATION_FAULT
;
2115 return ERROR_TARGET_DATA_ABORT
;
2119 static int cortex_a_write_apb_ab_memory_slow(struct target
*target
,
2120 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2122 /* Writes count objects of size size from *buffer. Old value of DSCR must
2123 * be in *dscr; updated to new value. This is slow because it works for
2124 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2125 * the address is aligned, cortex_a_write_apb_ab_memory_fast should be
2128 * - Address is in R0.
2129 * - R0 is marked dirty.
2131 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2132 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2133 struct arm
*arm
= &armv7a
->arm
;
2136 /* Mark register R1 as dirty, to use for transferring data. */
2137 arm_reg_current(arm
, 1)->dirty
= true;
2139 /* Switch to non-blocking mode if not already in that mode. */
2140 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2141 if (retval
!= ERROR_OK
)
2144 /* Go through the objects. */
2146 /* Write the value to store into DTRRX. */
2147 uint32_t data
, opcode
;
2151 data
= target_buffer_get_u16(target
, buffer
);
2153 data
= target_buffer_get_u32(target
, buffer
);
2154 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2155 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2156 if (retval
!= ERROR_OK
)
2159 /* Transfer the value from DTRRX to R1. */
2160 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2161 if (retval
!= ERROR_OK
)
2164 /* Write the value transferred to R1 into memory. */
2166 opcode
= ARMV4_5_STRB_IP(1, 0);
2168 opcode
= ARMV4_5_STRH_IP(1, 0);
2170 opcode
= ARMV4_5_STRW_IP(1, 0);
2171 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2172 if (retval
!= ERROR_OK
)
2175 /* Check for faults and return early. */
2176 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2177 return ERROR_OK
; /* A data fault is not considered a system failure. */
2179 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2180 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2181 * must also check RXfull_l). Most of the time this will be free
2182 * because RXfull_l will be cleared immediately and cached in dscr. */
2183 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2184 if (retval
!= ERROR_OK
)
2195 static int cortex_a_write_apb_ab_memory_fast(struct target
*target
,
2196 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2198 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2199 * in *dscr; updated to new value. This is fast but only works for
2200 * word-sized objects at aligned addresses.
2202 * - Address is in R0 and must be a multiple of 4.
2203 * - R0 is marked dirty.
2205 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2206 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2209 /* Switch to fast mode if not already in that mode. */
2210 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2211 if (retval
!= ERROR_OK
)
2214 /* Latch STC instruction. */
2215 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2216 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2217 if (retval
!= ERROR_OK
)
2220 /* Transfer all the data and issue all the instructions. */
2221 return mem_ap_sel_write_buf_noincr(swjdp
, armv7a
->debug_ap
, buffer
,
2222 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2225 static int cortex_a_write_apb_ab_memory(struct target
*target
,
2226 uint32_t address
, uint32_t size
,
2227 uint32_t count
, const uint8_t *buffer
)
2229 /* Write memory through APB-AP. */
2230 int retval
, final_retval
;
2231 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2232 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2233 struct arm
*arm
= &armv7a
->arm
;
2234 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2236 LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2237 address
, size
, count
);
2238 if (target
->state
!= TARGET_HALTED
) {
2239 LOG_WARNING("target not halted");
2240 return ERROR_TARGET_NOT_HALTED
;
2246 /* Clear any abort. */
2247 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2248 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2249 if (retval
!= ERROR_OK
)
2253 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2254 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2255 if (retval
!= ERROR_OK
)
2258 /* Switch to non-blocking mode if not already in that mode. */
2259 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2260 if (retval
!= ERROR_OK
)
2263 /* Mark R0 as dirty. */
2264 arm_reg_current(arm
, 0)->dirty
= true;
2266 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2267 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2268 if (retval
!= ERROR_OK
)
2271 /* Get the memory address into R0. */
2272 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2273 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2274 if (retval
!= ERROR_OK
)
2276 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2277 if (retval
!= ERROR_OK
)
2280 if (size
== 4 && (address
% 4) == 0) {
2281 /* We are doing a word-aligned transfer, so use fast mode. */
2282 retval
= cortex_a_write_apb_ab_memory_fast(target
, count
, buffer
, &dscr
);
2284 /* Use slow path. */
2285 retval
= cortex_a_write_apb_ab_memory_slow(target
, size
, count
, buffer
, &dscr
);
2289 final_retval
= retval
;
2291 /* Switch to non-blocking mode if not already in that mode. */
2292 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2293 if (final_retval
== ERROR_OK
)
2294 final_retval
= retval
;
2296 /* Wait for last issued instruction to complete. */
2297 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2298 if (final_retval
== ERROR_OK
)
2299 final_retval
= retval
;
2301 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2302 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2303 * check RXfull_l). Most of the time this will be free because RXfull_l
2304 * will be cleared immediately and cached in dscr. However, don’t do this
2305 * if there is fault, because then the instruction might not have completed
2307 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2308 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2309 if (retval
!= ERROR_OK
)
2313 /* If there were any sticky abort flags, clear them. */
2314 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2316 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2317 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2318 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2323 /* Handle synchronous data faults. */
2324 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2325 if (final_retval
== ERROR_OK
) {
2326 /* Final return value will reflect cause of fault. */
2327 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2328 if (retval
== ERROR_OK
) {
2329 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2330 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2332 final_retval
= retval
;
2334 /* Fault destroyed DFAR/DFSR; restore them. */
2335 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2336 if (retval
!= ERROR_OK
)
2337 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2340 /* Handle asynchronous data faults. */
2341 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2342 if (final_retval
== ERROR_OK
)
2343 /* No other error has been recorded so far, so keep this one. */
2344 final_retval
= ERROR_TARGET_DATA_ABORT
;
2347 /* If the DCC is nonempty, clear it. */
2348 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2350 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2351 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2352 if (final_retval
== ERROR_OK
)
2353 final_retval
= retval
;
2355 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2356 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2357 if (final_retval
== ERROR_OK
)
2358 final_retval
= retval
;
2362 return final_retval
;
2365 static int cortex_a_read_apb_ab_memory_slow(struct target
*target
,
2366 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2368 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2369 * in *dscr; updated to new value. This is slow because it works for
2370 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2371 * the address is aligned, cortex_a_read_apb_ab_memory_fast should be
2374 * - Address is in R0.
2375 * - R0 is marked dirty.
2377 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2378 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2379 struct arm
*arm
= &armv7a
->arm
;
2382 /* Mark register R1 as dirty, to use for transferring data. */
2383 arm_reg_current(arm
, 1)->dirty
= true;
2385 /* Switch to non-blocking mode if not already in that mode. */
2386 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2387 if (retval
!= ERROR_OK
)
2390 /* Go through the objects. */
2392 /* Issue a load of the appropriate size to R1. */
2393 uint32_t opcode
, data
;
2395 opcode
= ARMV4_5_LDRB_IP(1, 0);
2397 opcode
= ARMV4_5_LDRH_IP(1, 0);
2399 opcode
= ARMV4_5_LDRW_IP(1, 0);
2400 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2401 if (retval
!= ERROR_OK
)
2404 /* Issue a write of R1 to DTRTX. */
2405 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2406 if (retval
!= ERROR_OK
)
2409 /* Check for faults and return early. */
2410 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2411 return ERROR_OK
; /* A data fault is not considered a system failure. */
2413 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2414 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2415 * must also check TXfull_l). Most of the time this will be free
2416 * because TXfull_l will be set immediately and cached in dscr. */
2417 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2418 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2419 if (retval
!= ERROR_OK
)
2422 /* Read the value transferred to DTRTX into the buffer. */
2423 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2424 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2425 if (retval
!= ERROR_OK
)
2428 *buffer
= (uint8_t) data
;
2430 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2432 target_buffer_set_u32(target
, buffer
, data
);
2442 static int cortex_a_read_apb_ab_memory_fast(struct target
*target
,
2443 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2445 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2446 * *dscr; updated to new value. This is fast but only works for word-sized
2447 * objects at aligned addresses.
2449 * - Address is in R0 and must be a multiple of 4.
2450 * - R0 is marked dirty.
2452 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2453 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2457 /* Switch to non-blocking mode if not already in that mode. */
2458 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2459 if (retval
!= ERROR_OK
)
2462 /* Issue the LDC instruction via a write to ITR. */
2463 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2464 if (retval
!= ERROR_OK
)
2470 /* Switch to fast mode if not already in that mode. */
2471 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2472 if (retval
!= ERROR_OK
)
2475 /* Latch LDC instruction. */
2476 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2477 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2478 if (retval
!= ERROR_OK
)
2481 /* Read the value transferred to DTRTX into the buffer. Due to fast
2482 * mode rules, this blocks until the instruction finishes executing and
2483 * then reissues the read instruction to read the next word from
2484 * memory. The last read of DTRTX in this call reads the second-to-last
2485 * word from memory and issues the read instruction for the last word.
2487 retval
= mem_ap_sel_read_buf_noincr(swjdp
, armv7a
->debug_ap
, buffer
,
2488 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2489 if (retval
!= ERROR_OK
)
2493 buffer
+= count
* 4;
2496 /* Wait for last issued instruction to complete. */
2497 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2498 if (retval
!= ERROR_OK
)
2501 /* Switch to non-blocking mode if not already in that mode. */
2502 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2503 if (retval
!= ERROR_OK
)
2506 /* Check for faults and return early. */
2507 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2508 return ERROR_OK
; /* A data fault is not considered a system failure. */
2510 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2511 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2512 * check TXfull_l). Most of the time this will be free because TXfull_l
2513 * will be set immediately and cached in dscr. */
2514 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2515 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2516 if (retval
!= ERROR_OK
)
2519 /* Read the value transferred to DTRTX into the buffer. This is the last
2521 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2522 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2523 if (retval
!= ERROR_OK
)
2525 target_buffer_set_u32(target
, buffer
, u32
);
2530 static int cortex_a_read_apb_ab_memory(struct target
*target
,
2531 uint32_t address
, uint32_t size
,
2532 uint32_t count
, uint8_t *buffer
)
2534 /* Read memory through APB-AP. */
2535 int retval
, final_retval
;
2536 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2537 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2538 struct arm
*arm
= &armv7a
->arm
;
2539 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2541 LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2542 address
, size
, count
);
2543 if (target
->state
!= TARGET_HALTED
) {
2544 LOG_WARNING("target not halted");
2545 return ERROR_TARGET_NOT_HALTED
;
2551 /* Clear any abort. */
2552 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2553 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2554 if (retval
!= ERROR_OK
)
2558 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2559 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2560 if (retval
!= ERROR_OK
)
2563 /* Switch to non-blocking mode if not already in that mode. */
2564 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2565 if (retval
!= ERROR_OK
)
2568 /* Mark R0 as dirty. */
2569 arm_reg_current(arm
, 0)->dirty
= true;
2571 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2572 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2573 if (retval
!= ERROR_OK
)
2576 /* Get the memory address into R0. */
2577 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2578 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2579 if (retval
!= ERROR_OK
)
2581 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2582 if (retval
!= ERROR_OK
)
2585 if (size
== 4 && (address
% 4) == 0) {
2586 /* We are doing a word-aligned transfer, so use fast mode. */
2587 retval
= cortex_a_read_apb_ab_memory_fast(target
, count
, buffer
, &dscr
);
2589 /* Use slow path. */
2590 retval
= cortex_a_read_apb_ab_memory_slow(target
, size
, count
, buffer
, &dscr
);
2594 final_retval
= retval
;
2596 /* Switch to non-blocking mode if not already in that mode. */
2597 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2598 if (final_retval
== ERROR_OK
)
2599 final_retval
= retval
;
2601 /* Wait for last issued instruction to complete. */
2602 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2603 if (final_retval
== ERROR_OK
)
2604 final_retval
= retval
;
2606 /* If there were any sticky abort flags, clear them. */
2607 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2609 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2610 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2611 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2616 /* Handle synchronous data faults. */
2617 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2618 if (final_retval
== ERROR_OK
) {
2619 /* Final return value will reflect cause of fault. */
2620 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2621 if (retval
== ERROR_OK
) {
2622 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2623 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2625 final_retval
= retval
;
2627 /* Fault destroyed DFAR/DFSR; restore them. */
2628 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2629 if (retval
!= ERROR_OK
)
2630 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2633 /* Handle asynchronous data faults. */
2634 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2635 if (final_retval
== ERROR_OK
)
2636 /* No other error has been recorded so far, so keep this one. */
2637 final_retval
= ERROR_TARGET_DATA_ABORT
;
2640 /* If the DCC is nonempty, clear it. */
2641 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2643 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2644 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2645 if (final_retval
== ERROR_OK
)
2646 final_retval
= retval
;
2648 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2649 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2650 if (final_retval
== ERROR_OK
)
2651 final_retval
= retval
;
2655 return final_retval
;
2660 * Cortex-A Memory access
2662 * This is same Cortex M3 but we must also use the correct
2663 * ap number for every access.
2666 static int cortex_a_read_phys_memory(struct target
*target
,
2667 uint32_t address
, uint32_t size
,
2668 uint32_t count
, uint8_t *buffer
)
2670 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2672 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2673 address
, size
, count
);
2675 if (count
&& buffer
) {
2676 /* read memory through APB-AP */
2677 cortex_a_prep_memaccess(target
, 1);
2678 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2679 cortex_a_post_memaccess(target
, 1);
2684 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2685 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2689 /* cortex_a handles unaligned memory access */
2690 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2693 cortex_a_prep_memaccess(target
, 0);
2694 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2695 cortex_a_post_memaccess(target
, 0);
2700 static int cortex_a_read_memory_ahb(struct target
*target
, uint32_t address
,
2701 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2703 int mmu_enabled
= 0;
2704 uint32_t virt
, phys
;
2706 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2707 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2708 uint8_t apsel
= swjdp
->apsel
;
2710 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
))
2711 return target_read_memory(target
, address
, size
, count
, buffer
);
2713 /* cortex_a handles unaligned memory access */
2714 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2717 /* determine if MMU was enabled on target stop */
2718 if (!armv7a
->is_armv7r
) {
2719 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2720 if (retval
!= ERROR_OK
)
2726 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2727 if (retval
!= ERROR_OK
)
2730 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2735 if (!count
|| !buffer
)
2736 return ERROR_COMMAND_SYNTAX_ERROR
;
2738 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2743 static int cortex_a_write_phys_memory(struct target
*target
,
2744 uint32_t address
, uint32_t size
,
2745 uint32_t count
, const uint8_t *buffer
)
2747 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2749 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2752 if (count
&& buffer
) {
2753 /* write memory through APB-AP */
2754 cortex_a_prep_memaccess(target
, 1);
2755 retval
= cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2756 cortex_a_post_memaccess(target
, 1);
2762 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2763 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2767 /* cortex_a handles unaligned memory access */
2768 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2771 /* memory writes bypass the caches, must flush before writing */
2772 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2774 cortex_a_prep_memaccess(target
, 0);
2775 retval
= cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2776 cortex_a_post_memaccess(target
, 0);
2780 static int cortex_a_write_memory_ahb(struct target
*target
, uint32_t address
,
2781 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2783 int mmu_enabled
= 0;
2784 uint32_t virt
, phys
;
2786 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2787 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2788 uint8_t apsel
= swjdp
->apsel
;
2790 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
))
2791 return target_write_memory(target
, address
, size
, count
, buffer
);
2793 /* cortex_a handles unaligned memory access */
2794 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2797 /* determine if MMU was enabled on target stop */
2798 if (!armv7a
->is_armv7r
) {
2799 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2800 if (retval
!= ERROR_OK
)
2806 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2807 if (retval
!= ERROR_OK
)
2810 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2816 if (!count
|| !buffer
)
2817 return ERROR_COMMAND_SYNTAX_ERROR
;
2819 retval
= mem_ap_sel_write_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2824 static int cortex_a_read_buffer(struct target
*target
, uint32_t address
,
2825 uint32_t count
, uint8_t *buffer
)
2829 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2830 * will have something to do with the size we leave to it. */
2831 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2832 if (address
& size
) {
2833 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2834 if (retval
!= ERROR_OK
)
2842 /* Read the data with as large access size as possible. */
2843 for (; size
> 0; size
/= 2) {
2844 uint32_t aligned
= count
- count
% size
;
2846 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2847 if (retval
!= ERROR_OK
)
2858 static int cortex_a_write_buffer(struct target
*target
, uint32_t address
,
2859 uint32_t count
, const uint8_t *buffer
)
2863 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2864 * will have something to do with the size we leave to it. */
2865 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2866 if (address
& size
) {
2867 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2868 if (retval
!= ERROR_OK
)
2876 /* Write the data with as large access size as possible. */
2877 for (; size
> 0; size
/= 2) {
2878 uint32_t aligned
= count
- count
% size
;
2880 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2881 if (retval
!= ERROR_OK
)
2892 static int cortex_a_handle_target_request(void *priv
)
2894 struct target
*target
= priv
;
2895 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2896 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2899 if (!target_was_examined(target
))
2901 if (!target
->dbg_msg_enabled
)
2904 if (target
->state
== TARGET_RUNNING
) {
2907 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2908 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2910 /* check if we have data */
2911 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2912 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2913 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2914 if (retval
== ERROR_OK
) {
2915 target_request(target
, request
);
2916 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2917 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2926 * Cortex-A target information and configuration
2929 static int cortex_a_examine_first(struct target
*target
)
2931 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2932 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2933 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2935 int retval
= ERROR_OK
;
2936 uint32_t didr
, ctypr
, ttypr
, cpuid
, dbg_osreg
;
2938 /* We do one extra read to ensure DAP is configured,
2939 * we call ahbap_debugport_init(swjdp) instead
2941 retval
= ahbap_debugport_init(swjdp
);
2942 if (retval
!= ERROR_OK
)
2945 /* Search for the APB-AB - it is needed for access to debug registers */
2946 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2947 if (retval
!= ERROR_OK
) {
2948 LOG_ERROR("Could not find APB-AP for debug access");
2951 /* Search for the AHB-AB */
2952 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2953 if (retval
!= ERROR_OK
) {
2954 /* AHB-AP not found - use APB-AP */
2955 LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
2956 armv7a
->memory_ap_available
= false;
2958 armv7a
->memory_ap_available
= true;
2962 if (!target
->dbgbase_set
) {
2964 /* Get ROM Table base */
2966 int32_t coreidx
= target
->coreid
;
2967 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2969 retval
= dap_get_debugbase(swjdp
, 1, &dbgbase
, &apid
);
2970 if (retval
!= ERROR_OK
)
2972 /* Lookup 0x15 -- Processor DAP */
2973 retval
= dap_lookup_cs_component(swjdp
, 1, dbgbase
, 0x15,
2974 &armv7a
->debug_base
, &coreidx
);
2975 if (retval
!= ERROR_OK
) {
2976 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2980 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2981 target
->coreid
, armv7a
->debug_base
);
2983 armv7a
->debug_base
= target
->dbgbase
;
2985 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2986 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2987 if (retval
!= ERROR_OK
)
2990 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2991 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2992 if (retval
!= ERROR_OK
) {
2993 LOG_DEBUG("Examine %s failed", "CPUID");
2997 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2998 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
);
2999 if (retval
!= ERROR_OK
) {
3000 LOG_DEBUG("Examine %s failed", "CTYPR");
3004 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
3005 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
);
3006 if (retval
!= ERROR_OK
) {
3007 LOG_DEBUG("Examine %s failed", "TTYPR");
3011 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
3012 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
3013 if (retval
!= ERROR_OK
) {
3014 LOG_DEBUG("Examine %s failed", "DIDR");
3018 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3019 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
3020 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
3021 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
3023 cortex_a
->cpuid
= cpuid
;
3024 cortex_a
->ctypr
= ctypr
;
3025 cortex_a
->ttypr
= ttypr
;
3026 cortex_a
->didr
= didr
;
3028 /* Unlocking the debug registers */
3029 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3030 CORTEX_A15_PARTNUM
) {
3032 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
3033 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3036 if (retval
!= ERROR_OK
)
3040 /* Unlocking the debug registers */
3041 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3042 CORTEX_A7_PARTNUM
) {
3044 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
3045 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3048 if (retval
!= ERROR_OK
)
3052 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
3053 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3055 if (retval
!= ERROR_OK
)
3058 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3060 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3062 /* Avoid recreating the registers cache */
3063 if (!target_was_examined(target
)) {
3064 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3065 if (retval
!= ERROR_OK
)
3069 /* Setup Breakpoint Register Pairs */
3070 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3071 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3072 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3073 free(cortex_a
->brp_list
);
3074 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3075 /* cortex_a->brb_enabled = ????; */
3076 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3077 cortex_a
->brp_list
[i
].used
= 0;
3078 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3079 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3081 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3082 cortex_a
->brp_list
[i
].value
= 0;
3083 cortex_a
->brp_list
[i
].control
= 0;
3084 cortex_a
->brp_list
[i
].BRPn
= i
;
3087 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3089 target_set_examined(target
);
3093 static int cortex_a_examine(struct target
*target
)
3095 int retval
= ERROR_OK
;
3097 /* Reestablish communication after target reset */
3098 retval
= cortex_a_examine_first(target
);
3100 /* Configure core debug access */
3101 if (retval
== ERROR_OK
)
3102 retval
= cortex_a_init_debug_access(target
);
3108 * Cortex-A target creation and initialization
3111 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3112 struct target
*target
)
3114 /* examine_first() does a bunch of this */
3118 static int cortex_a_init_arch_info(struct target
*target
,
3119 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3121 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3122 struct adiv5_dap
*dap
= &armv7a
->dap
;
3124 armv7a
->arm
.dap
= dap
;
3126 /* Setup struct cortex_a_common */
3127 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3128 /* tap has no dap initialized */
3130 armv7a
->arm
.dap
= dap
;
3131 /* Setup struct cortex_a_common */
3133 /* prepare JTAG information for the new target */
3134 cortex_a
->jtag_info
.tap
= tap
;
3135 cortex_a
->jtag_info
.scann_size
= 4;
3137 /* Leave (only) generic DAP stuff for debugport_init() */
3138 dap
->jtag_info
= &cortex_a
->jtag_info
;
3140 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
3141 dap
->tar_autoincr_block
= (1 << 10);
3142 dap
->memaccess_tck
= 80;
3145 armv7a
->arm
.dap
= tap
->dap
;
3147 cortex_a
->fast_reg_read
= 0;
3149 /* register arch-specific functions */
3150 armv7a
->examine_debug_reason
= NULL
;
3152 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3154 armv7a
->pre_restore_context
= NULL
;
3156 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3159 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3161 /* REVISIT v7a setup should be in a v7a-specific routine */
3162 armv7a_init_arch_info(target
, armv7a
);
3163 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3168 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3170 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3172 cortex_a
->armv7a_common
.is_armv7r
= false;
3174 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3177 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3179 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3181 cortex_a
->armv7a_common
.is_armv7r
= true;
3183 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3186 static void cortex_a_deinit_target(struct target
*target
)
3188 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3189 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3191 free(cortex_a
->brp_list
);
3197 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3199 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3201 if (target
->state
!= TARGET_HALTED
) {
3202 LOG_ERROR("%s: target not halted", __func__
);
3203 return ERROR_TARGET_INVALID
;
3206 if (armv7a
->is_armv7r
)
3209 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3214 static int cortex_a_virt2phys(struct target
*target
,
3215 uint32_t virt
, uint32_t *phys
)
3217 int retval
= ERROR_FAIL
;
3218 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3219 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3220 uint8_t apsel
= swjdp
->apsel
;
3221 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
3223 retval
= armv7a_mmu_translate_va(target
,
3225 if (retval
!= ERROR_OK
)
3228 } else {/* use this method if armv7a->memory_ap not selected
3229 * mmu must be enable in order to get a correct translation */
3230 retval
= cortex_a_mmu_modify(target
, 1);
3231 if (retval
!= ERROR_OK
)
3233 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
3239 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3241 struct target
*target
= get_current_target(CMD_CTX
);
3242 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3244 return armv7a_handle_cache_info_command(CMD_CTX
,
3245 &armv7a
->armv7a_mmu
.armv7a_cache
);
3249 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3251 struct target
*target
= get_current_target(CMD_CTX
);
3252 if (!target_was_examined(target
)) {
3253 LOG_ERROR("target not examined yet");
3257 return cortex_a_init_debug_access(target
);
3259 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3261 struct target
*target
= get_current_target(CMD_CTX
);
3262 /* check target is an smp target */
3263 struct target_list
*head
;
3264 struct target
*curr
;
3265 head
= target
->head
;
3267 if (head
!= (struct target_list
*)NULL
) {
3268 while (head
!= (struct target_list
*)NULL
) {
3269 curr
= head
->target
;
3273 /* fixes the target display to the debugger */
3274 target
->gdb_service
->target
= target
;
3279 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3281 struct target
*target
= get_current_target(CMD_CTX
);
3282 struct target_list
*head
;
3283 struct target
*curr
;
3284 head
= target
->head
;
3285 if (head
!= (struct target_list
*)NULL
) {
3287 while (head
!= (struct target_list
*)NULL
) {
3288 curr
= head
->target
;
3296 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3298 struct target
*target
= get_current_target(CMD_CTX
);
3299 int retval
= ERROR_OK
;
3300 struct target_list
*head
;
3301 head
= target
->head
;
3302 if (head
!= (struct target_list
*)NULL
) {
3303 if (CMD_ARGC
== 1) {
3305 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3306 if (ERROR_OK
!= retval
)
3308 target
->gdb_service
->core
[1] = coreid
;
3311 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3312 , target
->gdb_service
->core
[1]);
3317 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3319 struct target
*target
= get_current_target(CMD_CTX
);
3320 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3322 static const Jim_Nvp nvp_maskisr_modes
[] = {
3323 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3324 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3325 { .name
= NULL
, .value
= -1 },
3329 if (target
->state
!= TARGET_HALTED
) {
3330 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3335 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3336 if (n
->name
== NULL
)
3337 return ERROR_COMMAND_SYNTAX_ERROR
;
3338 cortex_a
->isrmasking_mode
= n
->value
;
3342 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3343 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3348 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3350 .name
= "cache_info",
3351 .handler
= cortex_a_handle_cache_info_command
,
3352 .mode
= COMMAND_EXEC
,
3353 .help
= "display information about target caches",
3358 .handler
= cortex_a_handle_dbginit_command
,
3359 .mode
= COMMAND_EXEC
,
3360 .help
= "Initialize core debug",
3363 { .name
= "smp_off",
3364 .handler
= cortex_a_handle_smp_off_command
,
3365 .mode
= COMMAND_EXEC
,
3366 .help
= "Stop smp handling",
3370 .handler
= cortex_a_handle_smp_on_command
,
3371 .mode
= COMMAND_EXEC
,
3372 .help
= "Restart smp handling",
3377 .handler
= cortex_a_handle_smp_gdb_command
,
3378 .mode
= COMMAND_EXEC
,
3379 .help
= "display/fix current core played to gdb",
3384 .handler
= handle_cortex_a_mask_interrupts_command
,
3385 .mode
= COMMAND_EXEC
,
3386 .help
= "mask cortex_a interrupts",
3387 .usage
= "['on'|'off']",
3391 COMMAND_REGISTRATION_DONE
3393 static const struct command_registration cortex_a_command_handlers
[] = {
3395 .chain
= arm_command_handlers
,
3398 .chain
= armv7a_command_handlers
,
3402 .mode
= COMMAND_ANY
,
3403 .help
= "Cortex-A command group",
3405 .chain
= cortex_a_exec_command_handlers
,
3407 COMMAND_REGISTRATION_DONE
3410 struct target_type cortexa_target
= {
3412 .deprecated_name
= "cortex_a8",
3414 .poll
= cortex_a_poll
,
3415 .arch_state
= armv7a_arch_state
,
3417 .halt
= cortex_a_halt
,
3418 .resume
= cortex_a_resume
,
3419 .step
= cortex_a_step
,
3421 .assert_reset
= cortex_a_assert_reset
,
3422 .deassert_reset
= cortex_a_deassert_reset
,
3424 /* REVISIT allow exporting VFP3 registers ... */
3425 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3427 .read_memory
= cortex_a_read_memory
,
3428 .write_memory
= cortex_a_write_memory
,
3430 .read_buffer
= cortex_a_read_buffer
,
3431 .write_buffer
= cortex_a_write_buffer
,
3433 .checksum_memory
= arm_checksum_memory
,
3434 .blank_check_memory
= arm_blank_check_memory
,
3436 .run_algorithm
= armv4_5_run_algorithm
,
3438 .add_breakpoint
= cortex_a_add_breakpoint
,
3439 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3440 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3441 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3442 .add_watchpoint
= NULL
,
3443 .remove_watchpoint
= NULL
,
3445 .commands
= cortex_a_command_handlers
,
3446 .target_create
= cortex_a_target_create
,
3447 .init_target
= cortex_a_init_target
,
3448 .examine
= cortex_a_examine
,
3449 .deinit_target
= cortex_a_deinit_target
,
3451 .read_phys_memory
= cortex_a_read_phys_memory
,
3452 .write_phys_memory
= cortex_a_write_phys_memory
,
3453 .mmu
= cortex_a_mmu
,
3454 .virt2phys
= cortex_a_virt2phys
,
3457 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3459 .name
= "cache_info",
3460 .handler
= cortex_a_handle_cache_info_command
,
3461 .mode
= COMMAND_EXEC
,
3462 .help
= "display information about target caches",
3467 .handler
= cortex_a_handle_dbginit_command
,
3468 .mode
= COMMAND_EXEC
,
3469 .help
= "Initialize core debug",
3474 .handler
= handle_cortex_a_mask_interrupts_command
,
3475 .mode
= COMMAND_EXEC
,
3476 .help
= "mask cortex_r4 interrupts",
3477 .usage
= "['on'|'off']",
3480 COMMAND_REGISTRATION_DONE
3482 static const struct command_registration cortex_r4_command_handlers
[] = {
3484 .chain
= arm_command_handlers
,
3487 .chain
= armv7a_command_handlers
,
3490 .name
= "cortex_r4",
3491 .mode
= COMMAND_ANY
,
3492 .help
= "Cortex-R4 command group",
3494 .chain
= cortex_r4_exec_command_handlers
,
3496 COMMAND_REGISTRATION_DONE
3499 struct target_type cortexr4_target
= {
3500 .name
= "cortex_r4",
3502 .poll
= cortex_a_poll
,
3503 .arch_state
= armv7a_arch_state
,
3505 .halt
= cortex_a_halt
,
3506 .resume
= cortex_a_resume
,
3507 .step
= cortex_a_step
,
3509 .assert_reset
= cortex_a_assert_reset
,
3510 .deassert_reset
= cortex_a_deassert_reset
,
3512 /* REVISIT allow exporting VFP3 registers ... */
3513 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3515 .read_memory
= cortex_a_read_memory
,
3516 .write_memory
= cortex_a_write_memory
,
3518 .checksum_memory
= arm_checksum_memory
,
3519 .blank_check_memory
= arm_blank_check_memory
,
3521 .run_algorithm
= armv4_5_run_algorithm
,
3523 .add_breakpoint
= cortex_a_add_breakpoint
,
3524 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3525 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3526 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3527 .add_watchpoint
= NULL
,
3528 .remove_watchpoint
= NULL
,
3530 .commands
= cortex_r4_command_handlers
,
3531 .target_create
= cortex_r4_target_create
,
3532 .init_target
= cortex_a_init_target
,
3533 .examine
= cortex_a_examine
,
3534 .deinit_target
= cortex_a_deinit_target
,