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ARM: core DPM support for watchpoints
[openocd.git] / src / target / cortex_a8.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target, bool bpwp);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or (1 << DSCR_INSTR_COMP) if
95 * you happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
163 uint32_t *value, int regnum)
164 {
165 int retval = ERROR_OK;
166 uint8_t reg = regnum&0xFF;
167 uint32_t dscr = 0;
168 struct armv7a_common *armv7a = target_to_armv7a(target);
169 struct swjdp_common *swjdp = &armv7a->swjdp_info;
170
171 if (reg > 17)
172 return retval;
173
174 if (reg < 15)
175 {
176 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
177 cortex_a8_exec_opcode(target,
178 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
179 &dscr);
180 }
181 else if (reg == 15)
182 {
183 /* "MOV r0, r15"; then move r0 to DCCTX */
184 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
185 cortex_a8_exec_opcode(target,
186 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
187 &dscr);
188 }
189 else
190 {
191 /* "MRS r0, CPSR" or "MRS r0, SPSR"
192 * then move r0 to DCCTX
193 */
194 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
195 cortex_a8_exec_opcode(target,
196 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
197 &dscr);
198 }
199
200 /* Wait for DTRRXfull then read DTRRTX */
201 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
202 {
203 retval = mem_ap_read_atomic_u32(swjdp,
204 armv7a->debug_base + CPUDBG_DSCR, &dscr);
205 }
206
207 retval = mem_ap_read_atomic_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRTX, value);
209 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
210
211 return retval;
212 }
213
214 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
215 uint32_t value, int regnum)
216 {
217 int retval = ERROR_OK;
218 uint8_t Rd = regnum&0xFF;
219 uint32_t dscr;
220 struct armv7a_common *armv7a = target_to_armv7a(target);
221 struct swjdp_common *swjdp = &armv7a->swjdp_info;
222
223 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
224
225 /* Check that DCCRX is not full */
226 retval = mem_ap_read_atomic_u32(swjdp,
227 armv7a->debug_base + CPUDBG_DSCR, &dscr);
228 if (dscr & (1 << DSCR_DTR_RX_FULL))
229 {
230 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
231 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
232 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
233 &dscr);
234 }
235
236 if (Rd > 17)
237 return retval;
238
239 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
240 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
241 retval = mem_ap_write_u32(swjdp,
242 armv7a->debug_base + CPUDBG_DTRRX, value);
243
244 if (Rd < 15)
245 {
246 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
247 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
248 &dscr);
249 }
250 else if (Rd == 15)
251 {
252 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
253 * then "mov r15, r0"
254 */
255 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
256 &dscr);
257 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
258 }
259 else
260 {
261 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
262 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
263 */
264 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
265 &dscr);
266 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
267 &dscr);
268
269 /* "Prefetch flush" after modifying execution status in CPSR */
270 if (Rd == 16)
271 cortex_a8_exec_opcode(target,
272 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
273 &dscr);
274 }
275
276 return retval;
277 }
278
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
281 {
282 int retval;
283 struct armv7a_common *armv7a = target_to_armv7a(target);
284 struct swjdp_common *swjdp = &armv7a->swjdp_info;
285
286 retval = mem_ap_write_atomic_u32(swjdp, address, value);
287
288 return retval;
289 }
290
291 /*
292 * Cortex-A8 implementation of Debug Programmer's Model
293 *
294 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
295 * so there's no need to poll for it before executing an instruction.
296 *
297 * NOTE that in several of these cases the "stall" mode might be useful.
298 * It'd let us queue a few operations together... prepare/finish might
299 * be the places to enable/disable that mode.
300 */
301
302 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
303 {
304 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
305 }
306
307 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
308 {
309 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
310 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
311 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
312 }
313
314 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
315 uint32_t *dscr_p)
316 {
317 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
318 uint32_t dscr = 1 << DSCR_INSTR_COMP;
319 int retval;
320
321 if (dscr_p)
322 dscr = *dscr_p;
323
324 /* Wait for DTRRXfull */
325 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
326 retval = mem_ap_read_atomic_u32(swjdp,
327 a8->armv7a_common.debug_base + CPUDBG_DSCR,
328 &dscr);
329 }
330
331 retval = mem_ap_read_atomic_u32(swjdp,
332 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
333 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
334
335 if (dscr_p)
336 *dscr_p = dscr;
337
338 return retval;
339 }
340
341 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
342 {
343 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
344 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
345 uint32_t dscr;
346 int retval;
347
348 /* set up invariant: INSTR_COMP is set after ever DPM operation */
349 do {
350 retval = mem_ap_read_atomic_u32(swjdp,
351 a8->armv7a_common.debug_base + CPUDBG_DSCR,
352 &dscr);
353 } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
354
355 /* this "should never happen" ... */
356 if (dscr & (1 << DSCR_DTR_RX_FULL)) {
357 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
358 /* Clear DCCRX */
359 retval = cortex_a8_exec_opcode(
360 a8->armv7a_common.armv4_5_common.target,
361 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
362 &dscr);
363 }
364
365 return retval;
366 }
367
368 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
369 {
370 /* REVISIT what could be done here? */
371 return ERROR_OK;
372 }
373
374 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
375 uint32_t opcode, uint32_t data)
376 {
377 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
378 int retval;
379 uint32_t dscr = 1 << DSCR_INSTR_COMP;
380
381 retval = cortex_a8_write_dcc(a8, data);
382
383 return cortex_a8_exec_opcode(
384 a8->armv7a_common.armv4_5_common.target,
385 opcode,
386 &dscr);
387 }
388
389 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
390 uint32_t opcode, uint32_t data)
391 {
392 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
393 uint32_t dscr = 1 << DSCR_INSTR_COMP;
394 int retval;
395
396 retval = cortex_a8_write_dcc(a8, data);
397
398 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
399 retval = cortex_a8_exec_opcode(
400 a8->armv7a_common.armv4_5_common.target,
401 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
402 &dscr);
403
404 /* then the opcode, taking data from R0 */
405 retval = cortex_a8_exec_opcode(
406 a8->armv7a_common.armv4_5_common.target,
407 opcode,
408 &dscr);
409
410 return retval;
411 }
412
413 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
414 {
415 struct target *target = dpm->arm->target;
416 uint32_t dscr = 1 << DSCR_INSTR_COMP;
417
418 /* "Prefetch flush" after modifying execution status in CPSR */
419 return cortex_a8_exec_opcode(target,
420 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
421 &dscr);
422 }
423
424 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
425 uint32_t opcode, uint32_t *data)
426 {
427 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
428 int retval;
429 uint32_t dscr = 1 << DSCR_INSTR_COMP;
430
431 /* the opcode, writing data to DCC */
432 retval = cortex_a8_exec_opcode(
433 a8->armv7a_common.armv4_5_common.target,
434 opcode,
435 &dscr);
436
437 return cortex_a8_read_dcc(a8, data, &dscr);
438 }
439
440
441 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
442 uint32_t opcode, uint32_t *data)
443 {
444 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
445 uint32_t dscr = 1 << DSCR_INSTR_COMP;
446 int retval;
447
448 /* the opcode, writing data to R0 */
449 retval = cortex_a8_exec_opcode(
450 a8->armv7a_common.armv4_5_common.target,
451 opcode,
452 &dscr);
453
454 /* write R0 to DCC */
455 retval = cortex_a8_exec_opcode(
456 a8->armv7a_common.armv4_5_common.target,
457 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
458 &dscr);
459
460 return cortex_a8_read_dcc(a8, data, &dscr);
461 }
462
463 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
464 {
465 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
466
467 dpm->arm = &a8->armv7a_common.armv4_5_common;
468 dpm->didr = didr;
469
470 dpm->prepare = cortex_a8_dpm_prepare;
471 dpm->finish = cortex_a8_dpm_finish;
472
473 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
474 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
475 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
476
477 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
478 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
479
480 return arm_dpm_setup(dpm);
481 }
482
483
484 /*
485 * Cortex-A8 Run control
486 */
487
488 static int cortex_a8_poll(struct target *target)
489 {
490 int retval = ERROR_OK;
491 uint32_t dscr;
492 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
493 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
494 struct swjdp_common *swjdp = &armv7a->swjdp_info;
495 enum target_state prev_target_state = target->state;
496 uint8_t saved_apsel = dap_ap_get_select(swjdp);
497
498 dap_ap_select(swjdp, swjdp_debugap);
499 retval = mem_ap_read_atomic_u32(swjdp,
500 armv7a->debug_base + CPUDBG_DSCR, &dscr);
501 if (retval != ERROR_OK)
502 {
503 dap_ap_select(swjdp, saved_apsel);
504 return retval;
505 }
506 cortex_a8->cpudbg_dscr = dscr;
507
508 if ((dscr & 0x3) == 0x3)
509 {
510 if (prev_target_state != TARGET_HALTED)
511 {
512 /* We have a halting debug event */
513 LOG_DEBUG("Target halted");
514 target->state = TARGET_HALTED;
515 if ((prev_target_state == TARGET_RUNNING)
516 || (prev_target_state == TARGET_RESET))
517 {
518 retval = cortex_a8_debug_entry(target);
519 if (retval != ERROR_OK)
520 return retval;
521
522 target_call_event_callbacks(target,
523 TARGET_EVENT_HALTED);
524 }
525 if (prev_target_state == TARGET_DEBUG_RUNNING)
526 {
527 LOG_DEBUG(" ");
528
529 retval = cortex_a8_debug_entry(target);
530 if (retval != ERROR_OK)
531 return retval;
532
533 target_call_event_callbacks(target,
534 TARGET_EVENT_DEBUG_HALTED);
535 }
536 }
537 }
538 else if ((dscr & 0x3) == 0x2)
539 {
540 target->state = TARGET_RUNNING;
541 }
542 else
543 {
544 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
545 target->state = TARGET_UNKNOWN;
546 }
547
548 dap_ap_select(swjdp, saved_apsel);
549
550 return retval;
551 }
552
553 static int cortex_a8_halt(struct target *target)
554 {
555 int retval = ERROR_OK;
556 uint32_t dscr;
557 struct armv7a_common *armv7a = target_to_armv7a(target);
558 struct swjdp_common *swjdp = &armv7a->swjdp_info;
559 uint8_t saved_apsel = dap_ap_get_select(swjdp);
560 dap_ap_select(swjdp, swjdp_debugap);
561
562 /*
563 * Tell the core to be halted by writing DRCR with 0x1
564 * and then wait for the core to be halted.
565 */
566 retval = mem_ap_write_atomic_u32(swjdp,
567 armv7a->debug_base + CPUDBG_DRCR, 0x1);
568
569 /*
570 * enter halting debug mode
571 */
572 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
573 retval = mem_ap_write_atomic_u32(swjdp,
574 armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
575
576 if (retval != ERROR_OK)
577 goto out;
578
579 do {
580 mem_ap_read_atomic_u32(swjdp,
581 armv7a->debug_base + CPUDBG_DSCR, &dscr);
582 } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
583
584 target->debug_reason = DBG_REASON_DBGRQ;
585
586 out:
587 dap_ap_select(swjdp, saved_apsel);
588 return retval;
589 }
590
591 static int cortex_a8_resume(struct target *target, int current,
592 uint32_t address, int handle_breakpoints, int debug_execution)
593 {
594 struct armv7a_common *armv7a = target_to_armv7a(target);
595 struct arm *armv4_5 = &armv7a->armv4_5_common;
596 struct swjdp_common *swjdp = &armv7a->swjdp_info;
597
598 // struct breakpoint *breakpoint = NULL;
599 uint32_t resume_pc, dscr;
600
601 uint8_t saved_apsel = dap_ap_get_select(swjdp);
602 dap_ap_select(swjdp, swjdp_debugap);
603
604 if (!debug_execution)
605 target_free_all_working_areas(target);
606
607 #if 0
608 if (debug_execution)
609 {
610 /* Disable interrupts */
611 /* We disable interrupts in the PRIMASK register instead of
612 * masking with C_MASKINTS,
613 * This is probably the same issue as Cortex-M3 Errata 377493:
614 * C_MASKINTS in parallel with disabled interrupts can cause
615 * local faults to not be taken. */
616 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
617 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
618 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
619
620 /* Make sure we are in Thumb mode */
621 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
622 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
623 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
624 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
625 }
626 #endif
627
628 /* current = 1: continue on current pc, otherwise continue at <address> */
629 resume_pc = buf_get_u32(
630 armv4_5->core_cache->reg_list[15].value,
631 0, 32);
632 if (!current)
633 resume_pc = address;
634
635 /* Make sure that the Armv7 gdb thumb fixups does not
636 * kill the return address
637 */
638 switch (armv4_5->core_state)
639 {
640 case ARMV4_5_STATE_ARM:
641 resume_pc &= 0xFFFFFFFC;
642 break;
643 case ARMV4_5_STATE_THUMB:
644 case ARM_STATE_THUMB_EE:
645 /* When the return address is loaded into PC
646 * bit 0 must be 1 to stay in Thumb state
647 */
648 resume_pc |= 0x1;
649 break;
650 case ARMV4_5_STATE_JAZELLE:
651 LOG_ERROR("How do I resume into Jazelle state??");
652 return ERROR_FAIL;
653 }
654 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
655 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
656 0, 32, resume_pc);
657 armv4_5->core_cache->reg_list[15].dirty = 1;
658 armv4_5->core_cache->reg_list[15].valid = 1;
659
660 cortex_a8_restore_context(target, handle_breakpoints);
661
662 #if 0
663 /* the front-end may request us not to handle breakpoints */
664 if (handle_breakpoints)
665 {
666 /* Single step past breakpoint at current address */
667 if ((breakpoint = breakpoint_find(target, resume_pc)))
668 {
669 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
670 cortex_m3_unset_breakpoint(target, breakpoint);
671 cortex_m3_single_step_core(target);
672 cortex_m3_set_breakpoint(target, breakpoint);
673 }
674 }
675
676 #endif
677 /* Restart core and wait for it to be started */
678 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
679
680 do {
681 mem_ap_read_atomic_u32(swjdp,
682 armv7a->debug_base + CPUDBG_DSCR, &dscr);
683 } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
684
685 target->debug_reason = DBG_REASON_NOTHALTED;
686 target->state = TARGET_RUNNING;
687
688 /* registers are now invalid */
689 register_cache_invalidate(armv4_5->core_cache);
690
691 if (!debug_execution)
692 {
693 target->state = TARGET_RUNNING;
694 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
695 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
696 }
697 else
698 {
699 target->state = TARGET_DEBUG_RUNNING;
700 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
701 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
702 }
703
704 dap_ap_select(swjdp, saved_apsel);
705
706 return ERROR_OK;
707 }
708
709 static int cortex_a8_debug_entry(struct target *target)
710 {
711 int i;
712 uint32_t regfile[16], pc, cpsr, dscr;
713 int retval = ERROR_OK;
714 struct working_area *regfile_working_area = NULL;
715 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
716 struct armv7a_common *armv7a = target_to_armv7a(target);
717 struct arm *armv4_5 = &armv7a->armv4_5_common;
718 struct swjdp_common *swjdp = &armv7a->swjdp_info;
719 struct reg *reg;
720
721 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
722
723 /* Enable the ITR execution once we are in debug mode */
724 mem_ap_read_atomic_u32(swjdp,
725 armv7a->debug_base + CPUDBG_DSCR, &dscr);
726
727 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
728 * imprecise data aborts get discarded by issuing a Data
729 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
730 */
731
732 dscr |= (1 << DSCR_EXT_INT_EN);
733 retval = mem_ap_write_atomic_u32(swjdp,
734 armv7a->debug_base + CPUDBG_DSCR, dscr);
735
736 /* Examine debug reason */
737 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
738 {
739 case 0: /* DRCR[0] write */
740 case 4: /* EDBGRQ */
741 target->debug_reason = DBG_REASON_DBGRQ;
742 break;
743 case 1: /* HW breakpoint */
744 case 3: /* SW BKPT */
745 case 5: /* vector catch */
746 target->debug_reason = DBG_REASON_BREAKPOINT;
747 break;
748 case 10: /* precise watchpoint */
749 target->debug_reason = DBG_REASON_WATCHPOINT;
750 /* REVISIT could collect WFAR later, to see just
751 * which instruction triggered the watchpoint.
752 */
753 break;
754 default:
755 target->debug_reason = DBG_REASON_UNDEFINED;
756 break;
757 }
758
759 /* REVISIT fast_reg_read is never set ... */
760
761 /* Examine target state and mode */
762 if (cortex_a8->fast_reg_read)
763 target_alloc_working_area(target, 64, &regfile_working_area);
764
765 /* First load register acessible through core debug port*/
766 if (!regfile_working_area)
767 {
768 retval = arm_dpm_read_current_registers(&armv7a->dpm);
769 }
770 else
771 {
772 dap_ap_select(swjdp, swjdp_memoryap);
773 cortex_a8_read_regs_through_mem(target,
774 regfile_working_area->address, regfile);
775 dap_ap_select(swjdp, swjdp_memoryap);
776 target_free_working_area(target, regfile_working_area);
777
778 /* read Current PSR */
779 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
780 pc = regfile[15];
781 dap_ap_select(swjdp, swjdp_debugap);
782 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
783
784 arm_set_cpsr(armv4_5, cpsr);
785
786 /* update cache */
787 for (i = 0; i <= ARM_PC; i++)
788 {
789 reg = arm_reg_current(armv4_5, i);
790
791 buf_set_u32(reg->value, 0, 32, regfile[i]);
792 reg->valid = 1;
793 reg->dirty = 0;
794 }
795
796 /* Fixup PC Resume Address */
797 if (cpsr & (1 << 5))
798 {
799 // T bit set for Thumb or ThumbEE state
800 regfile[ARM_PC] -= 4;
801 }
802 else
803 {
804 // ARM state
805 regfile[ARM_PC] -= 8;
806 }
807
808 reg = armv4_5->core_cache->reg_list + 15;
809 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
810 reg->dirty = reg->valid;
811 }
812
813 #if 0
814 /* TODO, Move this */
815 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
816 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
817 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
818
819 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
820 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
821
822 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
823 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
824 #endif
825
826 /* Are we in an exception handler */
827 // armv4_5->exception_number = 0;
828 if (armv7a->post_debug_entry)
829 armv7a->post_debug_entry(target);
830
831
832
833 return retval;
834
835 }
836
837 static void cortex_a8_post_debug_entry(struct target *target)
838 {
839 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
840 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
841 int retval;
842
843 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
844 retval = armv7a->armv4_5_common.mrc(target, 15,
845 0, 0, /* op1, op2 */
846 1, 0, /* CRn, CRm */
847 &cortex_a8->cp15_control_reg);
848 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
849
850 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
851 {
852 uint32_t cache_type_reg;
853
854 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
855 retval = armv7a->armv4_5_common.mrc(target, 15,
856 0, 1, /* op1, op2 */
857 0, 0, /* CRn, CRm */
858 &cache_type_reg);
859 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
860
861 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
862 armv4_5_identify_cache(cache_type_reg,
863 &armv7a->armv4_5_mmu.armv4_5_cache);
864 }
865
866 armv7a->armv4_5_mmu.mmu_enabled =
867 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
868 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
869 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
870 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
871 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
872
873
874 }
875
876 static int cortex_a8_step(struct target *target, int current, uint32_t address,
877 int handle_breakpoints)
878 {
879 struct armv7a_common *armv7a = target_to_armv7a(target);
880 struct arm *armv4_5 = &armv7a->armv4_5_common;
881 struct breakpoint *breakpoint = NULL;
882 struct breakpoint stepbreakpoint;
883 struct reg *r;
884
885 int timeout = 100;
886
887 if (target->state != TARGET_HALTED)
888 {
889 LOG_WARNING("target not halted");
890 return ERROR_TARGET_NOT_HALTED;
891 }
892
893 /* current = 1: continue on current pc, otherwise continue at <address> */
894 r = armv4_5->core_cache->reg_list + 15;
895 if (!current)
896 {
897 buf_set_u32(r->value, 0, 32, address);
898 }
899 else
900 {
901 address = buf_get_u32(r->value, 0, 32);
902 }
903
904 /* The front-end may request us not to handle breakpoints.
905 * But since Cortex-A8 uses breakpoint for single step,
906 * we MUST handle breakpoints.
907 */
908 handle_breakpoints = 1;
909 if (handle_breakpoints) {
910 breakpoint = breakpoint_find(target, address);
911 if (breakpoint)
912 cortex_a8_unset_breakpoint(target, breakpoint);
913 }
914
915 /* Setup single step breakpoint */
916 stepbreakpoint.address = address;
917 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
918 ? 2 : 4;
919 stepbreakpoint.type = BKPT_HARD;
920 stepbreakpoint.set = 0;
921
922 /* Break on IVA mismatch */
923 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
924
925 target->debug_reason = DBG_REASON_SINGLESTEP;
926
927 cortex_a8_resume(target, 1, address, 0, 0);
928
929 while (target->state != TARGET_HALTED)
930 {
931 cortex_a8_poll(target);
932 if (--timeout == 0)
933 {
934 LOG_WARNING("timeout waiting for target halt");
935 break;
936 }
937 }
938
939 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
940 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
941
942 if (breakpoint)
943 cortex_a8_set_breakpoint(target, breakpoint, 0);
944
945 if (target->state != TARGET_HALTED)
946 LOG_DEBUG("target stepped");
947
948 return ERROR_OK;
949 }
950
951 static int cortex_a8_restore_context(struct target *target, bool bpwp)
952 {
953 struct armv7a_common *armv7a = target_to_armv7a(target);
954
955 LOG_DEBUG(" ");
956
957 if (armv7a->pre_restore_context)
958 armv7a->pre_restore_context(target);
959
960 arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
961
962 if (armv7a->post_restore_context)
963 armv7a->post_restore_context(target);
964
965 return ERROR_OK;
966 }
967
968
969 /*
970 * Cortex-A8 Breakpoint and watchpoint fuctions
971 */
972
973 /* Setup hardware Breakpoint Register Pair */
974 static int cortex_a8_set_breakpoint(struct target *target,
975 struct breakpoint *breakpoint, uint8_t matchmode)
976 {
977 int retval;
978 int brp_i=0;
979 uint32_t control;
980 uint8_t byte_addr_select = 0x0F;
981 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
982 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
983 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
984
985 if (breakpoint->set)
986 {
987 LOG_WARNING("breakpoint already set");
988 return ERROR_OK;
989 }
990
991 if (breakpoint->type == BKPT_HARD)
992 {
993 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
994 brp_i++ ;
995 if (brp_i >= cortex_a8->brp_num)
996 {
997 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
998 return ERROR_FAIL;
999 }
1000 breakpoint->set = brp_i + 1;
1001 if (breakpoint->length == 2)
1002 {
1003 byte_addr_select = (3 << (breakpoint->address & 0x02));
1004 }
1005 control = ((matchmode & 0x7) << 20)
1006 | (byte_addr_select << 5)
1007 | (3 << 1) | 1;
1008 brp_list[brp_i].used = 1;
1009 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1010 brp_list[brp_i].control = control;
1011 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1012 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1013 brp_list[brp_i].value);
1014 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1015 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1016 brp_list[brp_i].control);
1017 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1018 brp_list[brp_i].control,
1019 brp_list[brp_i].value);
1020 }
1021 else if (breakpoint->type == BKPT_SOFT)
1022 {
1023 uint8_t code[4];
1024 if (breakpoint->length == 2)
1025 {
1026 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1027 }
1028 else
1029 {
1030 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1031 }
1032 retval = target->type->read_memory(target,
1033 breakpoint->address & 0xFFFFFFFE,
1034 breakpoint->length, 1,
1035 breakpoint->orig_instr);
1036 if (retval != ERROR_OK)
1037 return retval;
1038 retval = target->type->write_memory(target,
1039 breakpoint->address & 0xFFFFFFFE,
1040 breakpoint->length, 1, code);
1041 if (retval != ERROR_OK)
1042 return retval;
1043 breakpoint->set = 0x11; /* Any nice value but 0 */
1044 }
1045
1046 return ERROR_OK;
1047 }
1048
1049 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1050 {
1051 int retval;
1052 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1053 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1054 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1055
1056 if (!breakpoint->set)
1057 {
1058 LOG_WARNING("breakpoint not set");
1059 return ERROR_OK;
1060 }
1061
1062 if (breakpoint->type == BKPT_HARD)
1063 {
1064 int brp_i = breakpoint->set - 1;
1065 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1066 {
1067 LOG_DEBUG("Invalid BRP number in breakpoint");
1068 return ERROR_OK;
1069 }
1070 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1071 brp_list[brp_i].control, brp_list[brp_i].value);
1072 brp_list[brp_i].used = 0;
1073 brp_list[brp_i].value = 0;
1074 brp_list[brp_i].control = 0;
1075 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1076 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1077 brp_list[brp_i].control);
1078 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1079 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1080 brp_list[brp_i].value);
1081 }
1082 else
1083 {
1084 /* restore original instruction (kept in target endianness) */
1085 if (breakpoint->length == 4)
1086 {
1087 retval = target->type->write_memory(target,
1088 breakpoint->address & 0xFFFFFFFE,
1089 4, 1, breakpoint->orig_instr);
1090 if (retval != ERROR_OK)
1091 return retval;
1092 }
1093 else
1094 {
1095 retval = target->type->write_memory(target,
1096 breakpoint->address & 0xFFFFFFFE,
1097 2, 1, breakpoint->orig_instr);
1098 if (retval != ERROR_OK)
1099 return retval;
1100 }
1101 }
1102 breakpoint->set = 0;
1103
1104 return ERROR_OK;
1105 }
1106
1107 static int cortex_a8_add_breakpoint(struct target *target,
1108 struct breakpoint *breakpoint)
1109 {
1110 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1111
1112 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1113 {
1114 LOG_INFO("no hardware breakpoint available");
1115 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1116 }
1117
1118 if (breakpoint->type == BKPT_HARD)
1119 cortex_a8->brp_num_available--;
1120 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1121
1122 return ERROR_OK;
1123 }
1124
1125 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1126 {
1127 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1128
1129 #if 0
1130 /* It is perfectly possible to remove brakpoints while the taget is running */
1131 if (target->state != TARGET_HALTED)
1132 {
1133 LOG_WARNING("target not halted");
1134 return ERROR_TARGET_NOT_HALTED;
1135 }
1136 #endif
1137
1138 if (breakpoint->set)
1139 {
1140 cortex_a8_unset_breakpoint(target, breakpoint);
1141 if (breakpoint->type == BKPT_HARD)
1142 cortex_a8->brp_num_available++ ;
1143 }
1144
1145
1146 return ERROR_OK;
1147 }
1148
1149
1150
1151 /*
1152 * Cortex-A8 Reset fuctions
1153 */
1154
1155 static int cortex_a8_assert_reset(struct target *target)
1156 {
1157 struct armv7a_common *armv7a = target_to_armv7a(target);
1158
1159 LOG_DEBUG(" ");
1160
1161 /* FIXME when halt is requested, make it work somehow... */
1162
1163 /* Issue some kind of warm reset. */
1164 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1165 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1166 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1167 /* REVISIT handle "pulls" cases, if there's
1168 * hardware that needs them to work.
1169 */
1170 jtag_add_reset(0, 1);
1171 } else {
1172 LOG_ERROR("%s: how to reset?", target_name(target));
1173 return ERROR_FAIL;
1174 }
1175
1176 /* registers are now invalid */
1177 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1178
1179 target->state = TARGET_RESET;
1180
1181 return ERROR_OK;
1182 }
1183
1184 static int cortex_a8_deassert_reset(struct target *target)
1185 {
1186 int retval;
1187
1188 LOG_DEBUG(" ");
1189
1190 /* be certain SRST is off */
1191 jtag_add_reset(0, 0);
1192
1193 retval = cortex_a8_poll(target);
1194
1195 if (target->reset_halt) {
1196 if (target->state != TARGET_HALTED) {
1197 LOG_WARNING("%s: ran after reset and before halt ...",
1198 target_name(target));
1199 if ((retval = target_halt(target)) != ERROR_OK)
1200 return retval;
1201 }
1202 }
1203
1204 return ERROR_OK;
1205 }
1206
1207 /*
1208 * Cortex-A8 Memory access
1209 *
1210 * This is same Cortex M3 but we must also use the correct
1211 * ap number for every access.
1212 */
1213
1214 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1215 uint32_t size, uint32_t count, uint8_t *buffer)
1216 {
1217 struct armv7a_common *armv7a = target_to_armv7a(target);
1218 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1219 int retval = ERROR_INVALID_ARGUMENTS;
1220
1221 /* cortex_a8 handles unaligned memory access */
1222
1223 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1224
1225 if (count && buffer) {
1226 switch (size) {
1227 case 4:
1228 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1229 break;
1230 case 2:
1231 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1232 break;
1233 case 1:
1234 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1235 break;
1236 }
1237 }
1238
1239 return retval;
1240 }
1241
1242 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1243 uint32_t size, uint32_t count, uint8_t *buffer)
1244 {
1245 struct armv7a_common *armv7a = target_to_armv7a(target);
1246 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1247 int retval = ERROR_INVALID_ARGUMENTS;
1248
1249 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1250
1251 if (count && buffer) {
1252 switch (size) {
1253 case 4:
1254 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1255 break;
1256 case 2:
1257 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1258 break;
1259 case 1:
1260 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1261 break;
1262 }
1263 }
1264
1265 /* REVISIT this op is generic ARMv7-A/R stuff */
1266 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1267 {
1268 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
1269
1270 retval = dpm->prepare(dpm);
1271 if (retval != ERROR_OK)
1272 return retval;
1273
1274 /* The Cache handling will NOT work with MMU active, the
1275 * wrong addresses will be invalidated!
1276 *
1277 * For both ICache and DCache, walk all cache lines in the
1278 * address range. Cortex-A8 has fixed 64 byte line length.
1279 */
1280
1281 /* invalidate I-Cache */
1282 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1283 {
1284 /* ICIMVAU - Invalidate Cache single entry
1285 * with MVA to PoU
1286 * MCR p15, 0, r0, c7, c5, 1
1287 */
1288 for (uint32_t cacheline = address;
1289 cacheline < address + size * count;
1290 cacheline += 64) {
1291 retval = dpm->instr_write_data_r0(dpm,
1292 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1293 cacheline);
1294 }
1295 }
1296
1297 /* invalidate D-Cache */
1298 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1299 {
1300 /* DCIMVAC - Invalidate data Cache line
1301 * with MVA to PoC
1302 * MCR p15, 0, r0, c7, c6, 1
1303 */
1304 for (uint32_t cacheline = address;
1305 cacheline < address + size * count;
1306 cacheline += 64) {
1307 retval = dpm->instr_write_data_r0(dpm,
1308 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1309 cacheline);
1310 }
1311 }
1312
1313 /* (void) */ dpm->finish(dpm);
1314 }
1315
1316 return retval;
1317 }
1318
1319 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1320 uint32_t count, uint8_t *buffer)
1321 {
1322 return cortex_a8_write_memory(target, address, 4, count, buffer);
1323 }
1324
1325
1326 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1327 {
1328 #if 0
1329 u16 dcrdr;
1330
1331 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1332 *ctrl = (uint8_t)dcrdr;
1333 *value = (uint8_t)(dcrdr >> 8);
1334
1335 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1336
1337 /* write ack back to software dcc register
1338 * signify we have read data */
1339 if (dcrdr & (1 << 0))
1340 {
1341 dcrdr = 0;
1342 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1343 }
1344 #endif
1345 return ERROR_OK;
1346 }
1347
1348
1349 static int cortex_a8_handle_target_request(void *priv)
1350 {
1351 struct target *target = priv;
1352 struct armv7a_common *armv7a = target_to_armv7a(target);
1353 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1354
1355 if (!target_was_examined(target))
1356 return ERROR_OK;
1357 if (!target->dbg_msg_enabled)
1358 return ERROR_OK;
1359
1360 if (target->state == TARGET_RUNNING)
1361 {
1362 uint8_t data = 0;
1363 uint8_t ctrl = 0;
1364
1365 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1366
1367 /* check if we have data */
1368 if (ctrl & (1 << 0))
1369 {
1370 uint32_t request;
1371
1372 /* we assume target is quick enough */
1373 request = data;
1374 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1375 request |= (data << 8);
1376 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1377 request |= (data << 16);
1378 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1379 request |= (data << 24);
1380 target_request(target, request);
1381 }
1382 }
1383
1384 return ERROR_OK;
1385 }
1386
1387 /*
1388 * Cortex-A8 target information and configuration
1389 */
1390
1391 static int cortex_a8_examine_first(struct target *target)
1392 {
1393 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1394 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1395 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1396 int i;
1397 int retval = ERROR_OK;
1398 uint32_t didr, ctypr, ttypr, cpuid;
1399
1400 LOG_DEBUG("TODO");
1401
1402 /* Here we shall insert a proper ROM Table scan */
1403 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1404
1405 /* We do one extra read to ensure DAP is configured,
1406 * we call ahbap_debugport_init(swjdp) instead
1407 */
1408 ahbap_debugport_init(swjdp);
1409 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1410 if ((retval = mem_ap_read_atomic_u32(swjdp,
1411 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1412 {
1413 LOG_DEBUG("Examine failed");
1414 return retval;
1415 }
1416
1417 if ((retval = mem_ap_read_atomic_u32(swjdp,
1418 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1419 {
1420 LOG_DEBUG("Examine failed");
1421 return retval;
1422 }
1423
1424 if ((retval = mem_ap_read_atomic_u32(swjdp,
1425 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1426 {
1427 LOG_DEBUG("Examine failed");
1428 return retval;
1429 }
1430
1431 if ((retval = mem_ap_read_atomic_u32(swjdp,
1432 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1433 {
1434 LOG_DEBUG("Examine failed");
1435 return retval;
1436 }
1437
1438 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1439 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1440 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1441 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1442
1443 armv7a->armv4_5_common.core_type = ARM_MODE_MON;
1444 cortex_a8_dpm_setup(cortex_a8, didr);
1445
1446 /* Setup Breakpoint Register Pairs */
1447 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1448 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1449 cortex_a8->brp_num_available = cortex_a8->brp_num;
1450 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1451 // cortex_a8->brb_enabled = ????;
1452 for (i = 0; i < cortex_a8->brp_num; i++)
1453 {
1454 cortex_a8->brp_list[i].used = 0;
1455 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1456 cortex_a8->brp_list[i].type = BRP_NORMAL;
1457 else
1458 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1459 cortex_a8->brp_list[i].value = 0;
1460 cortex_a8->brp_list[i].control = 0;
1461 cortex_a8->brp_list[i].BRPn = i;
1462 }
1463
1464 /* Setup Watchpoint Register Pairs */
1465 cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
1466 cortex_a8->wrp_num_available = cortex_a8->wrp_num;
1467 cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
1468 for (i = 0; i < cortex_a8->wrp_num; i++)
1469 {
1470 cortex_a8->wrp_list[i].used = 0;
1471 cortex_a8->wrp_list[i].type = 0;
1472 cortex_a8->wrp_list[i].value = 0;
1473 cortex_a8->wrp_list[i].control = 0;
1474 cortex_a8->wrp_list[i].WRPn = i;
1475 }
1476 LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
1477 cortex_a8->brp_num , cortex_a8->wrp_num);
1478
1479 target_set_examined(target);
1480 return ERROR_OK;
1481 }
1482
1483 static int cortex_a8_examine(struct target *target)
1484 {
1485 int retval = ERROR_OK;
1486
1487 /* don't re-probe hardware after each reset */
1488 if (!target_was_examined(target))
1489 retval = cortex_a8_examine_first(target);
1490
1491 /* Configure core debug access */
1492 if (retval == ERROR_OK)
1493 retval = cortex_a8_init_debug_access(target);
1494
1495 return retval;
1496 }
1497
1498 /*
1499 * Cortex-A8 target creation and initialization
1500 */
1501
1502 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1503 struct target *target)
1504 {
1505 /* examine_first() does a bunch of this */
1506 return ERROR_OK;
1507 }
1508
1509 static int cortex_a8_init_arch_info(struct target *target,
1510 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1511 {
1512 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1513 struct arm *armv4_5 = &armv7a->armv4_5_common;
1514 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1515
1516 /* Setup struct cortex_a8_common */
1517 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1518 armv4_5->arch_info = armv7a;
1519
1520 /* prepare JTAG information for the new target */
1521 cortex_a8->jtag_info.tap = tap;
1522 cortex_a8->jtag_info.scann_size = 4;
1523
1524 swjdp->dp_select_value = -1;
1525 swjdp->ap_csw_value = -1;
1526 swjdp->ap_tar_value = -1;
1527 swjdp->jtag_info = &cortex_a8->jtag_info;
1528 swjdp->memaccess_tck = 80;
1529
1530 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1531 swjdp->tar_autoincr_block = (1 << 10);
1532
1533 cortex_a8->fast_reg_read = 0;
1534
1535 /* register arch-specific functions */
1536 armv7a->examine_debug_reason = NULL;
1537
1538 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1539
1540 armv7a->pre_restore_context = NULL;
1541 armv7a->post_restore_context = NULL;
1542 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1543 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1544 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1545 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1546 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1547 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1548 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1549 armv7a->armv4_5_mmu.mmu_enabled = 0;
1550
1551
1552 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1553
1554 /* REVISIT v7a setup should be in a v7a-specific routine */
1555 armv4_5_init_arch_info(target, armv4_5);
1556 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1557
1558 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1559
1560 return ERROR_OK;
1561 }
1562
1563 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1564 {
1565 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1566
1567 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1568
1569 return ERROR_OK;
1570 }
1571
1572 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1573 {
1574 struct target *target = get_current_target(CMD_CTX);
1575 struct armv7a_common *armv7a = target_to_armv7a(target);
1576
1577 return armv4_5_handle_cache_info_command(CMD_CTX,
1578 &armv7a->armv4_5_mmu.armv4_5_cache);
1579 }
1580
1581
1582 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1583 {
1584 struct target *target = get_current_target(CMD_CTX);
1585
1586 cortex_a8_init_debug_access(target);
1587
1588 return ERROR_OK;
1589 }
1590
1591 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1592 {
1593 .name = "cache_info",
1594 .handler = &cortex_a8_handle_cache_info_command,
1595 .mode = COMMAND_EXEC,
1596 .help = "display information about target caches",
1597 },
1598 {
1599 .name = "dbginit",
1600 .handler = &cortex_a8_handle_dbginit_command,
1601 .mode = COMMAND_EXEC,
1602 .help = "Initialize core debug",
1603 },
1604 COMMAND_REGISTRATION_DONE
1605 };
1606 static const struct command_registration cortex_a8_command_handlers[] = {
1607 {
1608 .chain = arm_command_handlers,
1609 },
1610 {
1611 .chain = armv7a_command_handlers,
1612 },
1613 {
1614 .name = "cortex_a8",
1615 .mode = COMMAND_ANY,
1616 .help = "Cortex-A8 command group",
1617 .chain = cortex_a8_exec_command_handlers,
1618 },
1619 COMMAND_REGISTRATION_DONE
1620 };
1621
1622 struct target_type cortexa8_target = {
1623 .name = "cortex_a8",
1624
1625 .poll = cortex_a8_poll,
1626 .arch_state = armv7a_arch_state,
1627
1628 .target_request_data = NULL,
1629
1630 .halt = cortex_a8_halt,
1631 .resume = cortex_a8_resume,
1632 .step = cortex_a8_step,
1633
1634 .assert_reset = cortex_a8_assert_reset,
1635 .deassert_reset = cortex_a8_deassert_reset,
1636 .soft_reset_halt = NULL,
1637
1638 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1639
1640 .read_memory = cortex_a8_read_memory,
1641 .write_memory = cortex_a8_write_memory,
1642 .bulk_write_memory = cortex_a8_bulk_write_memory,
1643
1644 .checksum_memory = arm_checksum_memory,
1645 .blank_check_memory = arm_blank_check_memory,
1646
1647 .run_algorithm = armv4_5_run_algorithm,
1648
1649 .add_breakpoint = cortex_a8_add_breakpoint,
1650 .remove_breakpoint = cortex_a8_remove_breakpoint,
1651 .add_watchpoint = NULL,
1652 .remove_watchpoint = NULL,
1653
1654 .commands = cortex_a8_command_handlers,
1655 .target_create = cortex_a8_target_create,
1656 .init_target = cortex_a8_init_target,
1657 .examine = cortex_a8_examine,
1658 };
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