1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
35 #include "arm7_9_common.h"
37 extern char* cortex_a8_state_strings
[];
39 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
41 #define CPUID 0x54011D00
42 /* Debug Control Block */
43 #define CPUDBG_DIDR 0x000
44 #define CPUDBG_WFAR 0x018
45 #define CPUDBG_VCR 0x01C
46 #define CPUDBG_ECR 0x024
47 #define CPUDBG_DSCCR 0x028
48 #define CPUDBG_DTRRX 0x080
49 #define CPUDBG_ITR 0x084
50 #define CPUDBG_DSCR 0x088
51 #define CPUDBG_DTRTX 0x08c
52 #define CPUDBG_DRCR 0x090
53 #define CPUDBG_BVR_BASE 0x100
54 #define CPUDBG_BCR_BASE 0x140
55 #define CPUDBG_WVR_BASE 0x180
57 #define CPUDBG_OSLAR 0x300
58 #define CPUDBG_OSLSR 0x304
59 #define CPUDBG_OSSRR 0x308
61 #define CPUDBG_PRCR 0x310
62 #define CPUDBG_PRSR 0x314
64 #define CPUDBG_CPUID 0xD00
65 #define CPUDBG_CTYPR 0xD04
66 #define CPUDBG_TTYPR 0xD0C
67 #define CPUDBG_LOCKACCESS 0xFB0
68 #define CPUDBG_LOCKSTATUS 0xFB4
69 #define CPUDBG_AUTHSTATUS 0xFB8
75 #define DSCR_CORE_HALTED 0
76 #define DSCR_CORE_RESTARTED 1
77 #define DSCR_EXT_INT_EN 13
78 #define DSCR_HALT_DBG_MODE 14
79 #define DSCR_MON_DBG_MODE 15
80 #define DSCR_INSTR_COMP 24
81 #define DSCR_DTR_TX_FULL 29
83 typedef struct cortex_a8_brp_s
92 typedef struct cortex_a8_wrp_s
101 typedef struct cortex_a8_common_s
104 arm_jtag_t jtag_info
;
106 /* Context information */
107 uint32_t cpudbg_dscr
;
108 uint32_t nvic_dfsr
; /* Debug Fault Status Register - shows reason for debug halt */
109 uint32_t nvic_icsr
; /* Interrupt Control State Register - shows active and pending IRQ */
111 /* Saved cp15 registers */
112 uint32_t cp15_control_reg
;
113 uint32_t cp15_aux_control_reg
;
115 /* Breakpoint register pairs */
118 int brp_num_available
;
120 cortex_a8_brp_t
*brp_list
;
122 /* Watchpoint register pairs */
124 int wrp_num_available
;
125 cortex_a8_wrp_t
*wrp_list
;
129 uint32_t *intsetenable
;
131 /* Use cortex_a8_read_regs_through_mem for fast register reads */
134 armv7a_common_t armv7a_common
;
136 } cortex_a8_common_t
;
138 extern int cortex_a8_init_arch_info(target_t
*target
, cortex_a8_common_t
*cortex_a8
, jtag_tap_t
*tap
);
139 int cortex_a8_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
140 int cortex_a8_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
142 #endif /* CORTEX_A8_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)