1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m_store_core_reg_u32(struct target
*target
,
63 uint32_t num
, uint32_t value
);
64 static void cortex_m_dwt_free(struct target
*target
);
66 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
67 uint32_t *value
, int regnum
)
69 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
70 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
74 /* because the DCB_DCRDR is used for the emulated dcc channel
75 * we have to save/restore the DCB_DCRDR when used */
76 if (target
->dbg_msg_enabled
) {
77 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
78 if (retval
!= ERROR_OK
)
82 retval
= mem_ap_write_u32(swjdp
, DCB_DCRSR
, regnum
);
83 if (retval
!= ERROR_OK
)
86 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DCRDR
, value
);
87 if (retval
!= ERROR_OK
)
90 if (target
->dbg_msg_enabled
) {
91 /* restore DCB_DCRDR - this needs to be in a separate
92 * transaction otherwise the emulated DCC channel breaks */
93 if (retval
== ERROR_OK
)
94 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
100 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
101 uint32_t value
, int regnum
)
103 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
104 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
108 /* because the DCB_DCRDR is used for the emulated dcc channel
109 * we have to save/restore the DCB_DCRDR when used */
110 if (target
->dbg_msg_enabled
) {
111 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
112 if (retval
!= ERROR_OK
)
116 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, value
);
117 if (retval
!= ERROR_OK
)
120 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
121 if (retval
!= ERROR_OK
)
124 if (target
->dbg_msg_enabled
) {
125 /* restore DCB_DCRDR - this needs to be in a seperate
126 * transaction otherwise the emulated DCC channel breaks */
127 if (retval
== ERROR_OK
)
128 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
134 static int cortex_m_write_debug_halt_mask(struct target
*target
,
135 uint32_t mask_on
, uint32_t mask_off
)
137 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
138 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
140 /* mask off status bits */
141 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
142 /* create new register mask */
143 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
145 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
148 static int cortex_m_clear_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
154 /* clear step if any */
155 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
157 /* Read Debug Fault Status Register */
158 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
159 if (retval
!= ERROR_OK
)
162 /* Clear Debug Fault Status */
163 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
164 if (retval
!= ERROR_OK
)
166 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
171 static int cortex_m_single_step_core(struct target
*target
)
173 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
174 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
178 /* backup dhcsr reg */
179 dhcsr_save
= cortex_m
->dcb_dhcsr
;
181 /* Mask interrupts before clearing halt, if done already. This avoids
182 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
183 * HALT can put the core into an unknown state.
185 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
186 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
187 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
188 if (retval
!= ERROR_OK
)
191 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
192 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
193 if (retval
!= ERROR_OK
)
197 /* restore dhcsr reg */
198 cortex_m
->dcb_dhcsr
= dhcsr_save
;
199 cortex_m_clear_halt(target
);
204 static int cortex_m_enable_fpb(struct target
*target
)
206 int retval
= target_write_u32(target
, FP_CTRL
, 3);
207 if (retval
!= ERROR_OK
)
210 /* check the fpb is actually enabled */
212 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
213 if (retval
!= ERROR_OK
)
222 static int cortex_m_endreset_event(struct target
*target
)
227 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
228 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
229 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
230 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
231 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
233 /* REVISIT The four debug monitor bits are currently ignored... */
234 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
235 if (retval
!= ERROR_OK
)
237 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
239 /* this register is used for emulated dcc channel */
240 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
241 if (retval
!= ERROR_OK
)
244 /* Enable debug requests */
245 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
246 if (retval
!= ERROR_OK
)
248 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
249 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
250 if (retval
!= ERROR_OK
)
254 /* clear any interrupt masking */
255 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
257 /* Enable features controlled by ITM and DWT blocks, and catch only
258 * the vectors we were told to pay attention to.
260 * Target firmware is responsible for all fault handling policy
261 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
262 * or manual updates to the NVIC SHCSR and CCR registers.
264 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
265 if (retval
!= ERROR_OK
)
268 /* Paranoia: evidently some (early?) chips don't preserve all the
269 * debug state (including FBP, DWT, etc) across reset...
273 retval
= cortex_m_enable_fpb(target
);
274 if (retval
!= ERROR_OK
) {
275 LOG_ERROR("Failed to enable the FPB");
279 cortex_m
->fpb_enabled
= 1;
281 /* Restore FPB registers */
282 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
283 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
284 if (retval
!= ERROR_OK
)
288 /* Restore DWT registers */
289 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
290 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
292 if (retval
!= ERROR_OK
)
294 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
296 if (retval
!= ERROR_OK
)
298 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
299 dwt_list
[i
].function
);
300 if (retval
!= ERROR_OK
)
303 retval
= dap_run(swjdp
);
304 if (retval
!= ERROR_OK
)
307 register_cache_invalidate(armv7m
->arm
.core_cache
);
309 /* make sure we have latest dhcsr flags */
310 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
315 static int cortex_m_examine_debug_reason(struct target
*target
)
317 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
319 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
320 * only check the debug reason if we don't know it already */
322 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
323 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
324 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
325 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
326 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
327 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
328 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
329 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
330 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
331 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
332 else /* EXTERNAL, HALTED */
333 target
->debug_reason
= DBG_REASON_UNDEFINED
;
339 static int cortex_m_examine_exception_reason(struct target
*target
)
341 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
342 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
343 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
346 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
347 if (retval
!= ERROR_OK
)
349 switch (armv7m
->exception_number
) {
352 case 3: /* Hard Fault */
353 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
354 if (retval
!= ERROR_OK
)
356 if (except_sr
& 0x40000000) {
357 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
358 if (retval
!= ERROR_OK
)
362 case 4: /* Memory Management */
363 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
364 if (retval
!= ERROR_OK
)
366 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
367 if (retval
!= ERROR_OK
)
370 case 5: /* Bus Fault */
371 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
372 if (retval
!= ERROR_OK
)
374 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
375 if (retval
!= ERROR_OK
)
378 case 6: /* Usage Fault */
379 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
380 if (retval
!= ERROR_OK
)
383 case 11: /* SVCall */
385 case 12: /* Debug Monitor */
386 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
387 if (retval
!= ERROR_OK
)
390 case 14: /* PendSV */
392 case 15: /* SysTick */
398 retval
= dap_run(swjdp
);
399 if (retval
== ERROR_OK
)
400 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
401 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
402 armv7m_exception_string(armv7m
->exception_number
),
403 shcsr
, except_sr
, cfsr
, except_ar
);
407 static int cortex_m_debug_entry(struct target
*target
)
412 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
413 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
414 struct arm
*arm
= &armv7m
->arm
;
415 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
420 cortex_m_clear_halt(target
);
421 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
422 if (retval
!= ERROR_OK
)
425 retval
= armv7m
->examine_debug_reason(target
);
426 if (retval
!= ERROR_OK
)
429 /* Examine target state and mode
430 * First load register accessible through core debug port */
431 int num_regs
= arm
->core_cache
->num_regs
;
433 for (i
= 0; i
< num_regs
; i
++) {
434 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
436 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
440 xPSR
= buf_get_u32(r
->value
, 0, 32);
442 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
445 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
448 /* Are we in an exception handler */
450 armv7m
->exception_number
= (xPSR
& 0x1FF);
452 arm
->core_mode
= ARM_MODE_HANDLER
;
453 arm
->map
= armv7m_msp_reg_map
;
455 unsigned control
= buf_get_u32(arm
->core_cache
456 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
458 /* is this thread privileged? */
459 arm
->core_mode
= control
& 1
460 ? ARM_MODE_USER_THREAD
463 /* which stack is it using? */
465 arm
->map
= armv7m_psp_reg_map
;
467 arm
->map
= armv7m_msp_reg_map
;
469 armv7m
->exception_number
= 0;
472 if (armv7m
->exception_number
)
473 cortex_m_examine_exception_reason(target
);
475 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
476 arm_mode_name(arm
->core_mode
),
477 buf_get_u32(arm
->pc
->value
, 0, 32),
478 target_state_name(target
));
480 if (armv7m
->post_debug_entry
) {
481 retval
= armv7m
->post_debug_entry(target
);
482 if (retval
!= ERROR_OK
)
489 static int cortex_m_poll(struct target
*target
)
491 int detected_failure
= ERROR_OK
;
492 int retval
= ERROR_OK
;
493 enum target_state prev_target_state
= target
->state
;
494 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
495 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
497 /* Read from Debug Halting Control and Status Register */
498 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
499 if (retval
!= ERROR_OK
) {
500 target
->state
= TARGET_UNKNOWN
;
504 /* Recover from lockup. See ARMv7-M architecture spec,
505 * section B1.5.15 "Unrecoverable exception cases".
507 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
508 LOG_ERROR("%s -- clearing lockup after double fault",
509 target_name(target
));
510 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
511 target
->debug_reason
= DBG_REASON_DBGRQ
;
513 /* We have to execute the rest (the "finally" equivalent, but
514 * still throw this exception again).
516 detected_failure
= ERROR_FAIL
;
518 /* refresh status bits */
519 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
520 if (retval
!= ERROR_OK
)
524 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
525 target
->state
= TARGET_RESET
;
529 if (target
->state
== TARGET_RESET
) {
530 /* Cannot switch context while running so endreset is
531 * called with target->state == TARGET_RESET
533 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
534 cortex_m
->dcb_dhcsr
);
535 retval
= cortex_m_endreset_event(target
);
536 if (retval
!= ERROR_OK
) {
537 target
->state
= TARGET_UNKNOWN
;
540 target
->state
= TARGET_RUNNING
;
541 prev_target_state
= TARGET_RUNNING
;
544 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
545 target
->state
= TARGET_HALTED
;
547 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
548 retval
= cortex_m_debug_entry(target
);
549 if (retval
!= ERROR_OK
)
552 if (arm_semihosting(target
, &retval
) != 0)
555 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
557 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
559 retval
= cortex_m_debug_entry(target
);
560 if (retval
!= ERROR_OK
)
563 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
567 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
568 * How best to model low power modes?
571 if (target
->state
== TARGET_UNKNOWN
) {
572 /* check if processor is retiring instructions */
573 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
574 target
->state
= TARGET_RUNNING
;
579 /* Did we detect a failure condition that we cleared? */
580 if (detected_failure
!= ERROR_OK
)
581 retval
= detected_failure
;
585 static int cortex_m_halt(struct target
*target
)
587 LOG_DEBUG("target->state: %s",
588 target_state_name(target
));
590 if (target
->state
== TARGET_HALTED
) {
591 LOG_DEBUG("target was already halted");
595 if (target
->state
== TARGET_UNKNOWN
)
596 LOG_WARNING("target was in unknown state when halt was requested");
598 if (target
->state
== TARGET_RESET
) {
599 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
600 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
601 return ERROR_TARGET_FAILURE
;
603 /* we came here in a reset_halt or reset_init sequence
604 * debug entry was already prepared in cortex_m3_assert_reset()
606 target
->debug_reason
= DBG_REASON_DBGRQ
;
612 /* Write to Debug Halting Control and Status Register */
613 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
615 target
->debug_reason
= DBG_REASON_DBGRQ
;
620 static int cortex_m_soft_reset_halt(struct target
*target
)
622 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
623 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
624 uint32_t dcb_dhcsr
= 0;
625 int retval
, timeout
= 0;
627 /* soft_reset_halt is deprecated on cortex_m as the same functionality
628 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
629 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
630 * core, not the peripherals */
631 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
633 /* Enter debug state on reset; restore DEMCR in endreset_event() */
634 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
635 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
636 if (retval
!= ERROR_OK
)
639 /* Request a core-only reset */
640 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
641 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
642 if (retval
!= ERROR_OK
)
644 target
->state
= TARGET_RESET
;
646 /* registers are now invalid */
647 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
649 while (timeout
< 100) {
650 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
651 if (retval
== ERROR_OK
) {
652 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
653 &cortex_m
->nvic_dfsr
);
654 if (retval
!= ERROR_OK
)
656 if ((dcb_dhcsr
& S_HALT
)
657 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
658 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
660 (unsigned) dcb_dhcsr
,
661 (unsigned) cortex_m
->nvic_dfsr
);
662 cortex_m_poll(target
);
663 /* FIXME restore user's vector catch config */
666 LOG_DEBUG("waiting for system reset-halt, "
667 "DHCSR 0x%08x, %d ms",
668 (unsigned) dcb_dhcsr
, timeout
);
677 void cortex_m_enable_breakpoints(struct target
*target
)
679 struct breakpoint
*breakpoint
= target
->breakpoints
;
681 /* set any pending breakpoints */
683 if (!breakpoint
->set
)
684 cortex_m_set_breakpoint(target
, breakpoint
);
685 breakpoint
= breakpoint
->next
;
689 static int cortex_m_resume(struct target
*target
, int current
,
690 uint32_t address
, int handle_breakpoints
, int debug_execution
)
692 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
693 struct breakpoint
*breakpoint
= NULL
;
697 if (target
->state
!= TARGET_HALTED
) {
698 LOG_WARNING("target not halted");
699 return ERROR_TARGET_NOT_HALTED
;
702 if (!debug_execution
) {
703 target_free_all_working_areas(target
);
704 cortex_m_enable_breakpoints(target
);
705 cortex_m_enable_watchpoints(target
);
708 if (debug_execution
) {
709 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
711 /* Disable interrupts */
712 /* We disable interrupts in the PRIMASK register instead of
713 * masking with C_MASKINTS. This is probably the same issue
714 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
715 * in parallel with disabled interrupts can cause local faults
718 * REVISIT this clearly breaks non-debug execution, since the
719 * PRIMASK register state isn't saved/restored... workaround
720 * by never resuming app code after debug execution.
722 buf_set_u32(r
->value
, 0, 1, 1);
726 /* Make sure we are in Thumb mode */
727 r
= armv7m
->arm
.cpsr
;
728 buf_set_u32(r
->value
, 24, 1, 1);
733 /* current = 1: continue on current pc, otherwise continue at <address> */
736 buf_set_u32(r
->value
, 0, 32, address
);
741 /* if we halted last time due to a bkpt instruction
742 * then we have to manually step over it, otherwise
743 * the core will break again */
745 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
747 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
749 resume_pc
= buf_get_u32(r
->value
, 0, 32);
751 armv7m_restore_context(target
);
753 /* the front-end may request us not to handle breakpoints */
754 if (handle_breakpoints
) {
755 /* Single step past breakpoint at current address */
756 breakpoint
= breakpoint_find(target
, resume_pc
);
758 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %" PRIu32
")",
760 breakpoint
->unique_id
);
761 cortex_m_unset_breakpoint(target
, breakpoint
);
762 cortex_m_single_step_core(target
);
763 cortex_m_set_breakpoint(target
, breakpoint
);
768 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
770 target
->debug_reason
= DBG_REASON_NOTHALTED
;
772 /* registers are now invalid */
773 register_cache_invalidate(armv7m
->arm
.core_cache
);
775 if (!debug_execution
) {
776 target
->state
= TARGET_RUNNING
;
777 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
778 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
780 target
->state
= TARGET_DEBUG_RUNNING
;
781 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
782 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
788 /* int irqstepcount = 0; */
789 static int cortex_m_step(struct target
*target
, int current
,
790 uint32_t address
, int handle_breakpoints
)
792 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
793 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
794 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
795 struct breakpoint
*breakpoint
= NULL
;
796 struct reg
*pc
= armv7m
->arm
.pc
;
797 bool bkpt_inst_found
= false;
799 bool isr_timed_out
= false;
801 if (target
->state
!= TARGET_HALTED
) {
802 LOG_WARNING("target not halted");
803 return ERROR_TARGET_NOT_HALTED
;
806 /* current = 1: continue on current pc, otherwise continue at <address> */
808 buf_set_u32(pc
->value
, 0, 32, address
);
810 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
812 /* the front-end may request us not to handle breakpoints */
813 if (handle_breakpoints
) {
814 breakpoint
= breakpoint_find(target
, pc_value
);
816 cortex_m_unset_breakpoint(target
, breakpoint
);
819 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
821 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
823 armv7m_restore_context(target
);
825 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
827 /* if no bkpt instruction is found at pc then we can perform
828 * a normal step, otherwise we have to manually step over the bkpt
829 * instruction - as such simulate a step */
830 if (bkpt_inst_found
== false) {
831 /* Automatic ISR masking mode off: Just step over the next instruction */
832 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
))
833 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
835 /* Process interrupts during stepping in a way they don't interfere
840 * Set a temporary break point at the current pc and let the core run
841 * with interrupts enabled. Pending interrupts get served and we run
842 * into the breakpoint again afterwards. Then we step over the next
843 * instruction with interrupts disabled.
845 * If the pending interrupts don't complete within time, we leave the
846 * core running. This may happen if the interrupts trigger faster
847 * than the core can process them or the handler doesn't return.
849 * If no more breakpoints are available we simply do a step with
850 * interrupts enabled.
856 * If a break point is already set on the lower half word then a break point on
857 * the upper half word will not break again when the core is restarted. So we
858 * just step over the instruction with interrupts disabled.
860 * The documentation has no information about this, it was found by observation
861 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
862 * suffer from this problem.
864 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
865 * address has it always cleared. The former is done to indicate thumb mode
869 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
870 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
871 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
872 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
873 /* Re-enable interrupts */
874 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
878 /* Set a temporary break point */
880 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
882 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
883 bool tmp_bp_set
= (retval
== ERROR_OK
);
885 /* No more breakpoints left, just do a step */
887 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
890 LOG_DEBUG("Starting core to serve pending interrupts");
891 int64_t t_start
= timeval_ms();
892 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
894 /* Wait for pending handlers to complete or timeout */
896 retval
= mem_ap_read_atomic_u32(swjdp
,
898 &cortex_m
->dcb_dhcsr
);
899 if (retval
!= ERROR_OK
) {
900 target
->state
= TARGET_UNKNOWN
;
903 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
904 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
906 /* only remove breakpoint if we created it */
908 cortex_m_unset_breakpoint(target
, breakpoint
);
910 /* Remove the temporary breakpoint */
911 breakpoint_remove(target
, pc_value
);
915 LOG_DEBUG("Interrupt handlers didn't complete within time, "
916 "leaving target running");
918 /* Step over next instruction with interrupts disabled */
919 cortex_m_write_debug_halt_mask(target
,
922 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
923 /* Re-enable interrupts */
924 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
931 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
932 if (retval
!= ERROR_OK
)
935 /* registers are now invalid */
936 register_cache_invalidate(armv7m
->arm
.core_cache
);
939 cortex_m_set_breakpoint(target
, breakpoint
);
942 /* Leave the core running. The user has to stop execution manually. */
943 target
->debug_reason
= DBG_REASON_NOTHALTED
;
944 target
->state
= TARGET_RUNNING
;
948 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
949 " nvic_icsr = 0x%" PRIx32
,
950 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
952 retval
= cortex_m_debug_entry(target
);
953 if (retval
!= ERROR_OK
)
955 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
957 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
958 " nvic_icsr = 0x%" PRIx32
,
959 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
964 static int cortex_m_assert_reset(struct target
*target
)
966 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
967 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
968 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
970 LOG_DEBUG("target->state: %s",
971 target_state_name(target
));
973 enum reset_types jtag_reset_config
= jtag_get_reset_config();
975 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
976 /* allow scripts to override the reset event */
978 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
979 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
980 target
->state
= TARGET_RESET
;
985 /* some cores support connecting while srst is asserted
986 * use that mode is it has been configured */
988 bool srst_asserted
= false;
990 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
991 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
992 adapter_assert_reset();
993 srst_asserted
= true;
996 /* Enable debug requests */
998 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
999 if (retval
!= ERROR_OK
)
1001 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
1002 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1003 if (retval
!= ERROR_OK
)
1007 /* If the processor is sleeping in a WFI or WFE instruction, the
1008 * C_HALT bit must be asserted to regain control */
1009 if (cortex_m
->dcb_dhcsr
& S_SLEEP
) {
1010 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1011 if (retval
!= ERROR_OK
)
1015 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1016 if (retval
!= ERROR_OK
)
1019 if (!target
->reset_halt
) {
1020 /* Set/Clear C_MASKINTS in a separate operation */
1021 if (cortex_m
->dcb_dhcsr
& C_MASKINTS
) {
1022 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1023 DBGKEY
| C_DEBUGEN
| C_HALT
);
1024 if (retval
!= ERROR_OK
)
1028 /* clear any debug flags before resuming */
1029 cortex_m_clear_halt(target
);
1031 /* clear C_HALT in dhcsr reg */
1032 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1034 /* Halt in debug on reset; endreset_event() restores DEMCR.
1036 * REVISIT catching BUSERR presumably helps to defend against
1037 * bad vector table entries. Should this include MMERR or
1040 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1041 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1042 if (retval
!= ERROR_OK
)
1046 if (jtag_reset_config
& RESET_HAS_SRST
) {
1047 /* default to asserting srst */
1049 adapter_assert_reset();
1051 /* Use a standard Cortex-M3 software reset mechanism.
1052 * We default to using VECRESET as it is supported on all current cores.
1053 * This has the disadvantage of not resetting the peripherals, so a
1054 * reset-init event handler is needed to perform any peripheral resets.
1056 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1057 ? "SYSRESETREQ" : "VECTRESET");
1059 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1060 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1061 "handler to reset any peripherals or configure hardware srst support.");
1064 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1065 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1066 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1067 if (retval
!= ERROR_OK
)
1068 LOG_DEBUG("Ignoring AP write error right after reset");
1070 retval
= ahbap_debugport_init(swjdp
);
1071 if (retval
!= ERROR_OK
) {
1072 LOG_ERROR("DP initialisation failed");
1077 /* I do not know why this is necessary, but it
1078 * fixes strange effects (step/resume cause NMI
1079 * after reset) on LM3S6918 -- Michael Schwingen
1082 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1083 if (retval
!= ERROR_OK
)
1088 target
->state
= TARGET_RESET
;
1089 jtag_add_sleep(50000);
1091 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1093 if (target
->reset_halt
) {
1094 retval
= target_halt(target
);
1095 if (retval
!= ERROR_OK
)
1102 static int cortex_m_deassert_reset(struct target
*target
)
1104 LOG_DEBUG("target->state: %s",
1105 target_state_name(target
));
1107 /* deassert reset lines */
1108 adapter_deassert_reset();
1110 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1112 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1113 !(jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1114 int retval
= ahbap_debugport_init(target_to_cm(target
)->armv7m
.arm
.dap
);
1115 if (retval
!= ERROR_OK
) {
1116 LOG_ERROR("DP initialisation failed");
1124 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1129 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1130 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1132 if (breakpoint
->set
) {
1133 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1137 if (cortex_m
->auto_bp_type
)
1138 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1140 if (breakpoint
->type
== BKPT_HARD
) {
1141 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1143 if (fp_num
>= cortex_m
->fp_num_code
) {
1144 LOG_ERROR("Can not find free FPB Comparator!");
1147 breakpoint
->set
= fp_num
+ 1;
1148 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1149 comparator_list
[fp_num
].used
= 1;
1150 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1151 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1152 comparator_list
[fp_num
].fpcr_value
);
1153 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1155 comparator_list
[fp_num
].fpcr_value
);
1156 if (!cortex_m
->fpb_enabled
) {
1157 LOG_DEBUG("FPB wasn't enabled, do it now");
1158 retval
= cortex_m_enable_fpb(target
);
1159 if (retval
!= ERROR_OK
) {
1160 LOG_ERROR("Failed to enable the FPB");
1164 cortex_m
->fpb_enabled
= 1;
1166 } else if (breakpoint
->type
== BKPT_SOFT
) {
1169 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1170 * semihosting; don't use that. Otherwise the BKPT
1171 * parameter is arbitrary.
1173 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1174 retval
= target_read_memory(target
,
1175 breakpoint
->address
& 0xFFFFFFFE,
1176 breakpoint
->length
, 1,
1177 breakpoint
->orig_instr
);
1178 if (retval
!= ERROR_OK
)
1180 retval
= target_write_memory(target
,
1181 breakpoint
->address
& 0xFFFFFFFE,
1182 breakpoint
->length
, 1,
1184 if (retval
!= ERROR_OK
)
1186 breakpoint
->set
= true;
1189 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1190 breakpoint
->unique_id
,
1191 (int)(breakpoint
->type
),
1192 breakpoint
->address
,
1199 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1202 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1203 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1205 if (!breakpoint
->set
) {
1206 LOG_WARNING("breakpoint not set");
1210 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1211 breakpoint
->unique_id
,
1212 (int)(breakpoint
->type
),
1213 breakpoint
->address
,
1217 if (breakpoint
->type
== BKPT_HARD
) {
1218 int fp_num
= breakpoint
->set
- 1;
1219 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1220 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1223 comparator_list
[fp_num
].used
= 0;
1224 comparator_list
[fp_num
].fpcr_value
= 0;
1225 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1226 comparator_list
[fp_num
].fpcr_value
);
1228 /* restore original instruction (kept in target endianness) */
1229 if (breakpoint
->length
== 4) {
1230 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1231 breakpoint
->orig_instr
);
1232 if (retval
!= ERROR_OK
)
1235 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1236 breakpoint
->orig_instr
);
1237 if (retval
!= ERROR_OK
)
1241 breakpoint
->set
= false;
1246 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1248 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1250 if (cortex_m
->auto_bp_type
)
1251 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1253 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1254 if (breakpoint
->type
== BKPT_HARD
) {
1255 LOG_INFO("flash patch comparator requested outside code memory region");
1256 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1259 if (breakpoint
->type
== BKPT_SOFT
) {
1260 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1265 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m
->fp_code_available
< 1)) {
1266 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1267 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1270 if (breakpoint
->length
== 3) {
1271 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1272 breakpoint
->length
= 2;
1275 if ((breakpoint
->length
!= 2)) {
1276 LOG_INFO("only breakpoints of two bytes length supported");
1277 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1280 if (breakpoint
->type
== BKPT_HARD
)
1281 cortex_m
->fp_code_available
--;
1283 return cortex_m_set_breakpoint(target
, breakpoint
);
1286 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1288 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1290 /* REVISIT why check? FBP can be updated with core running ... */
1291 if (target
->state
!= TARGET_HALTED
) {
1292 LOG_WARNING("target not halted");
1293 return ERROR_TARGET_NOT_HALTED
;
1296 if (cortex_m
->auto_bp_type
)
1297 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1299 if (breakpoint
->set
)
1300 cortex_m_unset_breakpoint(target
, breakpoint
);
1302 if (breakpoint
->type
== BKPT_HARD
)
1303 cortex_m
->fp_code_available
++;
1308 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1311 uint32_t mask
, temp
;
1312 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1314 /* watchpoint params were validated earlier */
1316 temp
= watchpoint
->length
;
1323 /* REVISIT Don't fully trust these "not used" records ... users
1324 * may set up breakpoints by hand, e.g. dual-address data value
1325 * watchpoint using comparator #1; comparator #0 matching cycle
1326 * count; send data trace info through ITM and TPIU; etc
1328 struct cortex_m_dwt_comparator
*comparator
;
1330 for (comparator
= cortex_m
->dwt_comparator_list
;
1331 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1332 comparator
++, dwt_num
++)
1334 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1335 LOG_ERROR("Can not find free DWT Comparator");
1338 comparator
->used
= 1;
1339 watchpoint
->set
= dwt_num
+ 1;
1341 comparator
->comp
= watchpoint
->address
;
1342 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1345 comparator
->mask
= mask
;
1346 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1349 switch (watchpoint
->rw
) {
1351 comparator
->function
= 5;
1354 comparator
->function
= 6;
1357 comparator
->function
= 7;
1360 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1361 comparator
->function
);
1363 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1364 watchpoint
->unique_id
, dwt_num
,
1365 (unsigned) comparator
->comp
,
1366 (unsigned) comparator
->mask
,
1367 (unsigned) comparator
->function
);
1371 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1373 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1374 struct cortex_m_dwt_comparator
*comparator
;
1377 if (!watchpoint
->set
) {
1378 LOG_WARNING("watchpoint (wpid: %d) not set",
1379 watchpoint
->unique_id
);
1383 dwt_num
= watchpoint
->set
- 1;
1385 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1386 watchpoint
->unique_id
, dwt_num
,
1387 (unsigned) watchpoint
->address
);
1389 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1390 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1394 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1395 comparator
->used
= 0;
1396 comparator
->function
= 0;
1397 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1398 comparator
->function
);
1400 watchpoint
->set
= false;
1405 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1407 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1409 if (cortex_m
->dwt_comp_available
< 1) {
1410 LOG_DEBUG("no comparators?");
1411 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1414 /* hardware doesn't support data value masking */
1415 if (watchpoint
->mask
!= ~(uint32_t)0) {
1416 LOG_DEBUG("watchpoint value masks not supported");
1417 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1420 /* hardware allows address masks of up to 32K */
1423 for (mask
= 0; mask
< 16; mask
++) {
1424 if ((1u << mask
) == watchpoint
->length
)
1428 LOG_DEBUG("unsupported watchpoint length");
1429 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1431 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1432 LOG_DEBUG("watchpoint address is unaligned");
1433 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1436 /* Caller doesn't seem to be able to describe watching for data
1437 * values of zero; that flags "no value".
1439 * REVISIT This DWT may well be able to watch for specific data
1440 * values. Requires comparator #1 to set DATAVMATCH and match
1441 * the data, and another comparator (DATAVADDR0) matching addr.
1443 if (watchpoint
->value
) {
1444 LOG_DEBUG("data value watchpoint not YET supported");
1445 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1448 cortex_m
->dwt_comp_available
--;
1449 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1454 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1456 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1458 /* REVISIT why check? DWT can be updated with core running ... */
1459 if (target
->state
!= TARGET_HALTED
) {
1460 LOG_WARNING("target not halted");
1461 return ERROR_TARGET_NOT_HALTED
;
1464 if (watchpoint
->set
)
1465 cortex_m_unset_watchpoint(target
, watchpoint
);
1467 cortex_m
->dwt_comp_available
++;
1468 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1473 void cortex_m_enable_watchpoints(struct target
*target
)
1475 struct watchpoint
*watchpoint
= target
->watchpoints
;
1477 /* set any pending watchpoints */
1478 while (watchpoint
) {
1479 if (!watchpoint
->set
)
1480 cortex_m_set_watchpoint(target
, watchpoint
);
1481 watchpoint
= watchpoint
->next
;
1485 static int cortex_m_load_core_reg_u32(struct target
*target
,
1486 uint32_t num
, uint32_t *value
)
1490 /* NOTE: we "know" here that the register identifiers used
1491 * in the v7m header match the Cortex-M3 Debug Core Register
1492 * Selector values for R0..R15, xPSR, MSP, and PSP.
1496 /* read a normal core register */
1497 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1499 if (retval
!= ERROR_OK
) {
1500 LOG_ERROR("JTAG failure %i", retval
);
1501 return ERROR_JTAG_DEVICE_ERROR
;
1503 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1507 /* Floating-point Status and Registers */
1508 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1509 if (retval
!= ERROR_OK
)
1511 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1512 if (retval
!= ERROR_OK
)
1514 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1517 case ARMV7M_S0
... ARMV7M_S31
:
1518 /* Floating-point Status and Registers */
1519 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1520 if (retval
!= ERROR_OK
)
1522 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1523 if (retval
!= ERROR_OK
)
1525 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1526 (int)(num
- ARMV7M_S0
), *value
);
1529 case ARMV7M_PRIMASK
:
1530 case ARMV7M_BASEPRI
:
1531 case ARMV7M_FAULTMASK
:
1532 case ARMV7M_CONTROL
:
1533 /* Cortex-M3 packages these four registers as bitfields
1534 * in one Debug Core register. So say r0 and r2 docs;
1535 * it was removed from r1 docs, but still works.
1537 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1540 case ARMV7M_PRIMASK
:
1541 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1544 case ARMV7M_BASEPRI
:
1545 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1548 case ARMV7M_FAULTMASK
:
1549 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1552 case ARMV7M_CONTROL
:
1553 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1557 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1561 return ERROR_COMMAND_SYNTAX_ERROR
;
1567 static int cortex_m_store_core_reg_u32(struct target
*target
,
1568 uint32_t num
, uint32_t value
)
1572 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1574 /* NOTE: we "know" here that the register identifiers used
1575 * in the v7m header match the Cortex-M3 Debug Core Register
1576 * Selector values for R0..R15, xPSR, MSP, and PSP.
1580 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1581 if (retval
!= ERROR_OK
) {
1584 LOG_ERROR("JTAG failure");
1585 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1586 r
->dirty
= r
->valid
;
1587 return ERROR_JTAG_DEVICE_ERROR
;
1589 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1593 /* Floating-point Status and Registers */
1594 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1595 if (retval
!= ERROR_OK
)
1597 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1598 if (retval
!= ERROR_OK
)
1600 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1603 case ARMV7M_S0
... ARMV7M_S31
:
1604 /* Floating-point Status and Registers */
1605 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1606 if (retval
!= ERROR_OK
)
1608 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1609 if (retval
!= ERROR_OK
)
1611 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1612 (int)(num
- ARMV7M_S0
), value
);
1615 case ARMV7M_PRIMASK
:
1616 case ARMV7M_BASEPRI
:
1617 case ARMV7M_FAULTMASK
:
1618 case ARMV7M_CONTROL
:
1619 /* Cortex-M3 packages these four registers as bitfields
1620 * in one Debug Core register. So say r0 and r2 docs;
1621 * it was removed from r1 docs, but still works.
1623 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1626 case ARMV7M_PRIMASK
:
1627 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1630 case ARMV7M_BASEPRI
:
1631 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1634 case ARMV7M_FAULTMASK
:
1635 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1638 case ARMV7M_CONTROL
:
1639 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1643 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1645 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1649 return ERROR_COMMAND_SYNTAX_ERROR
;
1655 static int cortex_m_read_memory(struct target
*target
, uint32_t address
,
1656 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1658 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1659 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1661 if (armv7m
->arm
.is_armv6m
) {
1662 /* armv6m does not handle unaligned memory access */
1663 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1664 return ERROR_TARGET_UNALIGNED_ACCESS
;
1667 return mem_ap_read(swjdp
, buffer
, size
, count
, address
, true);
1670 static int cortex_m_write_memory(struct target
*target
, uint32_t address
,
1671 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1673 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1674 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1676 if (armv7m
->arm
.is_armv6m
) {
1677 /* armv6m does not handle unaligned memory access */
1678 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1679 return ERROR_TARGET_UNALIGNED_ACCESS
;
1682 return mem_ap_write(swjdp
, buffer
, size
, count
, address
, true);
1685 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1686 struct target
*target
)
1688 armv7m_build_reg_cache(target
);
1692 void cortex_m_deinit_target(struct target
*target
)
1694 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1696 free(cortex_m
->fp_comparator_list
);
1697 cortex_m_dwt_free(target
);
1701 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1702 * on r/w if the core is not running, and clear on resume or reset ... or
1703 * at least, in a post_restore_context() method.
1706 struct dwt_reg_state
{
1707 struct target
*target
;
1709 uint8_t value
[4]; /* scratch/cache */
1712 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1714 struct dwt_reg_state
*state
= reg
->arch_info
;
1717 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1718 if (retval
!= ERROR_OK
)
1721 buf_set_u32(state
->value
, 0, 32, tmp
);
1725 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1727 struct dwt_reg_state
*state
= reg
->arch_info
;
1729 return target_write_u32(state
->target
, state
->addr
,
1730 buf_get_u32(buf
, 0, reg
->size
));
1739 static struct dwt_reg dwt_base_regs
[] = {
1740 { DWT_CTRL
, "dwt_ctrl", 32, },
1741 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1742 * increments while the core is asleep.
1744 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1745 /* plus some 8 bit counters, useful for profiling with TPIU */
1748 static struct dwt_reg dwt_comp
[] = {
1749 #define DWT_COMPARATOR(i) \
1750 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1751 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1752 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1757 #undef DWT_COMPARATOR
1760 static const struct reg_arch_type dwt_reg_type
= {
1761 .get
= cortex_m_dwt_get_reg
,
1762 .set
= cortex_m_dwt_set_reg
,
1765 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1767 struct dwt_reg_state
*state
;
1769 state
= calloc(1, sizeof *state
);
1772 state
->addr
= d
->addr
;
1777 r
->value
= state
->value
;
1778 r
->arch_info
= state
;
1779 r
->type
= &dwt_reg_type
;
1782 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1785 struct reg_cache
*cache
;
1786 struct cortex_m_dwt_comparator
*comparator
;
1789 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1791 LOG_DEBUG("no DWT");
1795 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1796 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1797 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1798 sizeof(struct cortex_m_dwt_comparator
));
1799 if (!cm
->dwt_comparator_list
) {
1801 cm
->dwt_num_comp
= 0;
1802 LOG_ERROR("out of mem");
1806 cache
= calloc(1, sizeof *cache
);
1809 free(cm
->dwt_comparator_list
);
1812 cache
->name
= "Cortex-M DWT registers";
1813 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1814 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1815 if (!cache
->reg_list
) {
1820 for (reg
= 0; reg
< 2; reg
++)
1821 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1822 dwt_base_regs
+ reg
);
1824 comparator
= cm
->dwt_comparator_list
;
1825 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1828 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1829 for (j
= 0; j
< 3; j
++, reg
++)
1830 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1831 dwt_comp
+ 3 * i
+ j
);
1833 /* make sure we clear any watchpoints enabled on the target */
1834 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1837 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1838 cm
->dwt_cache
= cache
;
1840 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1841 dwtcr
, cm
->dwt_num_comp
,
1842 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1844 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1845 * implement single-address data value watchpoints ... so we
1846 * won't need to check it later, when asked to set one up.
1850 static void cortex_m_dwt_free(struct target
*target
)
1852 struct cortex_m_common
*cm
= target_to_cm(target
);
1853 struct reg_cache
*cache
= cm
->dwt_cache
;
1855 free(cm
->dwt_comparator_list
);
1856 cm
->dwt_comparator_list
= NULL
;
1859 register_unlink_cache(&target
->reg_cache
, cache
);
1861 if (cache
->reg_list
) {
1862 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
1863 free(cache
->reg_list
[i
].arch_info
);
1864 free(cache
->reg_list
);
1868 cm
->dwt_cache
= NULL
;
1871 #define MVFR0 0xe000ef40
1872 #define MVFR1 0xe000ef44
1874 #define MVFR0_DEFAULT_M4 0x10110021
1875 #define MVFR1_DEFAULT_M4 0x11000011
1877 int cortex_m_examine(struct target
*target
)
1880 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1882 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1883 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1884 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1886 /* stlink shares the examine handler but does not support
1888 if (!armv7m
->stlink
) {
1889 retval
= ahbap_debugport_init(swjdp
);
1890 if (retval
!= ERROR_OK
)
1894 if (!target_was_examined(target
)) {
1895 target_set_examined(target
);
1897 /* Read from Device Identification Registers */
1898 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1899 if (retval
!= ERROR_OK
)
1903 i
= (cpuid
>> 4) & 0xf;
1905 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1906 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1907 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1909 /* test for floating point feature on cortex-m4 */
1911 target_read_u32(target
, MVFR0
, &mvfr0
);
1912 target_read_u32(target
, MVFR1
, &mvfr1
);
1914 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1915 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1916 armv7m
->fp_feature
= FPv4_SP
;
1918 } else if (i
== 0) {
1919 /* Cortex-M0 does not support unaligned memory access */
1920 armv7m
->arm
.is_armv6m
= true;
1923 if (armv7m
->fp_feature
!= FPv4_SP
&&
1924 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
1925 /* free unavailable FPU registers */
1927 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
1928 idx
< armv7m
->arm
.core_cache
->num_regs
;
1930 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
1931 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
1934 if (i
== 4 || i
== 3) {
1935 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1936 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1939 /* Configure trace modules */
1940 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
1941 if (retval
!= ERROR_OK
)
1944 if (armv7m
->trace_config
.config_type
!= DISABLED
) {
1945 armv7m_trace_tpiu_config(target
);
1946 armv7m_trace_itm_config(target
);
1949 /* NOTE: FPB and DWT are both optional. */
1952 target_read_u32(target
, FP_CTRL
, &fpcr
);
1953 cortex_m
->auto_bp_type
= 1;
1954 /* bits [14:12] and [7:4] */
1955 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
1956 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1957 cortex_m
->fp_code_available
= cortex_m
->fp_num_code
;
1958 free(cortex_m
->fp_comparator_list
);
1959 cortex_m
->fp_comparator_list
= calloc(
1960 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
1961 sizeof(struct cortex_m_fp_comparator
));
1962 cortex_m
->fpb_enabled
= fpcr
& 1;
1963 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
1964 cortex_m
->fp_comparator_list
[i
].type
=
1965 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1966 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1968 /* make sure we clear any breakpoints enabled on the target */
1969 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
1971 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1973 cortex_m
->fp_num_code
,
1974 cortex_m
->fp_num_lit
);
1977 cortex_m_dwt_free(target
);
1978 cortex_m_dwt_setup(cortex_m
, target
);
1980 /* These hardware breakpoints only work for code in flash! */
1981 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1982 target_name(target
),
1983 cortex_m
->fp_num_code
,
1984 cortex_m
->dwt_num_comp
);
1990 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
1992 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1993 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1998 retval
= mem_ap_read(swjdp
, buf
, 2, 1, DCB_DCRDR
, false);
1999 if (retval
!= ERROR_OK
)
2002 dcrdr
= target_buffer_get_u16(target
, buf
);
2003 *ctrl
= (uint8_t)dcrdr
;
2004 *value
= (uint8_t)(dcrdr
>> 8);
2006 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2008 /* write ack back to software dcc register
2009 * signify we have read data */
2010 if (dcrdr
& (1 << 0)) {
2011 target_buffer_set_u16(target
, buf
, 0);
2012 retval
= mem_ap_write(swjdp
, buf
, 2, 1, DCB_DCRDR
, false);
2013 if (retval
!= ERROR_OK
)
2020 static int cortex_m_target_request_data(struct target
*target
,
2021 uint32_t size
, uint8_t *buffer
)
2027 for (i
= 0; i
< (size
* 4); i
++) {
2028 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2029 if (retval
!= ERROR_OK
)
2037 static int cortex_m_handle_target_request(void *priv
)
2039 struct target
*target
= priv
;
2040 if (!target_was_examined(target
))
2043 if (!target
->dbg_msg_enabled
)
2046 if (target
->state
== TARGET_RUNNING
) {
2051 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2052 if (retval
!= ERROR_OK
)
2055 /* check if we have data */
2056 if (ctrl
& (1 << 0)) {
2059 /* we assume target is quick enough */
2061 for (int i
= 1; i
<= 3; i
++) {
2062 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2063 if (retval
!= ERROR_OK
)
2065 request
|= ((uint32_t)data
<< (i
* 8));
2067 target_request(target
, request
);
2074 static int cortex_m_init_arch_info(struct target
*target
,
2075 struct cortex_m_common
*cortex_m
, struct jtag_tap
*tap
)
2078 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2080 armv7m_init_arch_info(target
, armv7m
);
2082 /* prepare JTAG information for the new target */
2083 cortex_m
->jtag_info
.tap
= tap
;
2084 cortex_m
->jtag_info
.scann_size
= 4;
2086 /* default reset mode is to use srst if fitted
2087 * if not it will use CORTEX_M3_RESET_VECTRESET */
2088 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2090 armv7m
->arm
.dap
= &armv7m
->dap
;
2092 /* Leave (only) generic DAP stuff for debugport_init(); */
2093 armv7m
->dap
.jtag_info
= &cortex_m
->jtag_info
;
2094 armv7m
->dap
.memaccess_tck
= 8;
2096 /* Cortex-M3/M4 has 4096 bytes autoincrement range
2097 * but set a safe default to 1024 to support Cortex-M0
2098 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
2099 armv7m
->dap
.tar_autoincr_block
= (1 << 10);
2101 /* register arch-specific functions */
2102 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2104 armv7m
->post_debug_entry
= NULL
;
2106 armv7m
->pre_restore_context
= NULL
;
2108 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2109 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2111 target_register_timer_callback(cortex_m_handle_target_request
, 1, 1, target
);
2113 retval
= arm_jtag_setup_connection(&cortex_m
->jtag_info
);
2114 if (retval
!= ERROR_OK
)
2120 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2122 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2124 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2125 cortex_m_init_arch_info(target
, cortex_m
, target
->tap
);
2130 /*--------------------------------------------------------------------------*/
2132 static int cortex_m_verify_pointer(struct command_context
*cmd_ctx
,
2133 struct cortex_m_common
*cm
)
2135 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2136 command_print(cmd_ctx
, "target is not a Cortex-M");
2137 return ERROR_TARGET_INVALID
;
2143 * Only stuff below this line should need to verify that its target
2144 * is a Cortex-M3. Everything else should have indirected through the
2145 * cortexm3_target structure, which is only used with CM3 targets.
2148 static const struct {
2152 { "hard_err", VC_HARDERR
, },
2153 { "int_err", VC_INTERR
, },
2154 { "bus_err", VC_BUSERR
, },
2155 { "state_err", VC_STATERR
, },
2156 { "chk_err", VC_CHKERR
, },
2157 { "nocp_err", VC_NOCPERR
, },
2158 { "mm_err", VC_MMERR
, },
2159 { "reset", VC_CORERESET
, },
2162 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2164 struct target
*target
= get_current_target(CMD_CTX
);
2165 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2166 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2167 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
2171 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2172 if (retval
!= ERROR_OK
)
2175 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2176 if (retval
!= ERROR_OK
)
2182 if (CMD_ARGC
== 1) {
2183 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2184 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2185 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2186 | VC_MMERR
| VC_CORERESET
;
2188 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2191 while (CMD_ARGC
-- > 0) {
2193 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2194 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2196 catch |= vec_ids
[i
].mask
;
2199 if (i
== ARRAY_SIZE(vec_ids
)) {
2200 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2201 return ERROR_COMMAND_SYNTAX_ERROR
;
2205 /* For now, armv7m->demcr only stores vector catch flags. */
2206 armv7m
->demcr
= catch;
2211 /* write, but don't assume it stuck (why not??) */
2212 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2213 if (retval
!= ERROR_OK
)
2215 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2216 if (retval
!= ERROR_OK
)
2219 /* FIXME be sure to clear DEMCR on clean server shutdown.
2220 * Otherwise the vector catch hardware could fire when there's
2221 * no debugger hooked up, causing much confusion...
2225 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2226 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2227 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2233 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2235 struct target
*target
= get_current_target(CMD_CTX
);
2236 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2239 static const Jim_Nvp nvp_maskisr_modes
[] = {
2240 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2241 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2242 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2243 { .name
= NULL
, .value
= -1 },
2248 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2249 if (retval
!= ERROR_OK
)
2252 if (target
->state
!= TARGET_HALTED
) {
2253 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2258 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2259 if (n
->name
== NULL
)
2260 return ERROR_COMMAND_SYNTAX_ERROR
;
2261 cortex_m
->isrmasking_mode
= n
->value
;
2264 if (cortex_m
->isrmasking_mode
== CORTEX_M_ISRMASK_ON
)
2265 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2267 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2270 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2271 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2276 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2278 struct target
*target
= get_current_target(CMD_CTX
);
2279 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2283 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2284 if (retval
!= ERROR_OK
)
2288 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2289 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2290 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2291 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2294 switch (cortex_m
->soft_reset_config
) {
2295 case CORTEX_M_RESET_SYSRESETREQ
:
2296 reset_config
= "sysresetreq";
2299 case CORTEX_M_RESET_VECTRESET
:
2300 reset_config
= "vectreset";
2304 reset_config
= "unknown";
2308 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2313 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2316 .handler
= handle_cortex_m_mask_interrupts_command
,
2317 .mode
= COMMAND_EXEC
,
2318 .help
= "mask cortex_m interrupts",
2319 .usage
= "['auto'|'on'|'off']",
2322 .name
= "vector_catch",
2323 .handler
= handle_cortex_m_vector_catch_command
,
2324 .mode
= COMMAND_EXEC
,
2325 .help
= "configure hardware vectors to trigger debug entry",
2326 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2329 .name
= "reset_config",
2330 .handler
= handle_cortex_m_reset_config_command
,
2331 .mode
= COMMAND_ANY
,
2332 .help
= "configure software reset handling",
2333 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2335 COMMAND_REGISTRATION_DONE
2337 static const struct command_registration cortex_m_command_handlers
[] = {
2339 .chain
= armv7m_command_handlers
,
2342 .chain
= armv7m_trace_command_handlers
,
2346 .mode
= COMMAND_EXEC
,
2347 .help
= "Cortex-M command group",
2349 .chain
= cortex_m_exec_command_handlers
,
2351 COMMAND_REGISTRATION_DONE
2354 struct target_type cortexm_target
= {
2356 .deprecated_name
= "cortex_m3",
2358 .poll
= cortex_m_poll
,
2359 .arch_state
= armv7m_arch_state
,
2361 .target_request_data
= cortex_m_target_request_data
,
2363 .halt
= cortex_m_halt
,
2364 .resume
= cortex_m_resume
,
2365 .step
= cortex_m_step
,
2367 .assert_reset
= cortex_m_assert_reset
,
2368 .deassert_reset
= cortex_m_deassert_reset
,
2369 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2371 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2373 .read_memory
= cortex_m_read_memory
,
2374 .write_memory
= cortex_m_write_memory
,
2375 .checksum_memory
= armv7m_checksum_memory
,
2376 .blank_check_memory
= armv7m_blank_check_memory
,
2378 .run_algorithm
= armv7m_run_algorithm
,
2379 .start_algorithm
= armv7m_start_algorithm
,
2380 .wait_algorithm
= armv7m_wait_algorithm
,
2382 .add_breakpoint
= cortex_m_add_breakpoint
,
2383 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2384 .add_watchpoint
= cortex_m_add_watchpoint
,
2385 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2387 .commands
= cortex_m_command_handlers
,
2388 .target_create
= cortex_m_target_create
,
2389 .init_target
= cortex_m_init_target
,
2390 .examine
= cortex_m_examine
,
2391 .deinit_target
= cortex_m_deinit_target
,
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