src/target/cortex_m.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  ***************************************************************************/
  13
  14 #ifndef OPENOCD_TARGET_CORTEX_M_H
  15 #define OPENOCD_TARGET_CORTEX_M_H
  16
  17 #include "armv7m.h"
  18 #include "helper/bits.h"
  19
  20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
  21
  22 #define SYSTEM_CONTROL_BASE 0x400FE000
  23
  24 #define ITM_TER0        0xE0000E00
  25 #define ITM_TPR         0xE0000E40
  26 #define ITM_TCR         0xE0000E80
  27 #define ITM_TCR_ITMENA_BIT      BIT(0)
  28 #define ITM_TCR_BUSY_BIT        BIT(23)
  29 #define ITM_LAR         0xE0000FB0
  30 #define ITM_LAR_KEY     0xC5ACCE55
  31
  32 #define CPUID           0xE000ED00
  33
  34 #define ARM_CPUID_PARTNO_POS    4
  35 #define ARM_CPUID_PARTNO_MASK   (0xFFF << ARM_CPUID_PARTNO_POS)
  36
  37 enum cortex_m_partno {
  38         CORTEX_M_PARTNO_INVALID,
  39         STAR_MC1_PARTNO    = 0x132,
  40         CORTEX_M0_PARTNO   = 0xC20,
  41         CORTEX_M1_PARTNO   = 0xC21,
  42         CORTEX_M3_PARTNO   = 0xC23,
  43         CORTEX_M4_PARTNO   = 0xC24,
  44         CORTEX_M7_PARTNO   = 0xC27,
  45         CORTEX_M0P_PARTNO  = 0xC60,
  46         CORTEX_M23_PARTNO  = 0xD20,
  47         CORTEX_M33_PARTNO  = 0xD21,
  48         CORTEX_M35P_PARTNO = 0xD31,
  49         CORTEX_M55_PARTNO  = 0xD22,
  50 };
  51
  52 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
  53 #define CORTEX_M_F_HAS_FPV4               BIT(0)
  54 #define CORTEX_M_F_HAS_FPV5               BIT(1)
  55 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K  BIT(2)
  56
  57 struct cortex_m_part_info {
  58         enum cortex_m_partno partno;
  59         const char *name;
  60         enum arm_arch arch;
  61         uint32_t flags;
  62 };
  63
  64 /* Debug Control Block */
  65 #define DCB_DHCSR       0xE000EDF0
  66 #define DCB_DCRSR       0xE000EDF4
  67 #define DCB_DCRDR       0xE000EDF8
  68 #define DCB_DEMCR       0xE000EDFC
  69 #define DCB_DSCSR       0xE000EE08
  70
  71 #define DAUTHSTATUS     0xE000EFB8
  72 #define DAUTHSTATUS_SID_MASK    0x00000030
  73
  74 #define DCRSR_WNR       BIT(16)
  75
  76 #define DWT_CTRL        0xE0001000
  77 #define DWT_CYCCNT      0xE0001004
  78 #define DWT_PCSR        0xE000101C
  79 #define DWT_COMP0       0xE0001020
  80 #define DWT_MASK0       0xE0001024
  81 #define DWT_FUNCTION0   0xE0001028
  82 #define DWT_DEVARCH             0xE0001FBC
  83
  84 #define DWT_DEVARCH_ARMV8M      0x101A02
  85
  86 #define FP_CTRL         0xE0002000
  87 #define FP_REMAP        0xE0002004
  88 #define FP_COMP0        0xE0002008
  89 #define FP_COMP1        0xE000200C
  90 #define FP_COMP2        0xE0002010
  91 #define FP_COMP3        0xE0002014
  92 #define FP_COMP4        0xE0002018
  93 #define FP_COMP5        0xE000201C
  94 #define FP_COMP6        0xE0002020
  95 #define FP_COMP7        0xE0002024
  96
  97 #define FPU_CPACR       0xE000ED88
  98 #define FPU_FPCCR       0xE000EF34
  99 #define FPU_FPCAR       0xE000EF38
 100 #define FPU_FPDSCR      0xE000EF3C
 101
 102 #define TPIU_SSPSR      0xE0040000
 103 #define TPIU_CSPSR      0xE0040004
 104 #define TPIU_ACPR       0xE0040010
 105 #define TPIU_SPPR       0xE00400F0
 106 #define TPIU_FFSR       0xE0040300
 107 #define TPIU_FFCR       0xE0040304
 108 #define TPIU_FSCR       0xE0040308
 109
 110 /* Maximum SWO prescaler value. */
 111 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
 112
 113 /* DCB_DHCSR bit and field definitions */
 114 #define DBGKEY          (0xA05Ful << 16)
 115 #define C_DEBUGEN       BIT(0)
 116 #define C_HALT          BIT(1)
 117 #define C_STEP          BIT(2)
 118 #define C_MASKINTS      BIT(3)
 119 #define S_REGRDY        BIT(16)
 120 #define S_HALT          BIT(17)
 121 #define S_SLEEP         BIT(18)
 122 #define S_LOCKUP        BIT(19)
 123 #define S_RETIRE_ST     BIT(24)
 124 #define S_RESET_ST      BIT(25)
 125
 126 /* DCB_DEMCR bit and field definitions */
 127 #define TRCENA                  BIT(24)
 128 #define VC_HARDERR              BIT(10)
 129 #define VC_INTERR               BIT(9)
 130 #define VC_BUSERR               BIT(8)
 131 #define VC_STATERR              BIT(7)
 132 #define VC_CHKERR               BIT(6)
 133 #define VC_NOCPERR              BIT(5)
 134 #define VC_MMERR                BIT(4)
 135 #define VC_CORERESET    BIT(0)
 136
 137 /* DCB_DSCSR bit and field definitions */
 138 #define DSCSR_CDS               BIT(16)
 139
 140 /* NVIC registers */
 141 #define NVIC_ICTR               0xE000E004
 142 #define NVIC_ISE0               0xE000E100
 143 #define NVIC_ICSR               0xE000ED04
 144 #define NVIC_AIRCR              0xE000ED0C
 145 #define NVIC_SHCSR              0xE000ED24
 146 #define NVIC_CFSR               0xE000ED28
 147 #define NVIC_MMFSRB             0xE000ED28
 148 #define NVIC_BFSRB              0xE000ED29
 149 #define NVIC_USFSRH             0xE000ED2A
 150 #define NVIC_HFSR               0xE000ED2C
 151 #define NVIC_DFSR               0xE000ED30
 152 #define NVIC_MMFAR              0xE000ED34
 153 #define NVIC_BFAR               0xE000ED38
 154 #define NVIC_SFSR               0xE000EDE4
 155 #define NVIC_SFAR               0xE000EDE8
 156
 157 /* NVIC_AIRCR bits */
 158 #define AIRCR_VECTKEY           (0x5FAul << 16)
 159 #define AIRCR_SYSRESETREQ       BIT(2)
 160 #define AIRCR_VECTCLRACTIVE     BIT(1)
 161 #define AIRCR_VECTRESET         BIT(0)
 162 /* NVIC_SHCSR bits */
 163 #define SHCSR_BUSFAULTENA       BIT(17)
 164 /* NVIC_DFSR bits */
 165 #define DFSR_HALTED                     1
 166 #define DFSR_BKPT                       2
 167 #define DFSR_DWTTRAP            4
 168 #define DFSR_VCATCH                     8
 169 #define DFSR_EXTERNAL           16
 170
 171 #define FPCR_CODE 0
 172 #define FPCR_LITERAL 1
 173 #define FPCR_REPLACE_REMAP  (0ul << 30)
 174 #define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
 175 #define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
 176 #define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 177
 178 struct cortex_m_fp_comparator {
 179         bool used;
 180         int type;
 181         uint32_t fpcr_value;
 182         uint32_t fpcr_address;
 183 };
 184
 185 struct cortex_m_dwt_comparator {
 186         bool used;
 187         uint32_t comp;
 188         uint32_t mask;
 189         uint32_t function;
 190         uint32_t dwt_comparator_address;
 191 };
 192
 193 enum cortex_m_soft_reset_config {
 194         CORTEX_M_RESET_SYSRESETREQ,
 195         CORTEX_M_RESET_VECTRESET,
 196 };
 197
 198 enum cortex_m_isrmasking_mode {
 199         CORTEX_M_ISRMASK_AUTO,
 200         CORTEX_M_ISRMASK_OFF,
 201         CORTEX_M_ISRMASK_ON,
 202         CORTEX_M_ISRMASK_STEPONLY,
 203 };
 204
 205 struct cortex_m_common {
 206         unsigned int common_magic;
 207
 208         struct armv7m_common armv7m;
 209
 210         /* Context information */
 211         uint32_t dcb_dhcsr;
 212         uint32_t dcb_dhcsr_cumulated_sticky;
 213         /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
 214         bool dcb_dhcsr_sticky_is_recent;
 215         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 216         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 217
 218         /* Flash Patch and Breakpoint (FPB) */
 219         unsigned int fp_num_lit;
 220         unsigned int fp_num_code;
 221         int fp_rev;
 222         bool fpb_enabled;
 223         struct cortex_m_fp_comparator *fp_comparator_list;
 224
 225         /* Data Watchpoint and Trace (DWT) */
 226         unsigned int dwt_num_comp;
 227         unsigned int dwt_comp_available;
 228         uint32_t dwt_devarch;
 229         struct cortex_m_dwt_comparator *dwt_comparator_list;
 230         struct reg_cache *dwt_cache;
 231
 232         enum cortex_m_soft_reset_config soft_reset_config;
 233         bool vectreset_supported;
 234         enum cortex_m_isrmasking_mode isrmasking_mode;
 235
 236         const struct cortex_m_part_info *core_info;
 237
 238         bool slow_register_read;        /* A register has not been ready, poll S_REGRDY */
 239
 240         uint64_t apsel;
 241
 242         /* Whether this target has the erratum that makes C_MASKINTS not apply to
 243          * already pending interrupts */
 244         bool maskints_erratum;
 245 };
 246
 247 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
 248 {
 249         return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
 250 }
 251
 252 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
 253 {
 254         if (!is_cortex_m_or_hla(cortex_m))
 255                 return false;
 256
 257         return !cortex_m->armv7m.is_hla_target;
 258 }
 259
 260 /**
 261  * @returns the pointer to the target specific struct
 262  * without matching a magic number.
 263  * Use in target specific service routines, where the correct
 264  * type of arch_info is certain.
 265  */
 266 static inline struct cortex_m_common *
 267 target_to_cm(struct target *target)
 268 {
 269         return container_of(target->arch_info,
 270                         struct cortex_m_common, armv7m.arm);
 271 }
 272
 273 /**
 274  * @returns the pointer to the target specific struct
 275  * or NULL if the magic number does not match.
 276  * Use in a flash driver or any place where mismatch of the arch_info
 277  * type can happen.
 278  */
 279 static inline struct cortex_m_common *
 280 target_to_cortex_m_safe(struct target *target)
 281 {
 282         /* Check the parent types first to prevent peeking memory too far
 283          * from arch_info pointer */
 284         if (!target_to_armv7m_safe(target))
 285                 return NULL;
 286
 287         struct cortex_m_common *cortex_m = target_to_cm(target);
 288         if (!is_cortex_m_or_hla(cortex_m))
 289                 return NULL;
 290
 291         return cortex_m;
 292 }
 293
 294 /**
 295  * @returns cached value of Cortex-M part number
 296  * or CORTEX_M_PARTNO_INVALID if the magic number does not match
 297  * or core_info is not initialised.
 298  */
 299 static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
 300 {
 301         struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
 302         if (!cortex_m)
 303                 return CORTEX_M_PARTNO_INVALID;
 304
 305         if (!cortex_m->core_info)
 306                 return CORTEX_M_PARTNO_INVALID;
 307
 308         return cortex_m->core_info->partno;
 309 }
 310
 311 int cortex_m_examine(struct target *target);
 312 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
 313 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 314 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 315 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 316 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 317 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 318 void cortex_m_enable_breakpoints(struct target *target);
 319 void cortex_m_enable_watchpoints(struct target *target);
 320 void cortex_m_deinit_target(struct target *target);
 321 int cortex_m_profiling(struct target *target, uint32_t *samples,
 322         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 323
 324 #endif /* OPENOCD_TARGET_CORTEX_M_H */