1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
57 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
58 static void cortex_m3_enable_watchpoints(struct target
*target
);
59 static int cortex_m3_store_core_reg_u32(struct target
*target
,
60 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
63 uint32_t *value
, int regnum
)
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
71 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
73 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
74 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
75 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
77 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
78 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
79 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
81 retval
= dap_run(swjdp
);
83 /* restore DCB_DCRDR - this needs to be in a seperate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
91 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
92 uint32_t value
, int regnum
)
97 /* because the DCB_DCRDR is used for the emulated dcc channel
98 * we have to save/restore the DCB_DCRDR when used */
100 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
102 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
103 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
104 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
106 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
107 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
108 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
110 retval
= dap_run(swjdp
);
112 /* restore DCB_DCRDR - this needs to be in a seperate
113 * transaction otherwise the emulated DCC channel breaks */
114 if (retval
== ERROR_OK
)
115 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
120 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
121 uint32_t mask_on
, uint32_t mask_off
)
123 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
124 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
126 /* mask off status bits */
127 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
128 /* create new register mask */
129 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
131 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
134 static int cortex_m3_clear_halt(struct target
*target
)
136 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
137 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
139 /* clear step if any */
140 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
142 /* Read Debug Fault Status Register */
143 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
152 static int cortex_m3_single_step_core(struct target
*target
)
154 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
155 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
158 /* backup dhcsr reg */
159 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
161 /* Mask interrupts before clearing halt, if done already. This avoids
162 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
163 * HALT can put the core into an unknown state.
165 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
166 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
167 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
168 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
169 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
172 /* restore dhcsr reg */
173 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
174 cortex_m3_clear_halt(target
);
179 static int cortex_m3_endreset_event(struct target
*target
)
184 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
185 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
186 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
187 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
188 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
190 /* REVISIT The four debug monitor bits are currently ignored... */
191 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
192 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
194 /* this register is used for emulated dcc channel */
195 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
197 /* Enable debug requests */
198 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
199 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
200 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
202 /* clear any interrupt masking */
203 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
205 /* Enable features controlled by ITM and DWT blocks, and catch only
206 * the vectors we were told to pay attention to.
208 * Target firmware is responsible for all fault handling policy
209 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
210 * or manual updates to the NVIC SHCSR and CCR registers.
212 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
214 /* Paranoia: evidently some (early?) chips don't preserve all the
215 * debug state (including FBP, DWT, etc) across reset...
219 target_write_u32(target
, FP_CTRL
, 3);
220 cortex_m3
->fpb_enabled
= 1;
222 /* Restore FPB registers */
223 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
225 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
228 /* Restore DWT registers */
229 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
231 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
233 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
235 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
236 dwt_list
[i
].function
);
238 retval
= dap_run(swjdp
);
239 if (retval
!= ERROR_OK
)
242 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
244 /* make sure we have latest dhcsr flags */
245 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
250 static int cortex_m3_examine_debug_reason(struct target
*target
)
252 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
254 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
255 /* only check the debug reason if we don't know it already */
257 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
258 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
260 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
262 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
263 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
264 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
266 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
267 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
268 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
269 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
270 else /* EXTERNAL, HALTED */
271 target
->debug_reason
= DBG_REASON_UNDEFINED
;
277 static int cortex_m3_examine_exception_reason(struct target
*target
)
279 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
280 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
281 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
284 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
285 switch (armv7m
->exception_number
)
289 case 3: /* Hard Fault */
290 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
291 if (except_sr
& 0x40000000)
293 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
296 case 4: /* Memory Management */
297 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
298 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
300 case 5: /* Bus Fault */
301 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
302 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
304 case 6: /* Usage Fault */
305 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
307 case 11: /* SVCall */
309 case 12: /* Debug Monitor */
310 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
312 case 14: /* PendSV */
314 case 15: /* SysTick */
320 retval
= dap_run(swjdp
);
321 if (retval
== ERROR_OK
)
322 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
323 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
324 armv7m_exception_string(armv7m
->exception_number
),
325 shcsr
, except_sr
, cfsr
, except_ar
);
329 /* PSP is used in some thread modes */
330 static const int armv7m_psp_reg_map
[17] = {
331 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
332 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
333 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
334 ARMV7M_R12
, ARMV7M_PSP
, ARMV7M_R14
, ARMV7M_PC
,
338 /* MSP is used in handler and some thread modes */
339 static const int armv7m_msp_reg_map
[17] = {
340 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
341 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
342 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
343 ARMV7M_R12
, ARMV7M_MSP
, ARMV7M_R14
, ARMV7M_PC
,
347 static int cortex_m3_debug_entry(struct target
*target
)
352 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
353 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
354 struct arm
*arm
= &armv7m
->arm
;
355 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
360 cortex_m3_clear_halt(target
);
361 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
363 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
366 /* Examine target state and mode */
367 /* First load register acessible through core debug port*/
368 int num_regs
= armv7m
->core_cache
->num_regs
;
370 for (i
= 0; i
< num_regs
; i
++)
372 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
373 armv7m
->read_core_reg(target
, i
);
376 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
377 xPSR
= buf_get_u32(r
->value
, 0, 32);
379 #ifdef ARMV7_GDB_HACKS
380 /* FIXME this breaks on scan chains with more than one Cortex-M3.
381 * Instead, each CM3 should have its own dummy value...
383 /* copy real xpsr reg for gdb, setting thumb bit */
384 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
385 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
386 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
387 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
390 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
394 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
397 /* Are we in an exception handler */
400 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
401 armv7m
->exception_number
= (xPSR
& 0x1FF);
403 arm
->core_mode
= ARM_MODE_HANDLER
;
404 arm
->map
= armv7m_msp_reg_map
;
408 unsigned control
= buf_get_u32(armv7m
->core_cache
409 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
411 /* is this thread privileged? */
412 armv7m
->core_mode
= control
& 1;
413 arm
->core_mode
= armv7m
->core_mode
414 ? ARM_MODE_USER_THREAD
417 /* which stack is it using? */
419 arm
->map
= armv7m_psp_reg_map
;
421 arm
->map
= armv7m_msp_reg_map
;
423 armv7m
->exception_number
= 0;
426 if (armv7m
->exception_number
)
428 cortex_m3_examine_exception_reason(target
);
431 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
432 armv7m_mode_strings
[armv7m
->core_mode
],
433 *(uint32_t*)(arm
->pc
->value
),
434 target_state_name(target
));
436 if (armv7m
->post_debug_entry
)
437 armv7m
->post_debug_entry(target
);
442 static int cortex_m3_poll(struct target
*target
)
445 enum target_state prev_target_state
= target
->state
;
446 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
447 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
449 /* Read from Debug Halting Control and Status Register */
450 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
451 if (retval
!= ERROR_OK
)
453 target
->state
= TARGET_UNKNOWN
;
457 /* Recover from lockup. See ARMv7-M architecture spec,
458 * section B1.5.15 "Unrecoverable exception cases".
460 * REVISIT Is there a better way to report and handle this?
462 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
463 LOG_WARNING("%s -- clearing lockup after double fault",
464 target_name(target
));
465 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
466 target
->debug_reason
= DBG_REASON_DBGRQ
;
468 /* refresh status bits */
469 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
472 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
474 /* check if still in reset */
475 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
477 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
479 target
->state
= TARGET_RESET
;
484 if (target
->state
== TARGET_RESET
)
486 /* Cannot switch context while running so endreset is
487 * called with target->state == TARGET_RESET
489 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
490 cortex_m3
->dcb_dhcsr
);
491 cortex_m3_endreset_event(target
);
492 target
->state
= TARGET_RUNNING
;
493 prev_target_state
= TARGET_RUNNING
;
496 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
498 target
->state
= TARGET_HALTED
;
500 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
502 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
505 if (arm_semihosting(target
, &retval
) != 0)
508 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
510 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
513 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
516 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
520 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
521 * How best to model low power modes?
524 if (target
->state
== TARGET_UNKNOWN
)
526 /* check if processor is retiring instructions */
527 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
529 target
->state
= TARGET_RUNNING
;
537 static int cortex_m3_halt(struct target
*target
)
539 LOG_DEBUG("target->state: %s",
540 target_state_name(target
));
542 if (target
->state
== TARGET_HALTED
)
544 LOG_DEBUG("target was already halted");
548 if (target
->state
== TARGET_UNKNOWN
)
550 LOG_WARNING("target was in unknown state when halt was requested");
553 if (target
->state
== TARGET_RESET
)
555 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
557 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
558 return ERROR_TARGET_FAILURE
;
562 /* we came here in a reset_halt or reset_init sequence
563 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
565 target
->debug_reason
= DBG_REASON_DBGRQ
;
571 /* Write to Debug Halting Control and Status Register */
572 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
574 target
->debug_reason
= DBG_REASON_DBGRQ
;
579 static int cortex_m3_soft_reset_halt(struct target
*target
)
581 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
582 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
583 uint32_t dcb_dhcsr
= 0;
584 int retval
, timeout
= 0;
586 /* Enter debug state on reset; restore DEMCR in endreset_event() */
587 mem_ap_write_u32(swjdp
, DCB_DEMCR
,
588 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
590 /* Request a core-only reset */
591 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
592 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
593 target
->state
= TARGET_RESET
;
595 /* registers are now invalid */
596 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
598 while (timeout
< 100)
600 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
601 if (retval
== ERROR_OK
)
603 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
604 &cortex_m3
->nvic_dfsr
);
605 if ((dcb_dhcsr
& S_HALT
)
606 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
608 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
610 (unsigned) dcb_dhcsr
,
611 (unsigned) cortex_m3
->nvic_dfsr
);
612 cortex_m3_poll(target
);
613 /* FIXME restore user's vector catch config */
617 LOG_DEBUG("waiting for system reset-halt, "
618 "DHCSR 0x%08x, %d ms",
619 (unsigned) dcb_dhcsr
, timeout
);
628 static void cortex_m3_enable_breakpoints(struct target
*target
)
630 struct breakpoint
*breakpoint
= target
->breakpoints
;
632 /* set any pending breakpoints */
635 if (!breakpoint
->set
)
636 cortex_m3_set_breakpoint(target
, breakpoint
);
637 breakpoint
= breakpoint
->next
;
641 static int cortex_m3_resume(struct target
*target
, int current
,
642 uint32_t address
, int handle_breakpoints
, int debug_execution
)
644 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
645 struct breakpoint
*breakpoint
= NULL
;
649 if (target
->state
!= TARGET_HALTED
)
651 LOG_WARNING("target not halted");
652 return ERROR_TARGET_NOT_HALTED
;
655 if (!debug_execution
)
657 target_free_all_working_areas(target
);
658 cortex_m3_enable_breakpoints(target
);
659 cortex_m3_enable_watchpoints(target
);
664 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
666 /* Disable interrupts */
667 /* We disable interrupts in the PRIMASK register instead of
668 * masking with C_MASKINTS. This is probably the same issue
669 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
670 * in parallel with disabled interrupts can cause local faults
673 * REVISIT this clearly breaks non-debug execution, since the
674 * PRIMASK register state isn't saved/restored... workaround
675 * by never resuming app code after debug execution.
677 buf_set_u32(r
->value
, 0, 1, 1);
681 /* Make sure we are in Thumb mode */
682 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
683 buf_set_u32(r
->value
, 24, 1, 1);
688 /* current = 1: continue on current pc, otherwise continue at <address> */
692 buf_set_u32(r
->value
, 0, 32, address
);
697 /* if we halted last time due to a bkpt instruction
698 * then we have to manually step over it, otherwise
699 * the core will break again */
701 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
704 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
707 resume_pc
= buf_get_u32(r
->value
, 0, 32);
709 armv7m_restore_context(target
);
711 /* the front-end may request us not to handle breakpoints */
712 if (handle_breakpoints
)
714 /* Single step past breakpoint at current address */
715 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
717 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
719 breakpoint
->unique_id
);
720 cortex_m3_unset_breakpoint(target
, breakpoint
);
721 cortex_m3_single_step_core(target
);
722 cortex_m3_set_breakpoint(target
, breakpoint
);
727 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
729 target
->debug_reason
= DBG_REASON_NOTHALTED
;
731 /* registers are now invalid */
732 register_cache_invalidate(armv7m
->core_cache
);
734 if (!debug_execution
)
736 target
->state
= TARGET_RUNNING
;
737 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
738 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
742 target
->state
= TARGET_DEBUG_RUNNING
;
743 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
744 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
750 /* int irqstepcount = 0; */
751 static int cortex_m3_step(struct target
*target
, int current
,
752 uint32_t address
, int handle_breakpoints
)
754 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
755 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
756 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
757 struct breakpoint
*breakpoint
= NULL
;
758 struct reg
*pc
= armv7m
->arm
.pc
;
759 bool bkpt_inst_found
= false;
761 if (target
->state
!= TARGET_HALTED
)
763 LOG_WARNING("target not halted");
764 return ERROR_TARGET_NOT_HALTED
;
767 /* current = 1: continue on current pc, otherwise continue at <address> */
769 buf_set_u32(pc
->value
, 0, 32, address
);
771 /* the front-end may request us not to handle breakpoints */
772 if (handle_breakpoints
) {
773 breakpoint
= breakpoint_find(target
,
774 buf_get_u32(pc
->value
, 0, 32));
776 cortex_m3_unset_breakpoint(target
, breakpoint
);
779 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
781 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
783 armv7m_restore_context(target
);
785 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
787 /* if no bkpt instruction is found at pc then we can perform
788 * a normal step, otherwise we have to manually step over the bkpt
789 * instruction - as such simulate a step */
790 if (bkpt_inst_found
== false)
792 /* set step and clear halt */
793 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
796 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
798 /* registers are now invalid */
799 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
802 cortex_m3_set_breakpoint(target
, breakpoint
);
804 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
805 " nvic_icsr = 0x%" PRIx32
,
806 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
808 cortex_m3_debug_entry(target
);
809 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
811 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
812 " nvic_icsr = 0x%" PRIx32
,
813 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
818 static int cortex_m3_assert_reset(struct target
*target
)
820 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
821 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
824 LOG_DEBUG("target->state: %s",
825 target_state_name(target
));
827 enum reset_types jtag_reset_config
= jtag_get_reset_config();
830 * We can reset Cortex-M3 targets using just the NVIC without
831 * requiring SRST, getting a SoC reset (or a core-only reset)
832 * instead of a system reset.
834 if (!(jtag_reset_config
& RESET_HAS_SRST
))
837 /* Enable debug requests */
838 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
839 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
840 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
842 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
844 if (!target
->reset_halt
)
846 /* Set/Clear C_MASKINTS in a separate operation */
847 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
848 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
849 DBGKEY
| C_DEBUGEN
| C_HALT
);
851 /* clear any debug flags before resuming */
852 cortex_m3_clear_halt(target
);
854 /* clear C_HALT in dhcsr reg */
855 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
859 /* Halt in debug on reset; endreset_event() restores DEMCR.
861 * REVISIT catching BUSERR presumably helps to defend against
862 * bad vector table entries. Should this include MMERR or
865 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
866 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
870 * When nRST is asserted on most Stellaris devices, it clears some of
871 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
872 * and OpenOCD depends on those TRMs. So we won't use SRST on those
873 * chips. (Only power-on reset should affect debug state, beyond a
874 * few specified bits; not the chip's nRST input, wired to SRST.)
876 * REVISIT current errata specs don't seem to cover this issue.
877 * Do we have more details than this email?
878 * https://lists.berlios.de/pipermail
879 * /openocd-development/2008-August/003065.html
881 if (strcmp(target
->variant
, "lm3s") == 0)
883 /* Check for silicon revisions with the issue. */
886 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
888 switch ((did0
>> 16) & 0xff)
891 /* all Sandstorm suffer issue */
897 /* Fury and DustDevil rev A have
898 * this nRST problem. It should
899 * be fixed in rev B silicon.
901 if (((did0
>> 8) & 0xff) == 0)
905 /* Tempest should be fine. */
913 /* default to asserting srst */
914 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
916 jtag_add_reset(1, 1);
920 jtag_add_reset(0, 1);
925 /* Use a standard Cortex-M3 software reset mechanism.
926 * SYSRESETREQ will reset SoC peripherals outside the
927 * core, like watchdog timers, if the SoC wires it up
928 * correctly. Else VECRESET can reset just the core.
930 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
931 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
932 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
935 /* I do not know why this is necessary, but it
936 * fixes strange effects (step/resume cause NMI
937 * after reset) on LM3S6918 -- Michael Schwingen
940 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
944 target
->state
= TARGET_RESET
;
945 jtag_add_sleep(50000);
947 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
949 if (target
->reset_halt
)
952 if ((retval
= target_halt(target
)) != ERROR_OK
)
959 static int cortex_m3_deassert_reset(struct target
*target
)
961 LOG_DEBUG("target->state: %s",
962 target_state_name(target
));
964 /* deassert reset lines */
965 jtag_add_reset(0, 0);
971 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
976 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
977 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
981 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
985 if (cortex_m3
->auto_bp_type
)
987 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
990 if (breakpoint
->type
== BKPT_HARD
)
992 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
994 if (fp_num
>= cortex_m3
->fp_num_code
)
996 LOG_ERROR("Can not find free FPB Comparator!");
999 breakpoint
->set
= fp_num
+ 1;
1000 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1001 comparator_list
[fp_num
].used
= 1;
1002 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1003 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1004 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
1005 if (!cortex_m3
->fpb_enabled
)
1007 LOG_DEBUG("FPB wasn't enabled, do it now");
1008 target_write_u32(target
, FP_CTRL
, 3);
1011 else if (breakpoint
->type
== BKPT_SOFT
)
1015 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1016 * semihosting; don't use that. Otherwise the BKPT
1017 * parameter is arbitrary.
1019 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1020 retval
= target_read_memory(target
,
1021 breakpoint
->address
& 0xFFFFFFFE,
1022 breakpoint
->length
, 1,
1023 breakpoint
->orig_instr
);
1024 if (retval
!= ERROR_OK
)
1026 retval
= target_write_memory(target
,
1027 breakpoint
->address
& 0xFFFFFFFE,
1028 breakpoint
->length
, 1,
1030 if (retval
!= ERROR_OK
)
1032 breakpoint
->set
= true;
1035 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1036 breakpoint
->unique_id
,
1037 (int)(breakpoint
->type
),
1038 breakpoint
->address
,
1046 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1049 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1050 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
1052 if (!breakpoint
->set
)
1054 LOG_WARNING("breakpoint not set");
1058 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1059 breakpoint
->unique_id
,
1060 (int)(breakpoint
->type
),
1061 breakpoint
->address
,
1065 if (breakpoint
->type
== BKPT_HARD
)
1067 int fp_num
= breakpoint
->set
- 1;
1068 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
1070 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1073 comparator_list
[fp_num
].used
= 0;
1074 comparator_list
[fp_num
].fpcr_value
= 0;
1075 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1079 /* restore original instruction (kept in target endianness) */
1080 if (breakpoint
->length
== 4)
1082 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1089 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1095 breakpoint
->set
= false;
1101 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1103 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1105 if (cortex_m3
->auto_bp_type
)
1107 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1108 #ifdef ARMV7_GDB_HACKS
1109 if (breakpoint
->length
!= 2) {
1110 /* XXX Hack: Replace all breakpoints with length != 2 with
1111 * a hardware breakpoint. */
1112 breakpoint
->type
= BKPT_HARD
;
1113 breakpoint
->length
= 2;
1118 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
1120 LOG_INFO("flash patch comparator requested outside code memory region");
1121 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1124 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
1126 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1127 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1130 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1132 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1133 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1136 if ((breakpoint
->length
!= 2))
1138 LOG_INFO("only breakpoints of two bytes length supported");
1139 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1142 if (breakpoint
->type
== BKPT_HARD
)
1143 cortex_m3
->fp_code_available
--;
1144 cortex_m3_set_breakpoint(target
, breakpoint
);
1150 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1152 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1154 /* REVISIT why check? FBP can be updated with core running ... */
1155 if (target
->state
!= TARGET_HALTED
)
1157 LOG_WARNING("target not halted");
1158 return ERROR_TARGET_NOT_HALTED
;
1161 if (cortex_m3
->auto_bp_type
)
1163 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1166 if (breakpoint
->set
)
1168 cortex_m3_unset_breakpoint(target
, breakpoint
);
1171 if (breakpoint
->type
== BKPT_HARD
)
1172 cortex_m3
->fp_code_available
++;
1178 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1181 uint32_t mask
, temp
;
1182 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1184 /* watchpoint params were validated earlier */
1186 temp
= watchpoint
->length
;
1193 /* REVISIT Don't fully trust these "not used" records ... users
1194 * may set up breakpoints by hand, e.g. dual-address data value
1195 * watchpoint using comparator #1; comparator #0 matching cycle
1196 * count; send data trace info through ITM and TPIU; etc
1198 struct cortex_m3_dwt_comparator
*comparator
;
1200 for (comparator
= cortex_m3
->dwt_comparator_list
;
1201 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1202 comparator
++, dwt_num
++)
1204 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1206 LOG_ERROR("Can not find free DWT Comparator");
1209 comparator
->used
= 1;
1210 watchpoint
->set
= dwt_num
+ 1;
1212 comparator
->comp
= watchpoint
->address
;
1213 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1216 comparator
->mask
= mask
;
1217 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1220 switch (watchpoint
->rw
) {
1222 comparator
->function
= 5;
1225 comparator
->function
= 6;
1228 comparator
->function
= 7;
1231 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1232 comparator
->function
);
1234 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1235 watchpoint
->unique_id
, dwt_num
,
1236 (unsigned) comparator
->comp
,
1237 (unsigned) comparator
->mask
,
1238 (unsigned) comparator
->function
);
1243 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1245 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1246 struct cortex_m3_dwt_comparator
*comparator
;
1249 if (!watchpoint
->set
)
1251 LOG_WARNING("watchpoint (wpid: %d) not set",
1252 watchpoint
->unique_id
);
1256 dwt_num
= watchpoint
->set
- 1;
1258 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1259 watchpoint
->unique_id
, dwt_num
,
1260 (unsigned) watchpoint
->address
);
1262 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1264 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1268 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1269 comparator
->used
= 0;
1270 comparator
->function
= 0;
1271 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1272 comparator
->function
);
1274 watchpoint
->set
= false;
1280 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1282 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1284 if (cortex_m3
->dwt_comp_available
< 1)
1286 LOG_DEBUG("no comparators?");
1287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1290 /* hardware doesn't support data value masking */
1291 if (watchpoint
->mask
!= ~(uint32_t)0) {
1292 LOG_DEBUG("watchpoint value masks not supported");
1293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1296 /* hardware allows address masks of up to 32K */
1299 for (mask
= 0; mask
< 16; mask
++) {
1300 if ((1u << mask
) == watchpoint
->length
)
1304 LOG_DEBUG("unsupported watchpoint length");
1305 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1307 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1308 LOG_DEBUG("watchpoint address is unaligned");
1309 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1312 /* Caller doesn't seem to be able to describe watching for data
1313 * values of zero; that flags "no value".
1315 * REVISIT This DWT may well be able to watch for specific data
1316 * values. Requires comparator #1 to set DATAVMATCH and match
1317 * the data, and another comparator (DATAVADDR0) matching addr.
1319 if (watchpoint
->value
) {
1320 LOG_DEBUG("data value watchpoint not YET supported");
1321 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1324 cortex_m3
->dwt_comp_available
--;
1325 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1331 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1333 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1335 /* REVISIT why check? DWT can be updated with core running ... */
1336 if (target
->state
!= TARGET_HALTED
)
1338 LOG_WARNING("target not halted");
1339 return ERROR_TARGET_NOT_HALTED
;
1342 if (watchpoint
->set
)
1344 cortex_m3_unset_watchpoint(target
, watchpoint
);
1347 cortex_m3
->dwt_comp_available
++;
1348 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1353 static void cortex_m3_enable_watchpoints(struct target
*target
)
1355 struct watchpoint
*watchpoint
= target
->watchpoints
;
1357 /* set any pending watchpoints */
1360 if (!watchpoint
->set
)
1361 cortex_m3_set_watchpoint(target
, watchpoint
);
1362 watchpoint
= watchpoint
->next
;
1366 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1367 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1370 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1371 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1373 /* NOTE: we "know" here that the register identifiers used
1374 * in the v7m header match the Cortex-M3 Debug Core Register
1375 * Selector values for R0..R15, xPSR, MSP, and PSP.
1379 /* read a normal core register */
1380 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1382 if (retval
!= ERROR_OK
)
1384 LOG_ERROR("JTAG failure %i",retval
);
1385 return ERROR_JTAG_DEVICE_ERROR
;
1387 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1390 case ARMV7M_PRIMASK
:
1391 case ARMV7M_BASEPRI
:
1392 case ARMV7M_FAULTMASK
:
1393 case ARMV7M_CONTROL
:
1394 /* Cortex-M3 packages these four registers as bitfields
1395 * in one Debug Core register. So say r0 and r2 docs;
1396 * it was removed from r1 docs, but still works.
1398 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1402 case ARMV7M_PRIMASK
:
1403 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1406 case ARMV7M_BASEPRI
:
1407 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1410 case ARMV7M_FAULTMASK
:
1411 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1414 case ARMV7M_CONTROL
:
1415 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1419 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1423 return ERROR_INVALID_ARGUMENTS
;
1429 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1430 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1434 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1435 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1437 #ifdef ARMV7_GDB_HACKS
1438 /* If the LR register is being modified, make sure it will put us
1439 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1440 * hack to deal with the fact that gdb will sometimes "forge"
1441 * return addresses, and doesn't set the LSB correctly (i.e., when
1442 * printing expressions containing function calls, it sets LR = 0.)
1443 * Valid exception return codes have bit 0 set too.
1445 if (num
== ARMV7M_R14
)
1449 /* NOTE: we "know" here that the register identifiers used
1450 * in the v7m header match the Cortex-M3 Debug Core Register
1451 * Selector values for R0..R15, xPSR, MSP, and PSP.
1455 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1456 if (retval
!= ERROR_OK
)
1460 LOG_ERROR("JTAG failure %i", retval
);
1461 r
= armv7m
->core_cache
->reg_list
+ num
;
1462 r
->dirty
= r
->valid
;
1463 return ERROR_JTAG_DEVICE_ERROR
;
1465 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1468 case ARMV7M_PRIMASK
:
1469 case ARMV7M_BASEPRI
:
1470 case ARMV7M_FAULTMASK
:
1471 case ARMV7M_CONTROL
:
1472 /* Cortex-M3 packages these four registers as bitfields
1473 * in one Debug Core register. So say r0 and r2 docs;
1474 * it was removed from r1 docs, but still works.
1476 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1480 case ARMV7M_PRIMASK
:
1481 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1484 case ARMV7M_BASEPRI
:
1485 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1488 case ARMV7M_FAULTMASK
:
1489 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1492 case ARMV7M_CONTROL
:
1493 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1497 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1499 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1503 return ERROR_INVALID_ARGUMENTS
;
1509 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1510 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1512 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1513 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1514 int retval
= ERROR_INVALID_ARGUMENTS
;
1516 /* cortex_m3 handles unaligned memory access */
1517 if (count
&& buffer
) {
1520 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1523 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1526 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1534 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1535 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1537 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1538 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1539 int retval
= ERROR_INVALID_ARGUMENTS
;
1541 if (count
&& buffer
) {
1544 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1547 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1550 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1558 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1559 uint32_t count
, uint8_t *buffer
)
1561 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1564 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1565 struct target
*target
)
1567 armv7m_build_reg_cache(target
);
1571 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1572 * on r/w if the core is not running, and clear on resume or reset ... or
1573 * at least, in a post_restore_context() method.
1576 struct dwt_reg_state
{
1577 struct target
*target
;
1579 uint32_t value
; /* scratch/cache */
1582 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1584 struct dwt_reg_state
*state
= reg
->arch_info
;
1586 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1589 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1591 struct dwt_reg_state
*state
= reg
->arch_info
;
1593 return target_write_u32(state
->target
, state
->addr
,
1594 buf_get_u32(buf
, 0, reg
->size
));
1603 static struct dwt_reg dwt_base_regs
[] = {
1604 { DWT_CTRL
, "dwt_ctrl", 32, },
1605 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1606 * increments while the core is asleep.
1608 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1609 /* plus some 8 bit counters, useful for profiling with TPIU */
1612 static struct dwt_reg dwt_comp
[] = {
1613 #define DWT_COMPARATOR(i) \
1614 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1615 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1616 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1621 #undef DWT_COMPARATOR
1624 static const struct reg_arch_type dwt_reg_type
= {
1625 .get
= cortex_m3_dwt_get_reg
,
1626 .set
= cortex_m3_dwt_set_reg
,
1630 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1632 struct dwt_reg_state
*state
;
1634 state
= calloc(1, sizeof *state
);
1637 state
->addr
= d
->addr
;
1642 r
->value
= &state
->value
;
1643 r
->arch_info
= state
;
1644 r
->type
= &dwt_reg_type
;
1648 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1651 struct reg_cache
*cache
;
1652 struct cortex_m3_dwt_comparator
*comparator
;
1655 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1657 LOG_DEBUG("no DWT");
1661 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1662 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1663 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1664 sizeof(struct cortex_m3_dwt_comparator
));
1665 if (!cm3
->dwt_comparator_list
) {
1667 cm3
->dwt_num_comp
= 0;
1668 LOG_ERROR("out of mem");
1672 cache
= calloc(1, sizeof *cache
);
1675 free(cm3
->dwt_comparator_list
);
1678 cache
->name
= "cortex-m3 dwt registers";
1679 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1680 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1681 if (!cache
->reg_list
) {
1686 for (reg
= 0; reg
< 2; reg
++)
1687 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1688 dwt_base_regs
+ reg
);
1690 comparator
= cm3
->dwt_comparator_list
;
1691 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1694 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1695 for (j
= 0; j
< 3; j
++, reg
++)
1696 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1697 dwt_comp
+ 3 * i
+ j
);
1700 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1701 cm3
->dwt_cache
= cache
;
1703 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1704 dwtcr
, cm3
->dwt_num_comp
,
1705 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1707 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1708 * implement single-address data value watchpoints ... so we
1709 * won't need to check it later, when asked to set one up.
1713 static int cortex_m3_examine(struct target
*target
)
1716 uint32_t cpuid
, fpcr
;
1718 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1719 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1721 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1724 if (!target_was_examined(target
))
1726 target_set_examined(target
);
1728 /* Read from Device Identification Registers */
1729 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1730 if (retval
!= ERROR_OK
)
1733 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1734 LOG_DEBUG("Cortex-M3 r%" PRId8
"p%" PRId8
" processor detected",
1735 (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1736 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1738 /* NOTE: FPB and DWT are both optional. */
1741 target_read_u32(target
, FP_CTRL
, &fpcr
);
1742 cortex_m3
->auto_bp_type
= 1;
1743 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1744 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1745 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1746 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1747 cortex_m3
->fpb_enabled
= fpcr
& 1;
1748 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1750 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1751 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1753 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1756 cortex_m3_dwt_setup(cortex_m3
, target
);
1758 /* These hardware breakpoints only work for code in flash! */
1759 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1760 target_name(target
),
1761 cortex_m3
->fp_num_code
,
1762 cortex_m3
->dwt_num_comp
);
1768 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1772 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1773 *ctrl
= (uint8_t)dcrdr
;
1774 *value
= (uint8_t)(dcrdr
>> 8);
1776 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1778 /* write ack back to software dcc register
1779 * signify we have read data */
1780 if (dcrdr
& (1 << 0))
1783 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1789 static int cortex_m3_target_request_data(struct target
*target
,
1790 uint32_t size
, uint8_t *buffer
)
1792 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1793 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1798 for (i
= 0; i
< (size
* 4); i
++)
1800 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1807 static int cortex_m3_handle_target_request(void *priv
)
1809 struct target
*target
= priv
;
1810 if (!target_was_examined(target
))
1812 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1813 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1815 if (!target
->dbg_msg_enabled
)
1818 if (target
->state
== TARGET_RUNNING
)
1823 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1825 /* check if we have data */
1826 if (ctrl
& (1 << 0))
1830 /* we assume target is quick enough */
1832 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1833 request
|= (data
<< 8);
1834 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1835 request
|= (data
<< 16);
1836 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1837 request
|= (data
<< 24);
1838 target_request(target
, request
);
1845 static int cortex_m3_init_arch_info(struct target
*target
,
1846 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1849 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1851 armv7m_init_arch_info(target
, armv7m
);
1853 /* prepare JTAG information for the new target */
1854 cortex_m3
->jtag_info
.tap
= tap
;
1855 cortex_m3
->jtag_info
.scann_size
= 4;
1857 /* Leave (only) generic DAP stuff for debugport_init(); */
1858 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1859 armv7m
->swjdp_info
.memaccess_tck
= 8;
1860 /* Cortex-M3 has 4096 bytes autoincrement range */
1861 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12);
1863 /* register arch-specific functions */
1864 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1866 armv7m
->post_debug_entry
= NULL
;
1868 armv7m
->pre_restore_context
= NULL
;
1869 armv7m
->post_restore_context
= NULL
;
1871 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1872 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1874 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1876 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1884 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1886 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1888 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1889 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1894 /*--------------------------------------------------------------------------*/
1896 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1897 struct cortex_m3_common
*cm3
)
1899 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1900 command_print(cmd_ctx
, "target is not a Cortex-M3");
1901 return ERROR_TARGET_INVALID
;
1907 * Only stuff below this line should need to verify that its target
1908 * is a Cortex-M3. Everything else should have indirected through the
1909 * cortexm3_target structure, which is only used with CM3 targets.
1912 static const struct {
1916 { "hard_err", VC_HARDERR
, },
1917 { "int_err", VC_INTERR
, },
1918 { "bus_err", VC_BUSERR
, },
1919 { "state_err", VC_STATERR
, },
1920 { "chk_err", VC_CHKERR
, },
1921 { "nocp_err", VC_NOCPERR
, },
1922 { "mm_err", VC_MMERR
, },
1923 { "reset", VC_CORERESET
, },
1926 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1928 struct target
*target
= get_current_target(CMD_CTX
);
1929 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1930 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1931 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1935 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1936 if (retval
!= ERROR_OK
)
1939 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1944 if (CMD_ARGC
== 1) {
1945 if (strcmp(CMD_ARGV
[0], "all") == 0) {
1946 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1947 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1948 | VC_MMERR
| VC_CORERESET
;
1950 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
1954 while (CMD_ARGC
-- > 0) {
1956 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1957 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
1959 catch |= vec_ids
[i
].mask
;
1962 if (i
== ARRAY_SIZE(vec_ids
)) {
1963 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
1964 return ERROR_INVALID_ARGUMENTS
;
1968 /* For now, armv7m->demcr only stores vector catch flags. */
1969 armv7m
->demcr
= catch;
1974 /* write, but don't assume it stuck (why not??) */
1975 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1976 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1978 /* FIXME be sure to clear DEMCR on clean server shutdown.
1979 * Otherwise the vector catch hardware could fire when there's
1980 * no debugger hooked up, causing much confusion...
1984 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1986 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
1987 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1993 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1995 struct target
*target
= get_current_target(CMD_CTX
);
1996 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1999 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2000 if (retval
!= ERROR_OK
)
2003 if (target
->state
!= TARGET_HALTED
)
2005 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2012 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], enable
);
2013 uint32_t mask_on
= C_HALT
| (enable
? C_MASKINTS
: 0);
2014 uint32_t mask_off
= enable
? 0 : C_MASKINTS
;
2015 cortex_m3_write_debug_halt_mask(target
, mask_on
, mask_off
);
2018 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s",
2019 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
2024 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2027 .handler
= handle_cortex_m3_mask_interrupts_command
,
2028 .mode
= COMMAND_EXEC
,
2029 .help
= "mask cortex_m3 interrupts",
2030 .usage
= "['on'|'off']",
2033 .name
= "vector_catch",
2034 .handler
= handle_cortex_m3_vector_catch_command
,
2035 .mode
= COMMAND_EXEC
,
2036 .help
= "configure hardware vectors to trigger debug entry",
2037 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2039 COMMAND_REGISTRATION_DONE
2041 static const struct command_registration cortex_m3_command_handlers
[] = {
2043 .chain
= armv7m_command_handlers
,
2046 .name
= "cortex_m3",
2047 .mode
= COMMAND_EXEC
,
2048 .help
= "Cortex-M3 command group",
2049 .chain
= cortex_m3_exec_command_handlers
,
2051 COMMAND_REGISTRATION_DONE
2054 struct target_type cortexm3_target
=
2056 .name
= "cortex_m3",
2058 .poll
= cortex_m3_poll
,
2059 .arch_state
= armv7m_arch_state
,
2061 .target_request_data
= cortex_m3_target_request_data
,
2063 .halt
= cortex_m3_halt
,
2064 .resume
= cortex_m3_resume
,
2065 .step
= cortex_m3_step
,
2067 .assert_reset
= cortex_m3_assert_reset
,
2068 .deassert_reset
= cortex_m3_deassert_reset
,
2069 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2071 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2073 .read_memory
= cortex_m3_read_memory
,
2074 .write_memory
= cortex_m3_write_memory
,
2075 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2076 .checksum_memory
= armv7m_checksum_memory
,
2077 .blank_check_memory
= armv7m_blank_check_memory
,
2079 .run_algorithm
= armv7m_run_algorithm
,
2081 .add_breakpoint
= cortex_m3_add_breakpoint
,
2082 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2083 .add_watchpoint
= cortex_m3_add_watchpoint
,
2084 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2086 .commands
= cortex_m3_command_handlers
,
2087 .target_create
= cortex_m3_target_create
,
2088 .init_target
= cortex_m3_init_target
,
2089 .examine
= cortex_m3_examine
,
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