1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
55 /* forward declarations */
56 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
57 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
58 static void cortex_m3_enable_watchpoints(struct target
*target
);
59 static int cortex_m3_store_core_reg_u32(struct target
*target
,
60 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
63 uint32_t *value
, int regnum
)
68 /* because the DCB_DCRDR is used for the emulated dcc channel
69 * we have to save/restore the DCB_DCRDR when used */
71 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
72 if (retval
!= ERROR_OK
)
75 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
76 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
77 if (retval
!= ERROR_OK
)
79 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
80 if (retval
!= ERROR_OK
)
83 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
84 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
85 if (retval
!= ERROR_OK
)
87 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
88 if (retval
!= ERROR_OK
)
91 retval
= dap_run(swjdp
);
92 if (retval
!= ERROR_OK
)
95 /* restore DCB_DCRDR - this needs to be in a seperate
96 * transaction otherwise the emulated DCC channel breaks */
97 if (retval
== ERROR_OK
)
98 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
103 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
104 uint32_t value
, int regnum
)
109 /* because the DCB_DCRDR is used for the emulated dcc channel
110 * we have to save/restore the DCB_DCRDR when used */
112 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
113 if (retval
!= ERROR_OK
)
116 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
117 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
118 if (retval
!= ERROR_OK
)
120 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
123 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
124 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
125 if (retval
!= ERROR_OK
)
127 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
130 retval
= dap_run(swjdp
);
132 /* restore DCB_DCRDR - this needs to be in a seperate
133 * transaction otherwise the emulated DCC channel breaks */
134 if (retval
== ERROR_OK
)
135 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
140 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
141 uint32_t mask_on
, uint32_t mask_off
)
143 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
144 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
146 /* mask off status bits */
147 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
148 /* create new register mask */
149 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
151 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
154 static int cortex_m3_clear_halt(struct target
*target
)
156 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
157 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
160 /* clear step if any */
161 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
163 /* Read Debug Fault Status Register */
164 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
165 if (retval
!= ERROR_OK
)
168 /* Clear Debug Fault Status */
169 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
170 if (retval
!= ERROR_OK
)
172 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
177 static int cortex_m3_single_step_core(struct target
*target
)
179 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
180 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
184 /* backup dhcsr reg */
185 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
187 /* Mask interrupts before clearing halt, if done already. This avoids
188 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
189 * HALT can put the core into an unknown state.
191 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
193 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
194 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
195 if (retval
!= ERROR_OK
)
198 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
199 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
200 if (retval
!= ERROR_OK
)
204 /* restore dhcsr reg */
205 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
206 cortex_m3_clear_halt(target
);
211 static int cortex_m3_endreset_event(struct target
*target
)
216 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
217 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
218 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
219 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
220 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
222 /* REVISIT The four debug monitor bits are currently ignored... */
223 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
224 if (retval
!= ERROR_OK
)
226 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
228 /* this register is used for emulated dcc channel */
229 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
230 if (retval
!= ERROR_OK
)
233 /* Enable debug requests */
234 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
235 if (retval
!= ERROR_OK
)
237 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
239 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
240 if (retval
!= ERROR_OK
)
244 /* clear any interrupt masking */
245 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
247 /* Enable features controlled by ITM and DWT blocks, and catch only
248 * the vectors we were told to pay attention to.
250 * Target firmware is responsible for all fault handling policy
251 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
252 * or manual updates to the NVIC SHCSR and CCR registers.
254 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
255 if (retval
!= ERROR_OK
)
258 /* Paranoia: evidently some (early?) chips don't preserve all the
259 * debug state (including FBP, DWT, etc) across reset...
263 retval
= target_write_u32(target
, FP_CTRL
, 3);
264 if (retval
!= ERROR_OK
)
267 cortex_m3
->fpb_enabled
= 1;
269 /* Restore FPB registers */
270 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
272 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
273 if (retval
!= ERROR_OK
)
277 /* Restore DWT registers */
278 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
280 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
282 if (retval
!= ERROR_OK
)
284 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
286 if (retval
!= ERROR_OK
)
288 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
289 dwt_list
[i
].function
);
290 if (retval
!= ERROR_OK
)
293 retval
= dap_run(swjdp
);
294 if (retval
!= ERROR_OK
)
297 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
299 /* make sure we have latest dhcsr flags */
300 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
305 static int cortex_m3_examine_debug_reason(struct target
*target
)
307 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
309 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
310 /* only check the debug reason if we don't know it already */
312 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
313 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
315 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
317 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
318 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
319 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
321 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
322 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
323 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
324 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
325 else /* EXTERNAL, HALTED */
326 target
->debug_reason
= DBG_REASON_UNDEFINED
;
332 static int cortex_m3_examine_exception_reason(struct target
*target
)
334 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
335 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
336 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
339 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
340 if (retval
!= ERROR_OK
)
342 switch (armv7m
->exception_number
)
346 case 3: /* Hard Fault */
347 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
348 if (retval
!= ERROR_OK
)
350 if (except_sr
& 0x40000000)
352 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
353 if (retval
!= ERROR_OK
)
357 case 4: /* Memory Management */
358 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
359 if (retval
!= ERROR_OK
)
361 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
362 if (retval
!= ERROR_OK
)
365 case 5: /* Bus Fault */
366 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
367 if (retval
!= ERROR_OK
)
369 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
370 if (retval
!= ERROR_OK
)
373 case 6: /* Usage Fault */
374 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
375 if (retval
!= ERROR_OK
)
378 case 11: /* SVCall */
380 case 12: /* Debug Monitor */
381 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
382 if (retval
!= ERROR_OK
)
385 case 14: /* PendSV */
387 case 15: /* SysTick */
393 retval
= dap_run(swjdp
);
394 if (retval
== ERROR_OK
)
395 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
396 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
397 armv7m_exception_string(armv7m
->exception_number
),
398 shcsr
, except_sr
, cfsr
, except_ar
);
402 /* PSP is used in some thread modes */
403 static const int armv7m_psp_reg_map
[17] = {
404 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
405 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
406 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
407 ARMV7M_R12
, ARMV7M_PSP
, ARMV7M_R14
, ARMV7M_PC
,
411 /* MSP is used in handler and some thread modes */
412 static const int armv7m_msp_reg_map
[17] = {
413 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
414 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
415 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
416 ARMV7M_R12
, ARMV7M_MSP
, ARMV7M_R14
, ARMV7M_PC
,
420 static int cortex_m3_debug_entry(struct target
*target
)
425 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
426 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
427 struct arm
*arm
= &armv7m
->arm
;
428 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
433 cortex_m3_clear_halt(target
);
434 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
435 if (retval
!= ERROR_OK
)
438 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
441 /* Examine target state and mode */
442 /* First load register acessible through core debug port*/
443 int num_regs
= armv7m
->core_cache
->num_regs
;
445 for (i
= 0; i
< num_regs
; i
++)
447 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
448 armv7m
->read_core_reg(target
, i
);
451 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
452 xPSR
= buf_get_u32(r
->value
, 0, 32);
454 #ifdef ARMV7_GDB_HACKS
455 /* FIXME this breaks on scan chains with more than one Cortex-M3.
456 * Instead, each CM3 should have its own dummy value...
458 /* copy real xpsr reg for gdb, setting thumb bit */
459 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
460 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
461 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
462 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
465 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
469 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
472 /* Are we in an exception handler */
475 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
476 armv7m
->exception_number
= (xPSR
& 0x1FF);
478 arm
->core_mode
= ARM_MODE_HANDLER
;
479 arm
->map
= armv7m_msp_reg_map
;
483 unsigned control
= buf_get_u32(armv7m
->core_cache
484 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
486 /* is this thread privileged? */
487 armv7m
->core_mode
= control
& 1;
488 arm
->core_mode
= armv7m
->core_mode
489 ? ARM_MODE_USER_THREAD
492 /* which stack is it using? */
494 arm
->map
= armv7m_psp_reg_map
;
496 arm
->map
= armv7m_msp_reg_map
;
498 armv7m
->exception_number
= 0;
501 if (armv7m
->exception_number
)
503 cortex_m3_examine_exception_reason(target
);
506 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
507 armv7m_mode_strings
[armv7m
->core_mode
],
508 *(uint32_t*)(arm
->pc
->value
),
509 target_state_name(target
));
511 if (armv7m
->post_debug_entry
)
513 retval
= armv7m
->post_debug_entry(target
);
514 if (retval
!= ERROR_OK
)
521 static int cortex_m3_poll(struct target
*target
)
523 int detected_failure
= ERROR_OK
;
524 int retval
= ERROR_OK
;
525 enum target_state prev_target_state
= target
->state
;
526 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
527 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
529 /* Read from Debug Halting Control and Status Register */
530 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
531 if (retval
!= ERROR_OK
)
533 target
->state
= TARGET_UNKNOWN
;
537 /* Recover from lockup. See ARMv7-M architecture spec,
538 * section B1.5.15 "Unrecoverable exception cases".
540 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
541 LOG_ERROR("%s -- clearing lockup after double fault",
542 target_name(target
));
543 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
544 target
->debug_reason
= DBG_REASON_DBGRQ
;
546 /* We have to execute the rest (the "finally" equivalent, but
547 * still throw this exception again).
549 detected_failure
= ERROR_FAIL
;
551 /* refresh status bits */
552 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
553 if (retval
!= ERROR_OK
)
557 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
559 /* check if still in reset */
560 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
561 if (retval
!= ERROR_OK
)
564 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
566 target
->state
= TARGET_RESET
;
571 if (target
->state
== TARGET_RESET
)
573 /* Cannot switch context while running so endreset is
574 * called with target->state == TARGET_RESET
576 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
577 cortex_m3
->dcb_dhcsr
);
578 cortex_m3_endreset_event(target
);
579 target
->state
= TARGET_RUNNING
;
580 prev_target_state
= TARGET_RUNNING
;
583 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
585 target
->state
= TARGET_HALTED
;
587 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
589 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
592 if (arm_semihosting(target
, &retval
) != 0)
595 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
597 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
600 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
603 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
607 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
608 * How best to model low power modes?
611 if (target
->state
== TARGET_UNKNOWN
)
613 /* check if processor is retiring instructions */
614 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
616 target
->state
= TARGET_RUNNING
;
621 /* Did we detect a failure condition that we cleared? */
622 if (detected_failure
!= ERROR_OK
)
623 retval
= detected_failure
;
627 static int cortex_m3_halt(struct target
*target
)
629 LOG_DEBUG("target->state: %s",
630 target_state_name(target
));
632 if (target
->state
== TARGET_HALTED
)
634 LOG_DEBUG("target was already halted");
638 if (target
->state
== TARGET_UNKNOWN
)
640 LOG_WARNING("target was in unknown state when halt was requested");
643 if (target
->state
== TARGET_RESET
)
645 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
647 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
648 return ERROR_TARGET_FAILURE
;
652 /* we came here in a reset_halt or reset_init sequence
653 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
655 target
->debug_reason
= DBG_REASON_DBGRQ
;
661 /* Write to Debug Halting Control and Status Register */
662 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
664 target
->debug_reason
= DBG_REASON_DBGRQ
;
669 static int cortex_m3_soft_reset_halt(struct target
*target
)
671 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
672 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
673 uint32_t dcb_dhcsr
= 0;
674 int retval
, timeout
= 0;
676 /* Enter debug state on reset; restore DEMCR in endreset_event() */
677 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
678 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
679 if (retval
!= ERROR_OK
)
682 /* Request a core-only reset */
683 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
684 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
685 if (retval
!= ERROR_OK
)
687 target
->state
= TARGET_RESET
;
689 /* registers are now invalid */
690 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
692 while (timeout
< 100)
694 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
695 if (retval
== ERROR_OK
)
697 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
698 &cortex_m3
->nvic_dfsr
);
699 if (retval
!= ERROR_OK
)
701 if ((dcb_dhcsr
& S_HALT
)
702 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
704 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
706 (unsigned) dcb_dhcsr
,
707 (unsigned) cortex_m3
->nvic_dfsr
);
708 cortex_m3_poll(target
);
709 /* FIXME restore user's vector catch config */
713 LOG_DEBUG("waiting for system reset-halt, "
714 "DHCSR 0x%08x, %d ms",
715 (unsigned) dcb_dhcsr
, timeout
);
724 static void cortex_m3_enable_breakpoints(struct target
*target
)
726 struct breakpoint
*breakpoint
= target
->breakpoints
;
728 /* set any pending breakpoints */
731 if (!breakpoint
->set
)
732 cortex_m3_set_breakpoint(target
, breakpoint
);
733 breakpoint
= breakpoint
->next
;
737 static int cortex_m3_resume(struct target
*target
, int current
,
738 uint32_t address
, int handle_breakpoints
, int debug_execution
)
740 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
741 struct breakpoint
*breakpoint
= NULL
;
745 if (target
->state
!= TARGET_HALTED
)
747 LOG_WARNING("target not halted");
748 return ERROR_TARGET_NOT_HALTED
;
751 if (!debug_execution
)
753 target_free_all_working_areas(target
);
754 cortex_m3_enable_breakpoints(target
);
755 cortex_m3_enable_watchpoints(target
);
760 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
762 /* Disable interrupts */
763 /* We disable interrupts in the PRIMASK register instead of
764 * masking with C_MASKINTS. This is probably the same issue
765 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
766 * in parallel with disabled interrupts can cause local faults
769 * REVISIT this clearly breaks non-debug execution, since the
770 * PRIMASK register state isn't saved/restored... workaround
771 * by never resuming app code after debug execution.
773 buf_set_u32(r
->value
, 0, 1, 1);
777 /* Make sure we are in Thumb mode */
778 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
779 buf_set_u32(r
->value
, 24, 1, 1);
784 /* current = 1: continue on current pc, otherwise continue at <address> */
788 buf_set_u32(r
->value
, 0, 32, address
);
793 /* if we halted last time due to a bkpt instruction
794 * then we have to manually step over it, otherwise
795 * the core will break again */
797 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
800 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
803 resume_pc
= buf_get_u32(r
->value
, 0, 32);
805 armv7m_restore_context(target
);
807 /* the front-end may request us not to handle breakpoints */
808 if (handle_breakpoints
)
810 /* Single step past breakpoint at current address */
811 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
813 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
815 breakpoint
->unique_id
);
816 cortex_m3_unset_breakpoint(target
, breakpoint
);
817 cortex_m3_single_step_core(target
);
818 cortex_m3_set_breakpoint(target
, breakpoint
);
823 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
825 target
->debug_reason
= DBG_REASON_NOTHALTED
;
827 /* registers are now invalid */
828 register_cache_invalidate(armv7m
->core_cache
);
830 if (!debug_execution
)
832 target
->state
= TARGET_RUNNING
;
833 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
834 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
838 target
->state
= TARGET_DEBUG_RUNNING
;
839 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
840 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
846 /* int irqstepcount = 0; */
847 static int cortex_m3_step(struct target
*target
, int current
,
848 uint32_t address
, int handle_breakpoints
)
850 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
851 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
852 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
853 struct breakpoint
*breakpoint
= NULL
;
854 struct reg
*pc
= armv7m
->arm
.pc
;
855 bool bkpt_inst_found
= false;
857 if (target
->state
!= TARGET_HALTED
)
859 LOG_WARNING("target not halted");
860 return ERROR_TARGET_NOT_HALTED
;
863 /* current = 1: continue on current pc, otherwise continue at <address> */
865 buf_set_u32(pc
->value
, 0, 32, address
);
867 /* the front-end may request us not to handle breakpoints */
868 if (handle_breakpoints
) {
869 breakpoint
= breakpoint_find(target
,
870 buf_get_u32(pc
->value
, 0, 32));
872 cortex_m3_unset_breakpoint(target
, breakpoint
);
875 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
877 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
879 armv7m_restore_context(target
);
881 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
883 /* if no bkpt instruction is found at pc then we can perform
884 * a normal step, otherwise we have to manually step over the bkpt
885 * instruction - as such simulate a step */
886 if (bkpt_inst_found
== false)
888 /* set step and clear halt */
889 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
893 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
894 if (retval
!= ERROR_OK
)
897 /* registers are now invalid */
898 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
901 cortex_m3_set_breakpoint(target
, breakpoint
);
903 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
904 " nvic_icsr = 0x%" PRIx32
,
905 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
907 retval
= cortex_m3_debug_entry(target
);
908 if (retval
!= ERROR_OK
)
910 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
912 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
913 " nvic_icsr = 0x%" PRIx32
,
914 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
919 static int cortex_m3_assert_reset(struct target
*target
)
921 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
922 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
923 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
925 LOG_DEBUG("target->state: %s",
926 target_state_name(target
));
928 enum reset_types jtag_reset_config
= jtag_get_reset_config();
931 * We can reset Cortex-M3 targets using just the NVIC without
932 * requiring SRST, getting a SoC reset (or a core-only reset)
933 * instead of a system reset.
935 if (!(jtag_reset_config
& RESET_HAS_SRST
) &&
936 (cortex_m3
->soft_reset_config
== CORTEX_M3_RESET_SRST
)) {
937 reset_config
= CORTEX_M3_RESET_VECTRESET
;
940 /* Enable debug requests */
942 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
943 if (retval
!= ERROR_OK
)
945 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
947 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
948 if (retval
!= ERROR_OK
)
952 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
953 if (retval
!= ERROR_OK
)
956 if (!target
->reset_halt
)
958 /* Set/Clear C_MASKINTS in a separate operation */
959 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
961 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
962 DBGKEY
| C_DEBUGEN
| C_HALT
);
963 if (retval
!= ERROR_OK
)
967 /* clear any debug flags before resuming */
968 cortex_m3_clear_halt(target
);
970 /* clear C_HALT in dhcsr reg */
971 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
975 /* Halt in debug on reset; endreset_event() restores DEMCR.
977 * REVISIT catching BUSERR presumably helps to defend against
978 * bad vector table entries. Should this include MMERR or
981 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
982 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
983 if (retval
!= ERROR_OK
)
987 if (reset_config
== CORTEX_M3_RESET_SRST
)
989 /* default to asserting srst */
990 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
992 jtag_add_reset(1, 1);
996 jtag_add_reset(0, 1);
1001 /* Use a standard Cortex-M3 software reset mechanism.
1002 * We default to using VECRESET as it is supported on all current cores.
1003 * This has the disadvantage of not resetting the peripherals, so a
1004 * reset-init event handler is needed to perform any peripheral resets.
1006 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1007 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1008 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1009 if (retval
!= ERROR_OK
)
1012 LOG_DEBUG("Using Cortex-M3 %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1013 ? "SYSRESETREQ" : "VECTRESET");
1015 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1016 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1017 "handler to reset any peripherals");
1021 /* I do not know why this is necessary, but it
1022 * fixes strange effects (step/resume cause NMI
1023 * after reset) on LM3S6918 -- Michael Schwingen
1026 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1027 if (retval
!= ERROR_OK
)
1032 target
->state
= TARGET_RESET
;
1033 jtag_add_sleep(50000);
1035 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1037 if (target
->reset_halt
)
1039 if ((retval
= target_halt(target
)) != ERROR_OK
)
1046 static int cortex_m3_deassert_reset(struct target
*target
)
1048 LOG_DEBUG("target->state: %s",
1049 target_state_name(target
));
1051 /* deassert reset lines */
1052 jtag_add_reset(0, 0);
1058 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1063 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1064 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1066 if (breakpoint
->set
)
1068 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1072 if (cortex_m3
->auto_bp_type
)
1074 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1077 if (breakpoint
->type
== BKPT_HARD
)
1079 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1081 if (fp_num
>= cortex_m3
->fp_num_code
)
1083 LOG_ERROR("Can not find free FPB Comparator!");
1086 breakpoint
->set
= fp_num
+ 1;
1087 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1088 comparator_list
[fp_num
].used
= 1;
1089 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1090 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1091 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
1092 if (!cortex_m3
->fpb_enabled
)
1094 LOG_DEBUG("FPB wasn't enabled, do it now");
1095 target_write_u32(target
, FP_CTRL
, 3);
1098 else if (breakpoint
->type
== BKPT_SOFT
)
1102 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1103 * semihosting; don't use that. Otherwise the BKPT
1104 * parameter is arbitrary.
1106 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1107 retval
= target_read_memory(target
,
1108 breakpoint
->address
& 0xFFFFFFFE,
1109 breakpoint
->length
, 1,
1110 breakpoint
->orig_instr
);
1111 if (retval
!= ERROR_OK
)
1113 retval
= target_write_memory(target
,
1114 breakpoint
->address
& 0xFFFFFFFE,
1115 breakpoint
->length
, 1,
1117 if (retval
!= ERROR_OK
)
1119 breakpoint
->set
= true;
1122 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1123 breakpoint
->unique_id
,
1124 (int)(breakpoint
->type
),
1125 breakpoint
->address
,
1133 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1136 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1137 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
1139 if (!breakpoint
->set
)
1141 LOG_WARNING("breakpoint not set");
1145 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1146 breakpoint
->unique_id
,
1147 (int)(breakpoint
->type
),
1148 breakpoint
->address
,
1152 if (breakpoint
->type
== BKPT_HARD
)
1154 int fp_num
= breakpoint
->set
- 1;
1155 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
1157 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1160 comparator_list
[fp_num
].used
= 0;
1161 comparator_list
[fp_num
].fpcr_value
= 0;
1162 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1166 /* restore original instruction (kept in target endianness) */
1167 if (breakpoint
->length
== 4)
1169 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1176 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1182 breakpoint
->set
= false;
1188 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1190 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1192 if (cortex_m3
->auto_bp_type
)
1194 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1195 #ifdef ARMV7_GDB_HACKS
1196 if (breakpoint
->length
!= 2) {
1197 /* XXX Hack: Replace all breakpoints with length != 2 with
1198 * a hardware breakpoint. */
1199 breakpoint
->type
= BKPT_HARD
;
1200 breakpoint
->length
= 2;
1205 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
1207 LOG_INFO("flash patch comparator requested outside code memory region");
1208 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1211 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
1213 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1214 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1217 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1219 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1220 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1223 if ((breakpoint
->length
!= 2))
1225 LOG_INFO("only breakpoints of two bytes length supported");
1226 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1229 if (breakpoint
->type
== BKPT_HARD
)
1230 cortex_m3
->fp_code_available
--;
1232 return cortex_m3_set_breakpoint(target
, breakpoint
);
1236 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1238 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1240 /* REVISIT why check? FBP can be updated with core running ... */
1241 if (target
->state
!= TARGET_HALTED
)
1243 LOG_WARNING("target not halted");
1244 return ERROR_TARGET_NOT_HALTED
;
1247 if (cortex_m3
->auto_bp_type
)
1249 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1252 if (breakpoint
->set
)
1254 cortex_m3_unset_breakpoint(target
, breakpoint
);
1257 if (breakpoint
->type
== BKPT_HARD
)
1258 cortex_m3
->fp_code_available
++;
1264 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1267 uint32_t mask
, temp
;
1268 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1270 /* watchpoint params were validated earlier */
1272 temp
= watchpoint
->length
;
1279 /* REVISIT Don't fully trust these "not used" records ... users
1280 * may set up breakpoints by hand, e.g. dual-address data value
1281 * watchpoint using comparator #1; comparator #0 matching cycle
1282 * count; send data trace info through ITM and TPIU; etc
1284 struct cortex_m3_dwt_comparator
*comparator
;
1286 for (comparator
= cortex_m3
->dwt_comparator_list
;
1287 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1288 comparator
++, dwt_num
++)
1290 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1292 LOG_ERROR("Can not find free DWT Comparator");
1295 comparator
->used
= 1;
1296 watchpoint
->set
= dwt_num
+ 1;
1298 comparator
->comp
= watchpoint
->address
;
1299 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1302 comparator
->mask
= mask
;
1303 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1306 switch (watchpoint
->rw
) {
1308 comparator
->function
= 5;
1311 comparator
->function
= 6;
1314 comparator
->function
= 7;
1317 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1318 comparator
->function
);
1320 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1321 watchpoint
->unique_id
, dwt_num
,
1322 (unsigned) comparator
->comp
,
1323 (unsigned) comparator
->mask
,
1324 (unsigned) comparator
->function
);
1329 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1331 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1332 struct cortex_m3_dwt_comparator
*comparator
;
1335 if (!watchpoint
->set
)
1337 LOG_WARNING("watchpoint (wpid: %d) not set",
1338 watchpoint
->unique_id
);
1342 dwt_num
= watchpoint
->set
- 1;
1344 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1345 watchpoint
->unique_id
, dwt_num
,
1346 (unsigned) watchpoint
->address
);
1348 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1350 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1354 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1355 comparator
->used
= 0;
1356 comparator
->function
= 0;
1357 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1358 comparator
->function
);
1360 watchpoint
->set
= false;
1366 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1368 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1370 if (cortex_m3
->dwt_comp_available
< 1)
1372 LOG_DEBUG("no comparators?");
1373 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1376 /* hardware doesn't support data value masking */
1377 if (watchpoint
->mask
!= ~(uint32_t)0) {
1378 LOG_DEBUG("watchpoint value masks not supported");
1379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1382 /* hardware allows address masks of up to 32K */
1385 for (mask
= 0; mask
< 16; mask
++) {
1386 if ((1u << mask
) == watchpoint
->length
)
1390 LOG_DEBUG("unsupported watchpoint length");
1391 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1393 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1394 LOG_DEBUG("watchpoint address is unaligned");
1395 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1398 /* Caller doesn't seem to be able to describe watching for data
1399 * values of zero; that flags "no value".
1401 * REVISIT This DWT may well be able to watch for specific data
1402 * values. Requires comparator #1 to set DATAVMATCH and match
1403 * the data, and another comparator (DATAVADDR0) matching addr.
1405 if (watchpoint
->value
) {
1406 LOG_DEBUG("data value watchpoint not YET supported");
1407 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1410 cortex_m3
->dwt_comp_available
--;
1411 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1417 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1419 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1421 /* REVISIT why check? DWT can be updated with core running ... */
1422 if (target
->state
!= TARGET_HALTED
)
1424 LOG_WARNING("target not halted");
1425 return ERROR_TARGET_NOT_HALTED
;
1428 if (watchpoint
->set
)
1430 cortex_m3_unset_watchpoint(target
, watchpoint
);
1433 cortex_m3
->dwt_comp_available
++;
1434 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1439 static void cortex_m3_enable_watchpoints(struct target
*target
)
1441 struct watchpoint
*watchpoint
= target
->watchpoints
;
1443 /* set any pending watchpoints */
1446 if (!watchpoint
->set
)
1447 cortex_m3_set_watchpoint(target
, watchpoint
);
1448 watchpoint
= watchpoint
->next
;
1452 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1453 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1456 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1457 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1459 /* NOTE: we "know" here that the register identifiers used
1460 * in the v7m header match the Cortex-M3 Debug Core Register
1461 * Selector values for R0..R15, xPSR, MSP, and PSP.
1465 /* read a normal core register */
1466 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1468 if (retval
!= ERROR_OK
)
1470 LOG_ERROR("JTAG failure %i",retval
);
1471 return ERROR_JTAG_DEVICE_ERROR
;
1473 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1476 case ARMV7M_PRIMASK
:
1477 case ARMV7M_BASEPRI
:
1478 case ARMV7M_FAULTMASK
:
1479 case ARMV7M_CONTROL
:
1480 /* Cortex-M3 packages these four registers as bitfields
1481 * in one Debug Core register. So say r0 and r2 docs;
1482 * it was removed from r1 docs, but still works.
1484 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1488 case ARMV7M_PRIMASK
:
1489 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1492 case ARMV7M_BASEPRI
:
1493 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1496 case ARMV7M_FAULTMASK
:
1497 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1500 case ARMV7M_CONTROL
:
1501 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1505 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1509 return ERROR_INVALID_ARGUMENTS
;
1515 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1516 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1520 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1521 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1523 #ifdef ARMV7_GDB_HACKS
1524 /* If the LR register is being modified, make sure it will put us
1525 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1526 * hack to deal with the fact that gdb will sometimes "forge"
1527 * return addresses, and doesn't set the LSB correctly (i.e., when
1528 * printing expressions containing function calls, it sets LR = 0.)
1529 * Valid exception return codes have bit 0 set too.
1531 if (num
== ARMV7M_R14
)
1535 /* NOTE: we "know" here that the register identifiers used
1536 * in the v7m header match the Cortex-M3 Debug Core Register
1537 * Selector values for R0..R15, xPSR, MSP, and PSP.
1541 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1542 if (retval
!= ERROR_OK
)
1546 LOG_ERROR("JTAG failure %i", retval
);
1547 r
= armv7m
->core_cache
->reg_list
+ num
;
1548 r
->dirty
= r
->valid
;
1549 return ERROR_JTAG_DEVICE_ERROR
;
1551 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1554 case ARMV7M_PRIMASK
:
1555 case ARMV7M_BASEPRI
:
1556 case ARMV7M_FAULTMASK
:
1557 case ARMV7M_CONTROL
:
1558 /* Cortex-M3 packages these four registers as bitfields
1559 * in one Debug Core register. So say r0 and r2 docs;
1560 * it was removed from r1 docs, but still works.
1562 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1566 case ARMV7M_PRIMASK
:
1567 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1570 case ARMV7M_BASEPRI
:
1571 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1574 case ARMV7M_FAULTMASK
:
1575 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1578 case ARMV7M_CONTROL
:
1579 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1583 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1585 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1589 return ERROR_INVALID_ARGUMENTS
;
1595 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1596 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1598 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1599 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1600 int retval
= ERROR_INVALID_ARGUMENTS
;
1602 /* cortex_m3 handles unaligned memory access */
1603 if (count
&& buffer
) {
1606 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1609 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1612 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1620 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1621 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1623 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1624 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1625 int retval
= ERROR_INVALID_ARGUMENTS
;
1627 if (count
&& buffer
) {
1630 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1633 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1636 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1644 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1645 uint32_t count
, uint8_t *buffer
)
1647 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1650 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1651 struct target
*target
)
1653 armv7m_build_reg_cache(target
);
1657 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1658 * on r/w if the core is not running, and clear on resume or reset ... or
1659 * at least, in a post_restore_context() method.
1662 struct dwt_reg_state
{
1663 struct target
*target
;
1665 uint32_t value
; /* scratch/cache */
1668 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1670 struct dwt_reg_state
*state
= reg
->arch_info
;
1672 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1675 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1677 struct dwt_reg_state
*state
= reg
->arch_info
;
1679 return target_write_u32(state
->target
, state
->addr
,
1680 buf_get_u32(buf
, 0, reg
->size
));
1689 static struct dwt_reg dwt_base_regs
[] = {
1690 { DWT_CTRL
, "dwt_ctrl", 32, },
1691 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1692 * increments while the core is asleep.
1694 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1695 /* plus some 8 bit counters, useful for profiling with TPIU */
1698 static struct dwt_reg dwt_comp
[] = {
1699 #define DWT_COMPARATOR(i) \
1700 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1701 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1702 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1707 #undef DWT_COMPARATOR
1710 static const struct reg_arch_type dwt_reg_type
= {
1711 .get
= cortex_m3_dwt_get_reg
,
1712 .set
= cortex_m3_dwt_set_reg
,
1716 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1718 struct dwt_reg_state
*state
;
1720 state
= calloc(1, sizeof *state
);
1723 state
->addr
= d
->addr
;
1728 r
->value
= &state
->value
;
1729 r
->arch_info
= state
;
1730 r
->type
= &dwt_reg_type
;
1734 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1737 struct reg_cache
*cache
;
1738 struct cortex_m3_dwt_comparator
*comparator
;
1741 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1743 LOG_DEBUG("no DWT");
1747 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1748 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1749 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1750 sizeof(struct cortex_m3_dwt_comparator
));
1751 if (!cm3
->dwt_comparator_list
) {
1753 cm3
->dwt_num_comp
= 0;
1754 LOG_ERROR("out of mem");
1758 cache
= calloc(1, sizeof *cache
);
1761 free(cm3
->dwt_comparator_list
);
1764 cache
->name
= "cortex-m3 dwt registers";
1765 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1766 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1767 if (!cache
->reg_list
) {
1772 for (reg
= 0; reg
< 2; reg
++)
1773 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1774 dwt_base_regs
+ reg
);
1776 comparator
= cm3
->dwt_comparator_list
;
1777 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1780 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1781 for (j
= 0; j
< 3; j
++, reg
++)
1782 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1783 dwt_comp
+ 3 * i
+ j
);
1786 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1787 cm3
->dwt_cache
= cache
;
1789 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1790 dwtcr
, cm3
->dwt_num_comp
,
1791 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1793 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1794 * implement single-address data value watchpoints ... so we
1795 * won't need to check it later, when asked to set one up.
1799 static int cortex_m3_examine(struct target
*target
)
1802 uint32_t cpuid
, fpcr
;
1804 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1805 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1807 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1810 if (!target_was_examined(target
))
1812 target_set_examined(target
);
1814 /* Read from Device Identification Registers */
1815 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1816 if (retval
!= ERROR_OK
)
1819 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1820 LOG_DEBUG("Cortex-M3 r%" PRId8
"p%" PRId8
" processor detected",
1821 (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1822 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1824 /* NOTE: FPB and DWT are both optional. */
1827 target_read_u32(target
, FP_CTRL
, &fpcr
);
1828 cortex_m3
->auto_bp_type
= 1;
1829 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1830 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1831 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1832 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1833 cortex_m3
->fpb_enabled
= fpcr
& 1;
1834 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1836 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1837 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1839 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1842 cortex_m3_dwt_setup(cortex_m3
, target
);
1844 /* These hardware breakpoints only work for code in flash! */
1845 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1846 target_name(target
),
1847 cortex_m3
->fp_num_code
,
1848 cortex_m3
->dwt_num_comp
);
1854 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1859 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1860 *ctrl
= (uint8_t)dcrdr
;
1861 *value
= (uint8_t)(dcrdr
>> 8);
1863 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1865 /* write ack back to software dcc register
1866 * signify we have read data */
1867 if (dcrdr
& (1 << 0))
1870 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1871 if (retval
!= ERROR_OK
)
1878 static int cortex_m3_target_request_data(struct target
*target
,
1879 uint32_t size
, uint8_t *buffer
)
1881 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1882 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1887 for (i
= 0; i
< (size
* 4); i
++)
1889 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1896 static int cortex_m3_handle_target_request(void *priv
)
1898 struct target
*target
= priv
;
1899 if (!target_was_examined(target
))
1901 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1902 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1904 if (!target
->dbg_msg_enabled
)
1907 if (target
->state
== TARGET_RUNNING
)
1912 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1914 /* check if we have data */
1915 if (ctrl
& (1 << 0))
1919 /* we assume target is quick enough */
1921 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1922 request
|= (data
<< 8);
1923 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1924 request
|= (data
<< 16);
1925 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1926 request
|= (data
<< 24);
1927 target_request(target
, request
);
1934 static int cortex_m3_init_arch_info(struct target
*target
,
1935 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1938 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1940 armv7m_init_arch_info(target
, armv7m
);
1942 /* prepare JTAG information for the new target */
1943 cortex_m3
->jtag_info
.tap
= tap
;
1944 cortex_m3
->jtag_info
.scann_size
= 4;
1946 /* default reset mode is to use srst if fitted
1947 * if not it will use CORTEX_M3_RESET_VECTRESET */
1948 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SRST
;
1950 armv7m
->arm
.dap
= &armv7m
->dap
;
1952 /* Leave (only) generic DAP stuff for debugport_init(); */
1953 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
1954 armv7m
->dap
.memaccess_tck
= 8;
1955 /* Cortex-M3 has 4096 bytes autoincrement range */
1956 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1958 /* register arch-specific functions */
1959 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1961 armv7m
->post_debug_entry
= NULL
;
1963 armv7m
->pre_restore_context
= NULL
;
1965 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1966 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1968 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1970 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1978 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1980 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1982 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1983 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1988 /*--------------------------------------------------------------------------*/
1990 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1991 struct cortex_m3_common
*cm3
)
1993 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1994 command_print(cmd_ctx
, "target is not a Cortex-M3");
1995 return ERROR_TARGET_INVALID
;
2001 * Only stuff below this line should need to verify that its target
2002 * is a Cortex-M3. Everything else should have indirected through the
2003 * cortexm3_target structure, which is only used with CM3 targets.
2006 static const struct {
2010 { "hard_err", VC_HARDERR
, },
2011 { "int_err", VC_INTERR
, },
2012 { "bus_err", VC_BUSERR
, },
2013 { "state_err", VC_STATERR
, },
2014 { "chk_err", VC_CHKERR
, },
2015 { "nocp_err", VC_NOCPERR
, },
2016 { "mm_err", VC_MMERR
, },
2017 { "reset", VC_CORERESET
, },
2020 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2022 struct target
*target
= get_current_target(CMD_CTX
);
2023 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2024 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2025 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
2029 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2030 if (retval
!= ERROR_OK
)
2033 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2034 if (retval
!= ERROR_OK
)
2040 if (CMD_ARGC
== 1) {
2041 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2042 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2043 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2044 | VC_MMERR
| VC_CORERESET
;
2046 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
2050 while (CMD_ARGC
-- > 0) {
2052 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2053 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2055 catch |= vec_ids
[i
].mask
;
2058 if (i
== ARRAY_SIZE(vec_ids
)) {
2059 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2060 return ERROR_INVALID_ARGUMENTS
;
2064 /* For now, armv7m->demcr only stores vector catch flags. */
2065 armv7m
->demcr
= catch;
2070 /* write, but don't assume it stuck (why not??) */
2071 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2072 if (retval
!= ERROR_OK
)
2074 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2075 if (retval
!= ERROR_OK
)
2078 /* FIXME be sure to clear DEMCR on clean server shutdown.
2079 * Otherwise the vector catch hardware could fire when there's
2080 * no debugger hooked up, causing much confusion...
2084 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
2086 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2087 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2093 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2095 struct target
*target
= get_current_target(CMD_CTX
);
2096 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2099 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2100 if (retval
!= ERROR_OK
)
2103 if (target
->state
!= TARGET_HALTED
)
2105 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2112 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], enable
);
2113 uint32_t mask_on
= C_HALT
| (enable
? C_MASKINTS
: 0);
2114 uint32_t mask_off
= enable
? 0 : C_MASKINTS
;
2115 cortex_m3_write_debug_halt_mask(target
, mask_on
, mask_off
);
2118 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s",
2119 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
2124 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2126 struct target
*target
= get_current_target(CMD_CTX
);
2127 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2131 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2132 if (retval
!= ERROR_OK
)
2137 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2138 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2139 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2140 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2142 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SRST
;
2145 switch (cortex_m3
->soft_reset_config
)
2147 case CORTEX_M3_RESET_SRST
:
2148 reset_config
= "srst";
2151 case CORTEX_M3_RESET_SYSRESETREQ
:
2152 reset_config
= "sysresetreq";
2155 case CORTEX_M3_RESET_VECTRESET
:
2156 reset_config
= "vectreset";
2160 reset_config
= "unknown";
2164 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2169 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2172 .handler
= handle_cortex_m3_mask_interrupts_command
,
2173 .mode
= COMMAND_EXEC
,
2174 .help
= "mask cortex_m3 interrupts",
2175 .usage
= "['on'|'off']",
2178 .name
= "vector_catch",
2179 .handler
= handle_cortex_m3_vector_catch_command
,
2180 .mode
= COMMAND_EXEC
,
2181 .help
= "configure hardware vectors to trigger debug entry",
2182 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2185 .name
= "reset_config",
2186 .handler
= handle_cortex_m3_reset_config_command
,
2187 .mode
= COMMAND_ANY
,
2188 .help
= "configure software reset handling",
2189 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2191 COMMAND_REGISTRATION_DONE
2193 static const struct command_registration cortex_m3_command_handlers
[] = {
2195 .chain
= armv7m_command_handlers
,
2198 .name
= "cortex_m3",
2199 .mode
= COMMAND_EXEC
,
2200 .help
= "Cortex-M3 command group",
2201 .chain
= cortex_m3_exec_command_handlers
,
2203 COMMAND_REGISTRATION_DONE
2206 struct target_type cortexm3_target
=
2208 .name
= "cortex_m3",
2210 .poll
= cortex_m3_poll
,
2211 .arch_state
= armv7m_arch_state
,
2213 .target_request_data
= cortex_m3_target_request_data
,
2215 .halt
= cortex_m3_halt
,
2216 .resume
= cortex_m3_resume
,
2217 .step
= cortex_m3_step
,
2219 .assert_reset
= cortex_m3_assert_reset
,
2220 .deassert_reset
= cortex_m3_deassert_reset
,
2221 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2223 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2225 .read_memory
= cortex_m3_read_memory
,
2226 .write_memory
= cortex_m3_write_memory
,
2227 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2228 .checksum_memory
= armv7m_checksum_memory
,
2229 .blank_check_memory
= armv7m_blank_check_memory
,
2231 .run_algorithm
= armv7m_run_algorithm
,
2233 .add_breakpoint
= cortex_m3_add_breakpoint
,
2234 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2235 .add_watchpoint
= cortex_m3_add_watchpoint
,
2236 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2238 .commands
= cortex_m3_command_handlers
,
2239 .target_create
= cortex_m3_target_create
,
2240 .init_target
= cortex_m3_init_target
,
2241 .examine
= cortex_m3_examine
,
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