1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
30 static char* etb_reg_list
[] =
37 "ETB_ram_read_pointer",
38 "ETB_ram_write_pointer",
39 "ETB_trigger_counter",
43 static int etb_get_reg(struct reg
*reg
);
45 static int etb_set_instr(struct etb
*etb
, uint32_t new_instr
)
53 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
55 struct scan_field field
;
57 field
.num_bits
= tap
->ir_length
;
58 void * t
= calloc(DIV_ROUND_UP(field
.num_bits
, 8), 1);
60 buf_set_u32(t
, 0, field
.num_bits
, new_instr
);
62 field
.in_value
= NULL
;
64 jtag_add_ir_scan(tap
, &field
, TAP_IDLE
);
72 static int etb_scann(struct etb
*etb
, uint32_t new_scan_chain
)
74 if (etb
->cur_scan_chain
!= new_scan_chain
)
76 struct scan_field field
;
79 void * t
= calloc(DIV_ROUND_UP(field
.num_bits
, 8), 1);
81 buf_set_u32(t
, 0, field
.num_bits
, new_scan_chain
);
83 field
.in_value
= NULL
;
85 /* select INTEST instruction */
86 etb_set_instr(etb
, 0x2);
87 jtag_add_dr_scan(etb
->tap
, 1, &field
, TAP_IDLE
);
89 etb
->cur_scan_chain
= new_scan_chain
;
97 static int etb_read_reg_w_check(struct reg
*, uint8_t *, uint8_t *);
98 static int etb_set_reg_w_exec(struct reg
*, uint8_t *);
100 static int etb_read_reg(struct reg
*reg
)
102 return etb_read_reg_w_check(reg
, NULL
, NULL
);
105 static int etb_get_reg(struct reg
*reg
)
109 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
111 LOG_ERROR("BUG: error scheduling ETB register read");
115 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
117 LOG_ERROR("ETB register read failed");
124 static const struct reg_arch_type etb_reg_type
= {
126 .set
= etb_set_reg_w_exec
,
129 struct reg_cache
* etb_build_reg_cache(struct etb
*etb
)
131 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
132 struct reg
*reg_list
= NULL
;
133 struct etb_reg
*arch_info
= NULL
;
137 /* the actual registers are kept in two arrays */
138 reg_list
= calloc(num_regs
, sizeof(struct reg
));
139 arch_info
= calloc(num_regs
, sizeof(struct etb_reg
));
141 /* fill in values for the reg cache */
142 reg_cache
->name
= "etb registers";
143 reg_cache
->next
= NULL
;
144 reg_cache
->reg_list
= reg_list
;
145 reg_cache
->num_regs
= num_regs
;
147 /* set up registers */
148 for (i
= 0; i
< num_regs
; i
++)
150 reg_list
[i
].name
= etb_reg_list
[i
];
151 reg_list
[i
].size
= 32;
152 reg_list
[i
].dirty
= 0;
153 reg_list
[i
].valid
= 0;
154 reg_list
[i
].value
= calloc(1, 4);
155 reg_list
[i
].arch_info
= &arch_info
[i
];
156 reg_list
[i
].type
= &etb_reg_type
;
157 reg_list
[i
].size
= 32;
158 arch_info
[i
].addr
= i
;
159 arch_info
[i
].etb
= etb
;
165 static void etb_getbuf(jtag_callback_data_t arg
)
167 uint8_t *in
= (uint8_t *)arg
;
169 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
173 static int etb_read_ram(struct etb
*etb
, uint32_t *data
, int num_frames
)
175 struct scan_field fields
[3];
179 etb_set_instr(etb
, 0xc);
181 fields
[0].num_bits
= 32;
182 fields
[0].out_value
= NULL
;
183 fields
[0].in_value
= NULL
;
185 fields
[1].num_bits
= 7;
187 fields
[1].out_value
= &temp1
;
188 buf_set_u32(&temp1
, 0, 7, 4);
189 fields
[1].in_value
= NULL
;
191 fields
[2].num_bits
= 1;
193 fields
[2].out_value
= &temp2
;
194 buf_set_u32(&temp2
, 0, 1, 0);
195 fields
[2].in_value
= NULL
;
197 jtag_add_dr_scan(etb
->tap
, 3, fields
, TAP_IDLE
);
199 for (i
= 0; i
< num_frames
; i
++)
201 /* ensure nR/W reamins set to read */
202 buf_set_u32(&temp2
, 0, 1, 0);
204 /* address remains set to 0x4 (RAM data) until we read the last frame */
205 if (i
< num_frames
- 1)
206 buf_set_u32(&temp1
, 0, 7, 4);
208 buf_set_u32(&temp1
, 0, 7, 0);
210 fields
[0].in_value
= (uint8_t *)(data
+ i
);
211 jtag_add_dr_scan(etb
->tap
, 3, fields
, TAP_IDLE
);
213 jtag_add_callback(etb_getbuf
, (jtag_callback_data_t
)(data
+ i
));
216 jtag_execute_queue();
221 static int etb_read_reg_w_check(struct reg
*reg
,
222 uint8_t* check_value
, uint8_t* check_mask
)
224 struct etb_reg
*etb_reg
= reg
->arch_info
;
225 uint8_t reg_addr
= etb_reg
->addr
& 0x7f;
226 struct scan_field fields
[3];
228 LOG_DEBUG("%i", (int)(etb_reg
->addr
));
230 etb_scann(etb_reg
->etb
, 0x0);
231 etb_set_instr(etb_reg
->etb
, 0xc);
233 fields
[0].num_bits
= 32;
234 fields
[0].out_value
= reg
->value
;
235 fields
[0].in_value
= NULL
;
236 fields
[0].check_value
= NULL
;
237 fields
[0].check_mask
= NULL
;
239 fields
[1].num_bits
= 7;
241 fields
[1].out_value
= &temp1
;
242 buf_set_u32(&temp1
, 0, 7, reg_addr
);
243 fields
[1].in_value
= NULL
;
244 fields
[1].check_value
= NULL
;
245 fields
[1].check_mask
= NULL
;
247 fields
[2].num_bits
= 1;
249 fields
[2].out_value
= &temp2
;
250 buf_set_u32(&temp2
, 0, 1, 0);
251 fields
[2].in_value
= NULL
;
252 fields
[2].check_value
= NULL
;
253 fields
[2].check_mask
= NULL
;
255 jtag_add_dr_scan(etb_reg
->etb
->tap
, 3, fields
, TAP_IDLE
);
257 /* read the identification register in the second run, to make sure we
258 * don't read the ETB data register twice, skipping every second entry
260 buf_set_u32(&temp1
, 0, 7, 0x0);
261 fields
[0].in_value
= reg
->value
;
262 fields
[0].check_value
= check_value
;
263 fields
[0].check_mask
= check_mask
;
265 jtag_add_dr_scan_check(etb_reg
->etb
->tap
, 3, fields
, TAP_IDLE
);
270 static int etb_write_reg(struct reg
*, uint32_t);
272 static int etb_set_reg(struct reg
*reg
, uint32_t value
)
276 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
278 LOG_ERROR("BUG: error scheduling ETB register write");
282 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
289 static int etb_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
293 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
295 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
297 LOG_ERROR("ETB: register write failed");
303 static int etb_write_reg(struct reg
*reg
, uint32_t value
)
305 struct etb_reg
*etb_reg
= reg
->arch_info
;
306 uint8_t reg_addr
= etb_reg
->addr
& 0x7f;
307 struct scan_field fields
[3];
309 LOG_DEBUG("%i: 0x%8.8" PRIx32
"", (int)(etb_reg
->addr
), value
);
311 etb_scann(etb_reg
->etb
, 0x0);
312 etb_set_instr(etb_reg
->etb
, 0xc);
314 fields
[0].num_bits
= 32;
316 fields
[0].out_value
= temp0
;
317 buf_set_u32(&temp0
, 0, 32, value
);
318 fields
[0].in_value
= NULL
;
320 fields
[1].num_bits
= 7;
322 fields
[1].out_value
= &temp1
;
323 buf_set_u32(&temp1
, 0, 7, reg_addr
);
324 fields
[1].in_value
= NULL
;
326 fields
[2].num_bits
= 1;
328 fields
[2].out_value
= &temp2
;
329 buf_set_u32(&temp2
, 0, 1, 1);
331 fields
[2].in_value
= NULL
;
335 COMMAND_HANDLER(handle_etb_config_command
)
337 struct target
*target
;
338 struct jtag_tap
*tap
;
343 return ERROR_COMMAND_SYNTAX_ERROR
;
346 target
= get_target(CMD_ARGV
[0]);
350 LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV
[0]);
354 arm
= target_to_arm(target
);
357 command_print(CMD_CTX
, "ETB: '%s' isn't an ARM", CMD_ARGV
[0]);
361 tap
= jtag_tap_by_string(CMD_ARGV
[1]);
364 command_print(CMD_CTX
, "ETB: TAP %s does not exist", CMD_ARGV
[1]);
370 struct etb
*etb
= malloc(sizeof(struct etb
));
372 arm
->etm
->capture_driver_priv
= etb
;
375 etb
->cur_scan_chain
= 0xffffffff;
376 etb
->reg_cache
= NULL
;
382 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
389 COMMAND_HANDLER(handle_etb_trigger_percent_command
)
391 struct target
*target
;
393 struct etm_context
*etm
;
396 target
= get_current_target(CMD_CTX
);
397 arm
= target_to_arm(target
);
400 command_print(CMD_CTX
, "ETB: current target isn't an ARM");
406 command_print(CMD_CTX
, "ETB: target has no ETM configured");
409 if (etm
->capture_driver
!= &etb_capture_driver
) {
410 command_print(CMD_CTX
, "ETB: target not using ETB");
413 etb
= arm
->etm
->capture_driver_priv
;
418 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], new_value
);
419 if ((new_value
< 2) || (new_value
> 100))
420 command_print(CMD_CTX
,
421 "valid percentages are 2%% to 100%%");
423 etb
->trigger_percent
= (unsigned) new_value
;
426 command_print(CMD_CTX
, "%d percent of tracebuffer fills after trigger",
427 etb
->trigger_percent
);
432 static const struct command_registration etb_config_command_handlers
[] = {
434 /* NOTE: with ADIv5, ETBs are accessed using DAP operations,
435 * possibly over SWD, not through separate TAPs...
438 .handler
= handle_etb_config_command
,
439 .mode
= COMMAND_CONFIG
,
440 .help
= "Associate ETB with target and JTAG TAP.",
441 .usage
= "target tap",
444 .name
= "trigger_percent",
445 .handler
= handle_etb_trigger_percent_command
,
446 .mode
= COMMAND_EXEC
,
447 .help
= "Set percent of trace buffer to be filled "
448 "after the trigger occurs (2..100).",
449 .usage
= "[percent]",
451 COMMAND_REGISTRATION_DONE
453 static const struct command_registration etb_command_handlers
[] = {
457 .help
= "Emebdded Trace Buffer command group",
458 .chain
= etb_config_command_handlers
,
460 COMMAND_REGISTRATION_DONE
463 static int etb_init(struct etm_context
*etm_ctx
)
465 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
467 etb
->etm_ctx
= etm_ctx
;
469 /* identify ETB RAM depth and width */
470 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
471 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
472 jtag_execute_queue();
474 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
475 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
477 etb
->trigger_percent
= 50;
482 static trace_status_t
etb_status(struct etm_context
*etm_ctx
)
484 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
485 struct reg
*control
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
486 struct reg
*status
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
487 trace_status_t retval
= 0;
488 int etb_timeout
= 100;
490 etb
->etm_ctx
= etm_ctx
;
492 /* read control and status registers */
493 etb_read_reg(control
);
494 etb_read_reg(status
);
495 jtag_execute_queue();
497 /* See if it's (still) active */
498 retval
= buf_get_u32(control
->value
, 0, 1) ? TRACE_RUNNING
: TRACE_IDLE
;
500 /* check Full bit to identify wraparound/overflow */
501 if (buf_get_u32(status
->value
, 0, 1) == 1)
502 retval
|= TRACE_OVERFLOWED
;
504 /* check Triggered bit to identify trigger condition */
505 if (buf_get_u32(status
->value
, 1, 1) == 1)
506 retval
|= TRACE_TRIGGERED
;
508 /* check AcqComp to see if trigger counter dropped to zero */
509 if (buf_get_u32(status
->value
, 2, 1) == 1) {
510 /* wait for DFEmpty */
511 while (etb_timeout
-- && buf_get_u32(status
->value
, 3, 1) == 0)
514 if (etb_timeout
== 0)
515 LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x",
516 (unsigned) buf_get_u32(status
->value
, 0, 4));
518 if (!(etm_ctx
->capture_status
& TRACE_TRIGGERED
))
519 LOG_WARNING("ETB: trace complete without triggering?");
521 retval
|= TRACE_COMPLETED
;
524 /* NOTE: using a trigger is optional; and at least ETB11 has a mode
525 * where it can ignore the trigger counter.
528 /* update recorded state */
529 etm_ctx
->capture_status
= retval
;
534 static int etb_read_trace(struct etm_context
*etm_ctx
)
536 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
538 int num_frames
= etb
->ram_depth
;
539 uint32_t *trace_data
= NULL
;
542 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
543 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
544 jtag_execute_queue();
546 /* check if we overflowed, and adjust first frame of the trace accordingly
547 * if we didn't overflow, read only up to the frame that would be written next,
548 * i.e. don't read invalid entries
550 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
552 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
556 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
559 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
561 /* read data into temporary array for unpacking */
562 trace_data
= malloc(sizeof(uint32_t) * num_frames
);
563 etb_read_ram(etb
, trace_data
, num_frames
);
565 if (etm_ctx
->trace_depth
> 0)
567 free(etm_ctx
->trace_data
);
570 if ((etm_ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
571 etm_ctx
->trace_depth
= num_frames
* 3;
572 else if ((etm_ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
573 etm_ctx
->trace_depth
= num_frames
* 2;
575 etm_ctx
->trace_depth
= num_frames
;
577 etm_ctx
->trace_data
= malloc(sizeof(struct etmv1_trace_data
) * etm_ctx
->trace_depth
);
579 for (i
= 0, j
= 0; i
< num_frames
; i
++)
581 if ((etm_ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
584 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
585 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
586 etm_ctx
->trace_data
[j
].flags
= 0;
587 if ((trace_data
[i
] & 0x80) >> 7)
589 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
591 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
593 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
594 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
597 /* trace word j + 1 */
598 etm_ctx
->trace_data
[j
+ 1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
599 etm_ctx
->trace_data
[j
+ 1].packet
= (trace_data
[i
] & 0x7800) >> 11;
600 etm_ctx
->trace_data
[j
+ 1].flags
= 0;
601 if ((trace_data
[i
] & 0x8000) >> 15)
603 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRACESYNC_CYCLE
;
605 if (etm_ctx
->trace_data
[j
+ 1].pipestat
== STAT_TR
)
607 etm_ctx
->trace_data
[j
+ 1].pipestat
= etm_ctx
->trace_data
[j
+ 1].packet
& 0x7;
608 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRIGGER_CYCLE
;
611 /* trace word j + 2 */
612 etm_ctx
->trace_data
[j
+ 2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
613 etm_ctx
->trace_data
[j
+ 2].packet
= (trace_data
[i
] & 0x780000) >> 19;
614 etm_ctx
->trace_data
[j
+ 2].flags
= 0;
615 if ((trace_data
[i
] & 0x800000) >> 23)
617 etm_ctx
->trace_data
[j
+ 2].flags
|= ETMV1_TRACESYNC_CYCLE
;
619 if (etm_ctx
->trace_data
[j
+ 2].pipestat
== STAT_TR
)
621 etm_ctx
->trace_data
[j
+ 2].pipestat
= etm_ctx
->trace_data
[j
+ 2].packet
& 0x7;
622 etm_ctx
->trace_data
[j
+ 2].flags
|= ETMV1_TRIGGER_CYCLE
;
627 else if ((etm_ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
630 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
631 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
632 etm_ctx
->trace_data
[j
].flags
= 0;
633 if ((trace_data
[i
] & 0x800) >> 11)
635 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
637 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
639 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
640 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
643 /* trace word j + 1 */
644 etm_ctx
->trace_data
[j
+ 1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
645 etm_ctx
->trace_data
[j
+ 1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
646 etm_ctx
->trace_data
[j
+ 1].flags
= 0;
647 if ((trace_data
[i
] & 0x800000) >> 23)
649 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRACESYNC_CYCLE
;
651 if (etm_ctx
->trace_data
[j
+ 1].pipestat
== STAT_TR
)
653 etm_ctx
->trace_data
[j
+ 1].pipestat
= etm_ctx
->trace_data
[j
+ 1].packet
& 0x7;
654 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRIGGER_CYCLE
;
662 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
663 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
664 etm_ctx
->trace_data
[j
].flags
= 0;
665 if ((trace_data
[i
] & 0x80000) >> 19)
667 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
669 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
671 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
672 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
684 static int etb_start_capture(struct etm_context
*etm_ctx
)
686 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
687 uint32_t etb_ctrl_value
= 0x1;
688 uint32_t trigger_count
;
690 if ((etm_ctx
->control
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
692 if ((etm_ctx
->control
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
694 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
695 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
697 etb_ctrl_value
|= 0x2;
700 if ((etm_ctx
->control
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
) {
701 LOG_ERROR("ETB: can't run in multiplexed mode");
702 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
705 trigger_count
= (etb
->ram_depth
* etb
->trigger_percent
) / 100;
707 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
708 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
709 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
710 jtag_execute_queue();
712 /* we're starting a new trace, initialize capture status */
713 etm_ctx
->capture_status
= TRACE_RUNNING
;
718 static int etb_stop_capture(struct etm_context
*etm_ctx
)
720 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
721 struct reg
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
723 etb_write_reg(etb_ctrl_reg
, 0x0);
724 jtag_execute_queue();
726 /* trace stopped, just clear running flag, but preserve others */
727 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
732 struct etm_capture_driver etb_capture_driver
=
735 .commands
= etb_command_handlers
,
737 .status
= etb_status
,
738 .start_capture
= etb_start_capture
,
739 .stop_capture
= etb_stop_capture
,
740 .read_trace
= etb_read_trace
,
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