1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
53 static int etm_reg_arch_info
[] =
55 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
56 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
57 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
58 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
59 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
60 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
61 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
62 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
63 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
64 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
65 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
66 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
67 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
68 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
71 static int etm_reg_arch_size_info
[] =
73 32, 32, 17, 8, 3, 9, 32, 16,
74 17, 26, 25, 8, 17, 32, 32, 17,
75 32, 32, 32, 32, 32, 32, 32, 32,
76 32, 32, 32, 32, 32, 32, 32, 32,
77 7, 7, 7, 7, 7, 7, 7, 7,
78 7, 7, 7, 7, 7, 7, 7, 7,
79 32, 32, 32, 32, 32, 32, 32, 32,
80 32, 32, 32, 32, 32, 32, 32, 32,
81 32, 32, 32, 32, 32, 32, 32, 32,
82 32, 32, 32, 32, 32, 32, 32, 32,
83 16, 16, 16, 16, 18, 18, 18, 18,
84 17, 17, 17, 17, 16, 16, 16, 16,
85 17, 17, 17, 17, 17, 17, 2,
86 17, 17, 17, 17, 32, 32, 32, 32
89 static char* etm_reg_list
[] =
97 "ETM_TRACE_RESOURCE_CTRL",
100 "ETM_TRACE_EN_CTRL1",
101 "ETM_FIFOFULL_REGION",
102 "ETM_FIFOFULL_LEVEL",
103 "ETM_VIEWDATA_EVENT",
104 "ETM_VIEWDATA_CTRL1",
105 "ETM_VIEWDATA_CTRL2",
106 "ETM_VIEWDATA_CTRL3",
107 "ETM_ADDR_COMPARATOR_VALUE1",
108 "ETM_ADDR_COMPARATOR_VALUE2",
109 "ETM_ADDR_COMPARATOR_VALUE3",
110 "ETM_ADDR_COMPARATOR_VALUE4",
111 "ETM_ADDR_COMPARATOR_VALUE5",
112 "ETM_ADDR_COMPARATOR_VALUE6",
113 "ETM_ADDR_COMPARATOR_VALUE7",
114 "ETM_ADDR_COMPARATOR_VALUE8",
115 "ETM_ADDR_COMPARATOR_VALUE9",
116 "ETM_ADDR_COMPARATOR_VALUE10",
117 "ETM_ADDR_COMPARATOR_VALUE11",
118 "ETM_ADDR_COMPARATOR_VALUE12",
119 "ETM_ADDR_COMPARATOR_VALUE13",
120 "ETM_ADDR_COMPARATOR_VALUE14",
121 "ETM_ADDR_COMPARATOR_VALUE15",
122 "ETM_ADDR_COMPARATOR_VALUE16",
123 "ETM_ADDR_ACCESS_TYPE1",
124 "ETM_ADDR_ACCESS_TYPE2",
125 "ETM_ADDR_ACCESS_TYPE3",
126 "ETM_ADDR_ACCESS_TYPE4",
127 "ETM_ADDR_ACCESS_TYPE5",
128 "ETM_ADDR_ACCESS_TYPE6",
129 "ETM_ADDR_ACCESS_TYPE7",
130 "ETM_ADDR_ACCESS_TYPE8",
131 "ETM_ADDR_ACCESS_TYPE9",
132 "ETM_ADDR_ACCESS_TYPE10",
133 "ETM_ADDR_ACCESS_TYPE11",
134 "ETM_ADDR_ACCESS_TYPE12",
135 "ETM_ADDR_ACCESS_TYPE13",
136 "ETM_ADDR_ACCESS_TYPE14",
137 "ETM_ADDR_ACCESS_TYPE15",
138 "ETM_ADDR_ACCESS_TYPE16",
139 "ETM_DATA_COMPARATOR_VALUE1",
140 "ETM_DATA_COMPARATOR_VALUE2",
141 "ETM_DATA_COMPARATOR_VALUE3",
142 "ETM_DATA_COMPARATOR_VALUE4",
143 "ETM_DATA_COMPARATOR_VALUE5",
144 "ETM_DATA_COMPARATOR_VALUE6",
145 "ETM_DATA_COMPARATOR_VALUE7",
146 "ETM_DATA_COMPARATOR_VALUE8",
147 "ETM_DATA_COMPARATOR_VALUE9",
148 "ETM_DATA_COMPARATOR_VALUE10",
149 "ETM_DATA_COMPARATOR_VALUE11",
150 "ETM_DATA_COMPARATOR_VALUE12",
151 "ETM_DATA_COMPARATOR_VALUE13",
152 "ETM_DATA_COMPARATOR_VALUE14",
153 "ETM_DATA_COMPARATOR_VALUE15",
154 "ETM_DATA_COMPARATOR_VALUE16",
155 "ETM_DATA_COMPARATOR_MASK1",
156 "ETM_DATA_COMPARATOR_MASK2",
157 "ETM_DATA_COMPARATOR_MASK3",
158 "ETM_DATA_COMPARATOR_MASK4",
159 "ETM_DATA_COMPARATOR_MASK5",
160 "ETM_DATA_COMPARATOR_MASK6",
161 "ETM_DATA_COMPARATOR_MASK7",
162 "ETM_DATA_COMPARATOR_MASK8",
163 "ETM_DATA_COMPARATOR_MASK9",
164 "ETM_DATA_COMPARATOR_MASK10",
165 "ETM_DATA_COMPARATOR_MASK11",
166 "ETM_DATA_COMPARATOR_MASK12",
167 "ETM_DATA_COMPARATOR_MASK13",
168 "ETM_DATA_COMPARATOR_MASK14",
169 "ETM_DATA_COMPARATOR_MASK15",
170 "ETM_DATA_COMPARATOR_MASK16",
171 "ETM_COUNTER_INITAL_VALUE1",
172 "ETM_COUNTER_INITAL_VALUE2",
173 "ETM_COUNTER_INITAL_VALUE3",
174 "ETM_COUNTER_INITAL_VALUE4",
175 "ETM_COUNTER_ENABLE1",
176 "ETM_COUNTER_ENABLE2",
177 "ETM_COUNTER_ENABLE3",
178 "ETM_COUNTER_ENABLE4",
179 "ETM_COUNTER_RELOAD_VALUE1",
180 "ETM_COUNTER_RELOAD_VALUE2",
181 "ETM_COUNTER_RELOAD_VALUE3",
182 "ETM_COUNTER_RELOAD_VALUE4",
183 "ETM_COUNTER_VALUE1",
184 "ETM_COUNTER_VALUE2",
185 "ETM_COUNTER_VALUE3",
186 "ETM_COUNTER_VALUE4",
187 "ETM_SEQUENCER_CTRL1",
188 "ETM_SEQUENCER_CTRL2",
189 "ETM_SEQUENCER_CTRL3",
190 "ETM_SEQUENCER_CTRL4",
191 "ETM_SEQUENCER_CTRL5",
192 "ETM_SEQUENCER_CTRL6",
193 "ETM_SEQUENCER_STATE",
194 "ETM_EXTERNAL_OUTPUT1",
195 "ETM_EXTERNAL_OUTPUT2",
196 "ETM_EXTERNAL_OUTPUT3",
197 "ETM_EXTERNAL_OUTPUT4",
198 "ETM_CONTEXTID_COMPARATOR_VALUE1",
199 "ETM_CONTEXTID_COMPARATOR_VALUE2",
200 "ETM_CONTEXTID_COMPARATOR_VALUE3",
201 "ETM_CONTEXTID_COMPARATOR_MASK"
204 static int etm_reg_arch_type
= -1;
206 static int etm_get_reg(reg_t
*reg
);
207 static int etm_read_reg_w_check(reg_t
*reg
,
208 uint8_t* check_value
, uint8_t* check_mask
);
209 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
210 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
211 static int etm_write_reg(reg_t
*reg
, uint32_t value
);
213 static command_t
*etm_cmd
;
216 /* Look up register by ID ... most ETM instances only
217 * support a subset of the possible registers.
219 static reg_t
*etm_reg_lookup(etm_context_t
*etm_ctx
, unsigned id
)
221 reg_cache_t
*cache
= etm_ctx
->reg_cache
;
224 for (i
= 0; i
< cache
->num_regs
; i
++) {
225 struct etm_reg_s
*reg
= cache
->reg_list
[i
].arch_info
;
227 if (reg
->addr
== (int) id
)
228 return &cache
->reg_list
[i
];
231 /* caller asking for nonexistent register is a bug! */
232 /* REVISIT say which of the N targets was involved */
233 LOG_ERROR("ETM: register 0x%02x not available", id
);
237 reg_cache_t
*etm_build_reg_cache(target_t
*target
,
238 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
240 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
241 reg_t
*reg_list
= NULL
;
242 etm_reg_t
*arch_info
= NULL
;
243 int num_regs
= sizeof(etm_reg_arch_info
)/sizeof(int);
246 /* register a register arch-type for etm registers only once */
247 if (etm_reg_arch_type
== -1)
248 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
, etm_set_reg_w_exec
);
250 /* the actual registers are kept in two arrays */
251 reg_list
= calloc(num_regs
, sizeof(reg_t
));
252 arch_info
= calloc(num_regs
, sizeof(etm_reg_t
));
254 /* fill in values for the reg cache */
255 reg_cache
->name
= "etm registers";
256 reg_cache
->next
= NULL
;
257 reg_cache
->reg_list
= reg_list
;
258 reg_cache
->num_regs
= num_regs
;
260 /* set up registers */
261 for (i
= 0; i
< num_regs
; i
++)
263 reg_list
[i
].name
= etm_reg_list
[i
];
264 reg_list
[i
].size
= 32;
265 reg_list
[i
].value
= calloc(1, 4);
266 reg_list
[i
].arch_info
= &arch_info
[i
];
267 reg_list
[i
].arch_type
= etm_reg_arch_type
;
268 reg_list
[i
].size
= etm_reg_arch_size_info
[i
];
269 arch_info
[i
].addr
= etm_reg_arch_info
[i
];
270 arch_info
[i
].jtag_info
= jtag_info
;
273 /* the ETM might have an ETB connected */
274 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
276 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
280 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
281 for (i
= 0; i
< num_regs
; i
++)
283 free(reg_list
[i
].value
);
290 reg_cache
->next
= etb_build_reg_cache(etb
);
292 etb
->reg_cache
= reg_cache
->next
;
299 static int etm_read_reg(reg_t
*reg
)
301 return etm_read_reg_w_check(reg
, NULL
, NULL
);
304 static int etm_store_reg(reg_t
*reg
)
306 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
309 int etm_setup(target_t
*target
)
312 uint32_t etm_ctrl_value
;
313 armv4_5_common_t
*armv4_5
= target
->arch_info
;
314 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
315 etm_context_t
*etm_ctx
= arm7_9
->etm_ctx
;
318 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
322 /* initialize some ETM control register settings */
323 etm_get_reg(etm_ctrl_reg
);
324 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
326 /* clear the ETM powerdown bit (0) */
327 etm_ctrl_value
&= ~0x1;
329 /* configure port width (6:4), mode (17:16) and clocking (13) */
330 etm_ctrl_value
= (etm_ctrl_value
&
331 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
334 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
335 etm_store_reg(etm_ctrl_reg
);
337 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
340 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
342 LOG_ERROR("ETM capture driver initialization failed");
348 static int etm_get_reg(reg_t
*reg
)
352 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
354 LOG_ERROR("BUG: error scheduling etm register read");
358 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
360 LOG_ERROR("register read failed");
367 static int etm_read_reg_w_check(reg_t
*reg
,
368 uint8_t* check_value
, uint8_t* check_mask
)
370 etm_reg_t
*etm_reg
= reg
->arch_info
;
371 uint8_t reg_addr
= etm_reg
->addr
& 0x7f;
372 scan_field_t fields
[3];
374 LOG_DEBUG("%i", etm_reg
->addr
);
376 jtag_set_end_state(TAP_IDLE
);
377 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
378 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
380 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
381 fields
[0].num_bits
= 32;
382 fields
[0].out_value
= reg
->value
;
383 fields
[0].in_value
= NULL
;
384 fields
[0].check_value
= NULL
;
385 fields
[0].check_mask
= NULL
;
387 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
388 fields
[1].num_bits
= 7;
389 fields
[1].out_value
= malloc(1);
390 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
391 fields
[1].in_value
= NULL
;
392 fields
[1].check_value
= NULL
;
393 fields
[1].check_mask
= NULL
;
395 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
396 fields
[2].num_bits
= 1;
397 fields
[2].out_value
= malloc(1);
398 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
399 fields
[2].in_value
= NULL
;
400 fields
[2].check_value
= NULL
;
401 fields
[2].check_mask
= NULL
;
403 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
405 fields
[0].in_value
= reg
->value
;
406 fields
[0].check_value
= check_value
;
407 fields
[0].check_mask
= check_mask
;
409 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
411 free(fields
[1].out_value
);
412 free(fields
[2].out_value
);
417 static int etm_set_reg(reg_t
*reg
, uint32_t value
)
421 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
423 LOG_ERROR("BUG: error scheduling etm register write");
427 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
434 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
438 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
440 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
442 LOG_ERROR("register write failed");
448 static int etm_write_reg(reg_t
*reg
, uint32_t value
)
450 etm_reg_t
*etm_reg
= reg
->arch_info
;
451 uint8_t reg_addr
= etm_reg
->addr
& 0x7f;
452 scan_field_t fields
[3];
454 LOG_DEBUG("%i: 0x%8.8" PRIx32
"", etm_reg
->addr
, value
);
456 jtag_set_end_state(TAP_IDLE
);
457 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
458 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
460 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
461 fields
[0].num_bits
= 32;
463 fields
[0].out_value
= tmp1
;
464 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
465 fields
[0].in_value
= NULL
;
467 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
468 fields
[1].num_bits
= 7;
470 fields
[1].out_value
= &tmp2
;
471 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
472 fields
[1].in_value
= NULL
;
474 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
475 fields
[2].num_bits
= 1;
477 fields
[2].out_value
= &tmp3
;
478 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
479 fields
[2].in_value
= NULL
;
481 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
487 /* ETM trace analysis functionality
490 extern etm_capture_driver_t etm_dummy_capture_driver
;
491 #if BUILD_OOCD_TRACE == 1
492 extern etm_capture_driver_t oocd_trace_capture_driver
;
495 static etm_capture_driver_t
*etm_capture_drivers
[] =
498 &etm_dummy_capture_driver
,
499 #if BUILD_OOCD_TRACE == 1
500 &oocd_trace_capture_driver
,
505 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
514 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
516 /* search for the section the current instruction belongs to */
517 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
519 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
520 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
529 /* current instruction couldn't be found in the image */
530 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
533 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
536 if ((retval
= image_read_section(ctx
->image
, section
,
537 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
538 4, buf
, &size_read
)) != ERROR_OK
)
540 LOG_ERROR("error while reading instruction: %i", retval
);
541 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
543 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
544 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
546 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
549 if ((retval
= image_read_section(ctx
->image
, section
,
550 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
551 2, buf
, &size_read
)) != ERROR_OK
)
553 LOG_ERROR("error while reading instruction: %i", retval
);
554 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
556 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
557 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
559 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
561 LOG_ERROR("BUG: tracing of jazelle code not supported");
566 LOG_ERROR("BUG: unknown core state encountered");
573 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
575 while (ctx
->data_index
< ctx
->trace_depth
)
577 /* if the caller specified an address packet offset, skip until the
578 * we reach the n-th cycle marked with tracesync */
581 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
592 /* no tracedata output during a TD cycle
593 * or in a trigger cycle */
594 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
595 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
602 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
604 if (ctx
->data_half
== 0)
606 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
611 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
616 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
618 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
623 /* on a 4-bit port, a packet will be output during two consecutive cycles */
624 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
627 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
628 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
629 ctx
->data_index
+= 2;
638 static int etmv1_branch_address(etm_context_t
*ctx
)
646 /* quit analysis if less than two cycles are left in the trace
647 * because we can't extract the APO */
648 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
651 /* a BE could be output during an APO cycle, skip the current
652 * and continue with the new one */
653 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
655 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
658 /* address packet offset encoded in the next two cycles' pipestat bits */
659 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
660 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
662 /* count number of tracesync cycles between current pipe_index and data_index
663 * i.e. the number of tracesyncs that data_index already passed by
664 * to subtract them from the APO */
665 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
667 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
671 /* extract up to four 7-bit packets */
673 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
675 ctx
->last_branch
&= ~(0x7f << shift
);
676 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
678 } while ((packet
& 0x80) && (shift
< 28));
680 /* one last packet holding 4 bits of the address, plus the branch reason code */
681 if ((shift
== 28) && (packet
& 0x80))
683 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
685 ctx
->last_branch
&= 0x0fffffff;
686 ctx
->last_branch
|= (packet
& 0x0f) << 28;
687 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
692 ctx
->last_branch_reason
= 0;
700 /* if a full address was output, we might have branched into Jazelle state */
701 if ((shift
== 32) && (packet
& 0x80))
703 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
707 /* if we didn't branch into Jazelle state, the current processor state is
708 * encoded in bit 0 of the branch target address */
709 if (ctx
->last_branch
& 0x1)
711 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
712 ctx
->last_branch
&= ~0x1;
716 ctx
->core_state
= ARMV4_5_STATE_ARM
;
717 ctx
->last_branch
&= ~0x3;
724 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
730 for (j
= 0; j
< size
; j
++)
732 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
738 LOG_ERROR("TODO: add support for 64-bit values");
742 *data
= target_buffer_get_u32(ctx
->target
, buf
);
744 *data
= target_buffer_get_u16(ctx
->target
, buf
);
753 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
756 arm_instruction_t instruction
;
758 /* read the trace data if it wasn't read already */
759 if (ctx
->trace_depth
== 0)
760 ctx
->capture_driver
->read_trace(ctx
);
762 /* start at the beginning of the captured trace */
767 /* neither the PC nor the data pointer are valid */
771 while (ctx
->pipe_index
< ctx
->trace_depth
)
773 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
774 uint32_t next_pc
= ctx
->current_pc
;
775 uint32_t old_data_index
= ctx
->data_index
;
776 uint32_t old_data_half
= ctx
->data_half
;
777 uint32_t old_index
= ctx
->pipe_index
;
778 uint32_t last_instruction
= ctx
->last_instruction
;
780 int current_pc_ok
= ctx
->pc_ok
;
782 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
784 command_print(cmd_ctx
, "--- trigger ---");
787 /* instructions execute in IE/D or BE/D cycles */
788 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
789 ctx
->last_instruction
= ctx
->pipe_index
;
791 /* if we don't have a valid pc skip until we reach an indirect branch */
792 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
798 /* any indirect branch could have interrupted instruction flow
799 * - the branch reason code could indicate a trace discontinuity
800 * - a branch to the exception vectors indicates an exception
802 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
804 /* backup current data index, to be able to consume the branch address
805 * before examining data address and values
807 old_data_index
= ctx
->data_index
;
808 old_data_half
= ctx
->data_half
;
810 ctx
->last_instruction
= ctx
->pipe_index
;
812 if ((retval
= etmv1_branch_address(ctx
)) != 0)
814 /* negative return value from etmv1_branch_address means we ran out of packets,
815 * quit analysing the trace */
819 /* a positive return values means the current branch was abandoned,
820 * and a new branch was encountered in cycle ctx->pipe_index + retval;
822 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
823 ctx
->pipe_index
+= retval
;
827 /* skip over APO cycles */
828 ctx
->pipe_index
+= 2;
830 switch (ctx
->last_branch_reason
)
832 case 0x0: /* normal PC change */
833 next_pc
= ctx
->last_branch
;
835 case 0x1: /* tracing enabled */
836 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
837 ctx
->current_pc
= ctx
->last_branch
;
841 case 0x2: /* trace restarted after FIFO overflow */
842 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
843 ctx
->current_pc
= ctx
->last_branch
;
847 case 0x3: /* exit from debug state */
848 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
849 ctx
->current_pc
= ctx
->last_branch
;
853 case 0x4: /* periodic synchronization point */
854 next_pc
= ctx
->last_branch
;
855 /* if we had no valid PC prior to this synchronization point,
856 * we have to move on with the next trace cycle
860 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
861 ctx
->current_pc
= next_pc
;
866 default: /* reserved */
867 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
872 /* if we got here the branch was a normal PC change
873 * (or a periodic synchronization point, which means the same for that matter)
874 * if we didn't accquire a complete PC continue with the next cycle
879 /* indirect branch to the exception vector means an exception occured */
880 if ((ctx
->last_branch
<= 0x20)
881 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
883 if ((ctx
->last_branch
& 0xff) == 0x10)
885 command_print(cmd_ctx
, "data abort");
889 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
890 ctx
->current_pc
= ctx
->last_branch
;
897 /* an instruction was executed (or not, depending on the condition flags)
898 * retrieve it from the image for displaying */
899 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
900 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
901 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
903 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
905 /* can't continue tracing with no image available */
906 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
910 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
912 /* TODO: handle incomplete images
913 * for now we just quit the analsysis*/
918 cycles
= old_index
- last_instruction
;
921 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
923 uint32_t new_data_index
= ctx
->data_index
;
924 uint32_t new_data_half
= ctx
->data_half
;
926 /* in case of a branch with data, the branch target address was consumed before
927 * we temporarily go back to the saved data index */
928 if (pipestat
== STAT_BD
)
930 ctx
->data_index
= old_data_index
;
931 ctx
->data_half
= old_data_half
;
934 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
940 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
941 return ERROR_ETM_ANALYSIS_FAILED
;
942 ctx
->last_ptr
&= ~(0x7f << shift
);
943 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
945 } while ((packet
& 0x80) && (shift
< 32));
952 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
956 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
958 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
961 for (i
= 0; i
< 16; i
++)
963 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
966 if (etmv1_data(ctx
, 4, &data
) != 0)
967 return ERROR_ETM_ANALYSIS_FAILED
;
968 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
972 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
975 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
976 return ERROR_ETM_ANALYSIS_FAILED
;
977 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
981 /* restore data index after consuming BD address and data */
982 if (pipestat
== STAT_BD
)
984 ctx
->data_index
= new_data_index
;
985 ctx
->data_half
= new_data_half
;
990 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
992 if (((instruction
.type
== ARM_B
) ||
993 (instruction
.type
== ARM_BL
) ||
994 (instruction
.type
== ARM_BLX
)) &&
995 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
997 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1001 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1004 else if (pipestat
== STAT_IN
)
1006 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1009 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1011 char cycles_text
[32] = "";
1013 /* if the trace was captured with cycle accurate tracing enabled,
1014 * output the number of cycles since the last executed instruction
1016 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1018 snprintf(cycles_text
, 32, " (%i %s)",
1020 (cycles
== 1) ? "cycle" : "cycles");
1023 command_print(cmd_ctx
, "%s%s%s",
1025 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1028 ctx
->current_pc
= next_pc
;
1030 /* packets for an instruction don't start on or before the preceding
1031 * functional pipestat (i.e. other than WT or TD)
1033 if (ctx
->data_index
<= ctx
->pipe_index
)
1035 ctx
->data_index
= ctx
->pipe_index
+ 1;
1040 ctx
->pipe_index
+= 1;
1046 static int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1049 armv4_5_common_t
*armv4_5
;
1050 arm7_9_common_t
*arm7_9
;
1051 etmv1_tracemode_t tracemode
;
1053 target
= get_current_target(cmd_ctx
);
1055 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1057 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1061 if (!arm7_9
->etm_ctx
)
1063 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1067 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1071 if (strcmp(args
[0], "none") == 0)
1073 tracemode
= ETMV1_TRACE_NONE
;
1075 else if (strcmp(args
[0], "data") == 0)
1077 tracemode
= ETMV1_TRACE_DATA
;
1079 else if (strcmp(args
[0], "address") == 0)
1081 tracemode
= ETMV1_TRACE_ADDR
;
1083 else if (strcmp(args
[0], "all") == 0)
1085 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1089 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1093 switch (strtol(args
[1], NULL
, 0))
1096 tracemode
|= ETMV1_CONTEXTID_NONE
;
1099 tracemode
|= ETMV1_CONTEXTID_8
;
1102 tracemode
|= ETMV1_CONTEXTID_16
;
1105 tracemode
|= ETMV1_CONTEXTID_32
;
1108 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1112 if (strcmp(args
[2], "enable") == 0)
1114 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1116 else if (strcmp(args
[2], "disable") == 0)
1122 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1126 if (strcmp(args
[3], "enable") == 0)
1128 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1130 else if (strcmp(args
[3], "disable") == 0)
1136 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1142 command_print(cmd_ctx
, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1146 command_print(cmd_ctx
, "current tracemode configuration:");
1148 switch (tracemode
& ETMV1_TRACE_MASK
)
1150 case ETMV1_TRACE_NONE
:
1151 command_print(cmd_ctx
, "data tracing: none");
1153 case ETMV1_TRACE_DATA
:
1154 command_print(cmd_ctx
, "data tracing: data only");
1156 case ETMV1_TRACE_ADDR
:
1157 command_print(cmd_ctx
, "data tracing: address only");
1159 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1160 command_print(cmd_ctx
, "data tracing: address and data");
1164 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1166 case ETMV1_CONTEXTID_NONE
:
1167 command_print(cmd_ctx
, "contextid tracing: none");
1169 case ETMV1_CONTEXTID_8
:
1170 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1172 case ETMV1_CONTEXTID_16
:
1173 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1175 case ETMV1_CONTEXTID_32
:
1176 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1180 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1182 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1186 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1189 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1191 command_print(cmd_ctx
, "full branch address output enabled");
1195 command_print(cmd_ctx
, "full branch address output disabled");
1198 /* only update ETM_CTRL register if tracemode changed */
1199 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1201 reg_t
*etm_ctrl_reg
;
1203 etm_ctrl_reg
= etm_reg_lookup(arm7_9
->etm_ctx
, ETM_CTRL
);
1207 etm_get_reg(etm_ctrl_reg
);
1209 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1210 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1211 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1212 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1213 etm_store_reg(etm_ctrl_reg
);
1215 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1217 /* invalidate old trace data */
1218 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1219 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1221 free(arm7_9
->etm_ctx
->trace_data
);
1222 arm7_9
->etm_ctx
->trace_data
= NULL
;
1224 arm7_9
->etm_ctx
->trace_depth
= 0;
1230 static int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1233 armv4_5_common_t
*armv4_5
;
1234 arm7_9_common_t
*arm7_9
;
1235 etm_portmode_t portmode
= 0x0;
1236 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1242 return ERROR_COMMAND_SYNTAX_ERROR
;
1245 target
= get_target(args
[0]);
1248 LOG_ERROR("target '%s' not defined", args
[0]);
1253 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1255 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1260 switch (strtoul(args
[1], NULL
, 0))
1263 portmode
|= ETM_PORT_4BIT
;
1266 portmode
|= ETM_PORT_8BIT
;
1269 portmode
|= ETM_PORT_16BIT
;
1272 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1277 if (strcmp("normal", args
[2]) == 0)
1279 portmode
|= ETM_PORT_NORMAL
;
1281 else if (strcmp("multiplexed", args
[2]) == 0)
1283 portmode
|= ETM_PORT_MUXED
;
1285 else if (strcmp("demultiplexed", args
[2]) == 0)
1287 portmode
|= ETM_PORT_DEMUXED
;
1291 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1296 if (strcmp("half", args
[3]) == 0)
1298 portmode
|= ETM_PORT_HALF_CLOCK
;
1300 else if (strcmp("full", args
[3]) == 0)
1302 portmode
|= ETM_PORT_FULL_CLOCK
;
1306 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1311 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1313 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1316 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1322 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1328 if (!etm_capture_drivers
[i
])
1330 /* no supported capture driver found, don't register an ETM */
1332 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1336 etm_ctx
->target
= target
;
1337 etm_ctx
->trigger_percent
= 50;
1338 etm_ctx
->trace_data
= NULL
;
1339 etm_ctx
->trace_depth
= 0;
1340 etm_ctx
->portmode
= portmode
;
1341 etm_ctx
->tracemode
= 0x0;
1342 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1343 etm_ctx
->image
= NULL
;
1344 etm_ctx
->pipe_index
= 0;
1345 etm_ctx
->data_index
= 0;
1346 etm_ctx
->current_pc
= 0x0;
1348 etm_ctx
->last_branch
= 0x0;
1349 etm_ctx
->last_branch_reason
= 0x0;
1350 etm_ctx
->last_ptr
= 0x0;
1351 etm_ctx
->ptr_ok
= 0x0;
1352 etm_ctx
->last_instruction
= 0;
1354 arm7_9
->etm_ctx
= etm_ctx
;
1356 return etm_register_user_commands(cmd_ctx
);
1359 static int handle_etm_info_command(struct command_context_s
*cmd_ctx
,
1360 char *cmd
, char **args
, int argc
)
1363 armv4_5_common_t
*armv4_5
;
1364 arm7_9_common_t
*arm7_9
;
1365 reg_t
*etm_config_reg
;
1366 reg_t
*etm_sys_config_reg
;
1370 target
= get_current_target(cmd_ctx
);
1372 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1374 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1378 if (!arm7_9
->etm_ctx
)
1380 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1384 etm_config_reg
= etm_reg_lookup(arm7_9
->etm_ctx
, ETM_CONFIG
);
1385 if (!etm_config_reg
)
1387 etm_sys_config_reg
= etm_reg_lookup(arm7_9
->etm_ctx
, ETM_SYS_CONFIG
);
1388 if (!etm_sys_config_reg
)
1391 etm_get_reg(etm_config_reg
);
1392 command_print(cmd_ctx
, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg
->value
, 0, 4));
1393 command_print(cmd_ctx
, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg
->value
, 4, 4));
1394 command_print(cmd_ctx
, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg
->value
, 8, 5));
1395 command_print(cmd_ctx
, "number of counters: %i", (int)buf_get_u32(etm_config_reg
->value
, 13, 3));
1396 command_print(cmd_ctx
, "sequencer %spresent",
1397 (buf_get_u32(etm_config_reg
->value
, 16, 1) == 1) ? "" : "not ");
1398 command_print(cmd_ctx
, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg
->value
, 17, 3));
1399 command_print(cmd_ctx
, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg
->value
, 20, 3));
1400 command_print(cmd_ctx
, "FIFO full %spresent",
1401 (buf_get_u32(etm_config_reg
->value
, 23, 1) == 1) ? "" : "not ");
1402 command_print(cmd_ctx
, "protocol version: %i", (int)buf_get_u32(etm_config_reg
->value
, 28, 3));
1404 etm_get_reg(etm_sys_config_reg
);
1406 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1418 LOG_ERROR("Illegal max_port_size");
1421 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1423 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1424 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1425 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1426 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1427 command_print(cmd_ctx
, "normal trace format %ssupported",
1428 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1429 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1430 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1431 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1432 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1433 command_print(cmd_ctx
, "FIFO full %ssupported",
1434 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1439 static int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1442 armv4_5_common_t
*armv4_5
;
1443 arm7_9_common_t
*arm7_9
;
1444 trace_status_t trace_status
;
1446 target
= get_current_target(cmd_ctx
);
1448 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1450 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1454 if (!arm7_9
->etm_ctx
)
1456 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1460 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1462 if (trace_status
== TRACE_IDLE
)
1464 command_print(cmd_ctx
, "tracing is idle");
1468 static char *completed
= " completed";
1469 static char *running
= " is running";
1470 static char *overflowed
= ", trace overflowed";
1471 static char *triggered
= ", trace triggered";
1473 command_print(cmd_ctx
, "trace collection%s%s%s",
1474 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1475 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1476 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1478 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1480 command_print(cmd_ctx
, "%i frames of trace data read", (int)(arm7_9
->etm_ctx
->trace_depth
));
1487 static int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1490 armv4_5_common_t
*armv4_5
;
1491 arm7_9_common_t
*arm7_9
;
1492 etm_context_t
*etm_ctx
;
1496 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1500 target
= get_current_target(cmd_ctx
);
1502 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1504 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1508 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1510 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1516 image_close(etm_ctx
->image
);
1517 free(etm_ctx
->image
);
1518 command_print(cmd_ctx
, "previously loaded image found and closed");
1521 etm_ctx
->image
= malloc(sizeof(image_t
));
1522 etm_ctx
->image
->base_address_set
= 0;
1523 etm_ctx
->image
->start_address_set
= 0;
1525 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1528 etm_ctx
->image
->base_address_set
= 1;
1529 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1533 etm_ctx
->image
->base_address_set
= 0;
1536 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1538 free(etm_ctx
->image
);
1539 etm_ctx
->image
= NULL
;
1546 static int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1550 armv4_5_common_t
*armv4_5
;
1551 arm7_9_common_t
*arm7_9
;
1552 etm_context_t
*etm_ctx
;
1557 command_print(cmd_ctx
, "usage: etm dump <file>");
1561 target
= get_current_target(cmd_ctx
);
1563 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1565 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1569 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1571 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1575 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1577 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1581 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1583 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1584 command_print(cmd_ctx
, "trace capture not completed");
1588 /* read the trace data if it wasn't read already */
1589 if (etm_ctx
->trace_depth
== 0)
1590 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1592 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1597 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1598 fileio_write_u32(&file
, etm_ctx
->portmode
);
1599 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1600 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1602 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1604 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1605 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1606 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1609 fileio_close(&file
);
1614 static int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1618 armv4_5_common_t
*armv4_5
;
1619 arm7_9_common_t
*arm7_9
;
1620 etm_context_t
*etm_ctx
;
1625 command_print(cmd_ctx
, "usage: etm load <file>");
1629 target
= get_current_target(cmd_ctx
);
1631 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1633 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1637 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1639 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1643 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1645 command_print(cmd_ctx
, "trace capture running, stop first");
1649 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1656 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1657 fileio_close(&file
);
1661 if (etm_ctx
->trace_depth
> 0)
1663 free(etm_ctx
->trace_data
);
1664 etm_ctx
->trace_data
= NULL
;
1669 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1670 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1671 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1672 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1674 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1675 if (etm_ctx
->trace_data
== NULL
)
1677 command_print(cmd_ctx
, "not enough memory to perform operation");
1678 fileio_close(&file
);
1682 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1684 uint32_t pipestat
, packet
, flags
;
1685 fileio_read_u32(&file
, &pipestat
);
1686 fileio_read_u32(&file
, &packet
);
1687 fileio_read_u32(&file
, &flags
);
1688 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1689 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1690 etm_ctx
->trace_data
[i
].flags
= flags
;
1693 fileio_close(&file
);
1698 static int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1701 armv4_5_common_t
*armv4_5
;
1702 arm7_9_common_t
*arm7_9
;
1703 etm_context_t
*etm_ctx
;
1705 target
= get_current_target(cmd_ctx
);
1707 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1709 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1713 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1715 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1721 uint32_t new_value
= strtoul(args
[0], NULL
, 0);
1723 if ((new_value
< 2) || (new_value
> 100))
1725 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1729 etm_ctx
->trigger_percent
= new_value
;
1733 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1738 static int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1741 armv4_5_common_t
*armv4_5
;
1742 arm7_9_common_t
*arm7_9
;
1743 etm_context_t
*etm_ctx
;
1744 reg_t
*etm_ctrl_reg
;
1746 target
= get_current_target(cmd_ctx
);
1748 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1750 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1754 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1756 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1760 /* invalidate old tracing data */
1761 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1762 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1764 free(arm7_9
->etm_ctx
->trace_data
);
1765 arm7_9
->etm_ctx
->trace_data
= NULL
;
1767 arm7_9
->etm_ctx
->trace_depth
= 0;
1769 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1773 etm_get_reg(etm_ctrl_reg
);
1775 /* Clear programming bit (10), set port selection bit (11) */
1776 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1778 etm_store_reg(etm_ctrl_reg
);
1779 jtag_execute_queue();
1781 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1786 static int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1789 armv4_5_common_t
*armv4_5
;
1790 arm7_9_common_t
*arm7_9
;
1791 etm_context_t
*etm_ctx
;
1792 reg_t
*etm_ctrl_reg
;
1794 target
= get_current_target(cmd_ctx
);
1796 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1798 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1802 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1804 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1808 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1812 etm_get_reg(etm_ctrl_reg
);
1814 /* Set programming bit (10), clear port selection bit (11) */
1815 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1817 etm_store_reg(etm_ctrl_reg
);
1818 jtag_execute_queue();
1820 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1825 static int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1828 armv4_5_common_t
*armv4_5
;
1829 arm7_9_common_t
*arm7_9
;
1830 etm_context_t
*etm_ctx
;
1833 target
= get_current_target(cmd_ctx
);
1835 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1837 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1841 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1843 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1847 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
1851 case ERROR_ETM_ANALYSIS_FAILED
:
1852 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
1854 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1855 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
1857 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
1858 command_print(cmd_ctx
, "no image available for trace analysis");
1861 command_print(cmd_ctx
, "unknown error: %i", retval
);
1868 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1870 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1872 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
1873 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1878 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
1880 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
1881 COMMAND_EXEC
, "configure/display trace mode: "
1882 "<none | data | address | all> "
1883 "<context_id_bits> <cycle_accurate> <branch_output>");
1885 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
1886 COMMAND_EXEC
, "display info about the current target's ETM");
1888 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
1889 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1890 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
1891 COMMAND_EXEC
, "display current target's ETM status");
1892 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
1893 COMMAND_EXEC
, "start ETM trace collection");
1894 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
1895 COMMAND_EXEC
, "stop ETM trace collection");
1897 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
1898 COMMAND_EXEC
, "anaylze collected ETM trace");
1900 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
1901 COMMAND_EXEC
, "load image from <file> [base address]");
1903 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
1904 COMMAND_EXEC
, "dump captured trace data <file>");
1905 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
1906 COMMAND_EXEC
, "load trace data for analysis <file>");
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