1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007 by Vincent Palatin *
6 * vincent.palatin_openocd@m4x.org *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
32 /* ETM registers (JTAG protocol) */
37 ETM_TRIG_EVENT
= 0x02,
40 ETM_SYS_CONFIG
= 0x05,
41 ETM_TRACE_RESOURCE_CTRL
= 0x06,
42 ETM_TRACE_EN_CTRL2
= 0x07,
43 ETM_TRACE_EN_EVENT
= 0x08,
44 ETM_TRACE_EN_CTRL1
= 0x09,
45 /* optional FIFOFULL */
46 ETM_FIFOFULL_REGION
= 0x0a,
47 ETM_FIFOFULL_LEVEL
= 0x0b,
48 /* viewdata support */
49 ETM_VIEWDATA_EVENT
= 0x0c,
50 ETM_VIEWDATA_CTRL1
= 0x0d,
51 ETM_VIEWDATA_CTRL2
= 0x0e, /* optional */
52 ETM_VIEWDATA_CTRL3
= 0x0f,
53 /* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
54 ETM_ADDR_COMPARATOR_VALUE
= 0x10,
55 ETM_ADDR_ACCESS_TYPE
= 0x20,
56 /* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
57 ETM_DATA_COMPARATOR_VALUE
= 0x30,
58 ETM_DATA_COMPARATOR_MASK
= 0x40,
59 /* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
60 ETM_COUNTER_RELOAD_VALUE
= 0x50,
61 ETM_COUNTER_ENABLE
= 0x54,
62 ETM_COUNTER_RELOAD_EVENT
= 0x58,
63 ETM_COUNTER_VALUE
= 0x5c,
64 /* 6 sequencer event transitions */
65 ETM_SEQUENCER_EVENT
= 0x60,
66 ETM_SEQUENCER_STATE
= 0x67,
67 /* N triggered outputs */
68 ETM_EXTERNAL_OUTPUT
= 0x68,
70 ETM_CONTEXTID_COMPARATOR_VALUE
= 0x6c,
71 ETM_CONTEXTID_COMPARATOR_MASK
= 0x6f,
74 typedef struct etm_reg_s
77 const struct etm_reg_info
*reg_info
;
78 arm_jtag_t
*jtag_info
;
86 ETM_PORT_16BIT
= 0x20,
87 ETM_PORT_WIDTH_MASK
= 0x70,
89 ETM_PORT_NORMAL
= 0x00000,
90 ETM_PORT_MUXED
= 0x10000,
91 ETM_PORT_DEMUXED
= 0x20000,
92 ETM_PORT_MODE_MASK
= 0x30000,
94 ETM_PORT_FULL_CLOCK
= 0x0000,
95 ETM_PORT_HALF_CLOCK
= 0x1000,
96 ETM_PORT_CLOCK_MASK
= 0x1000,
102 ETMV1_TRACE_NONE
= 0x00,
103 ETMV1_TRACE_DATA
= 0x01,
104 ETMV1_TRACE_ADDR
= 0x02,
105 ETMV1_TRACE_MASK
= 0x03,
107 ETMV1_CONTEXTID_NONE
= 0x00,
108 ETMV1_CONTEXTID_8
= 0x10,
109 ETMV1_CONTEXTID_16
= 0x20,
110 ETMV1_CONTEXTID_32
= 0x30,
111 ETMV1_CONTEXTID_MASK
= 0x30,
113 ETMV1_CYCLE_ACCURATE
= 0x100,
114 ETMV1_BRANCH_OUTPUT
= 0x200
117 /* forward-declare ETM context */
120 typedef struct etm_capture_driver_s
123 int (*register_commands
)(struct command_context_s
*cmd_ctx
);
124 int (*init
)(struct etm
*etm_ctx
);
125 trace_status_t (*status
)(struct etm
*etm_ctx
);
126 int (*read_trace
)(struct etm
*etm_ctx
);
127 int (*start_capture
)(struct etm
*etm_ctx
);
128 int (*stop_capture
)(struct etm
*etm_ctx
);
129 } etm_capture_driver_t
;
133 ETMV1_TRACESYNC_CYCLE
= 0x1,
134 ETMV1_TRIGGER_CYCLE
= 0x2,
137 typedef struct etmv1_trace_data_s
139 uint8_t pipestat
; /* bits 0-2 pipeline status */
140 uint16_t packet
; /* packet data (4, 8 or 16 bit) */
141 int flags
; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
142 } etmv1_trace_data_t
;
144 /* describe a trace context
145 * if support for ETMv2 or ETMv3 is to be implemented,
146 * this will have to be split into version independent elements
147 * and a version specific part
151 target_t
*target
; /* target this ETM is connected to */
152 reg_cache_t
*reg_cache
; /* ETM register cache */
153 etm_capture_driver_t
*capture_driver
; /* driver used to access ETM data */
154 void *capture_driver_priv
; /* capture driver private data */
155 uint32_t trigger_percent
; /* how much trace buffer to fill after trigger */
156 trace_status_t capture_status
; /* current state of capture run */
157 etmv1_trace_data_t
*trace_data
; /* trace data */
158 uint32_t trace_depth
; /* number of cycles to be analyzed, 0 if no data available */
159 etm_portmode_t portmode
; /* normal, multiplexed or demultiplexed */
160 etmv1_tracemode_t tracemode
; /* type of info trace contains */
161 armv4_5_state_t core_state
; /* current core state */
162 struct image_s
*image
; /* source for target opcodes */
163 uint32_t pipe_index
; /* current trace cycle */
164 uint32_t data_index
; /* cycle holding next data packet */
165 bool data_half
; /* port half on a 16 bit port */
166 bool pc_ok
; /* full PC has been acquired */
167 bool ptr_ok
; /* whether last_ptr is valid */
168 uint8_t bcd_vers
; /* e.g. 0x13 == ETMv1.3 */
169 uint32_t config
; /* cache of ETM_CONFIG value */
170 uint32_t current_pc
; /* current program counter */
171 uint32_t last_branch
; /* last branch address output */
172 uint32_t last_branch_reason
; /* type of last branch encountered */
173 uint32_t last_ptr
; /* address of the last data access */
174 uint32_t last_instruction
; /* index of last executed (to calc timings) */
177 /* PIPESTAT values */
190 /* branch reason values */
193 BR_NORMAL
= 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
194 BR_ENABLE
= 0x1, /* Trace has been enabled */
195 BR_RESTART
= 0x2, /* Trace restarted after a FIFO overflow */
196 BR_NODEBUG
= 0x3, /* ARM has exited for debug state */
197 BR_PERIOD
= 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
198 BR_RSVD5
= 0x5, /* reserved */
199 BR_RSVD6
= 0x6, /* reserved */
200 BR_RSVD7
= 0x7, /* reserved */
201 } etmv1_branch_reason_t
;
203 reg_cache_t
* etm_build_reg_cache(target_t
*target
,
204 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
);
206 int etm_setup(target_t
*target
);
208 int etm_register_commands(struct command_context_s
*cmd_ctx
);
210 #define ERROR_ETM_INVALID_DRIVER (-1300)
211 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
212 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
213 #define ERROR_ETM_ANALYSIS_FAILED (-1303)
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