1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * Mathias Kuester <kesmtp@freenet.de> *
5 * Copyright (C) 2011 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * revised: 4/25/13 by brent@mbari.org [DCC target request support] *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ***************************************************************************/
30 #include "jtag/jtag.h"
31 #include "jtag/hla/hla_transport.h"
32 #include "jtag/hla/hla_interface.h"
33 #include "jtag/hla/hla_layout.h"
35 #include "algorithm.h"
37 #include "breakpoints.h"
38 #include "target_type.h"
41 #include "arm_semihosting.h"
42 #include "target_request.h"
44 #define savedDCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */
46 #define ARMV7M_SCS_DCRSR DCB_DCRSR
47 #define ARMV7M_SCS_DCRDR DCB_DCRDR
49 static inline struct hl_interface_s
*target_to_adapter(struct target
*target
)
51 return target
->tap
->priv
;
54 static int adapter_load_core_reg_u32(struct target
*target
,
55 uint32_t num
, uint32_t *value
)
58 struct hl_interface_s
*adapter
= target_to_adapter(target
);
60 LOG_DEBUG("%s", __func__
);
62 /* NOTE: we "know" here that the register identifiers used
63 * in the v7m header match the Cortex-M3 Debug Core Register
64 * Selector values for R0..R15, xPSR, MSP, and PSP.
68 /* read a normal core register */
69 retval
= adapter
->layout
->api
->read_reg(adapter
->handle
, num
, value
);
71 if (retval
!= ERROR_OK
) {
72 LOG_ERROR("JTAG failure %i", retval
);
73 return ERROR_JTAG_DEVICE_ERROR
;
75 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
79 /* Floating-point Status and Registers */
80 retval
= target_write_u32(target
, ARMV7M_SCS_DCRSR
, 33);
81 if (retval
!= ERROR_OK
)
83 retval
= target_read_u32(target
, ARMV7M_SCS_DCRDR
, value
);
84 if (retval
!= ERROR_OK
)
86 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
89 case ARMV7M_S0
... ARMV7M_S31
:
90 /* Floating-point Status and Registers */
91 retval
= target_write_u32(target
, ARMV7M_SCS_DCRSR
, num
-ARMV7M_S0
+64);
92 if (retval
!= ERROR_OK
)
94 retval
= target_read_u32(target
, ARMV7M_SCS_DCRDR
, value
);
95 if (retval
!= ERROR_OK
)
97 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
98 (int)(num
- ARMV7M_S0
), *value
);
103 case ARMV7M_FAULTMASK
:
105 /* Cortex-M3 packages these four registers as bitfields
106 * in one Debug Core register. So say r0 and r2 docs;
107 * it was removed from r1 docs, but still works.
109 retval
= adapter
->layout
->api
->read_reg(adapter
->handle
, 20, value
);
110 if (retval
!= ERROR_OK
)
115 *value
= buf_get_u32((uint8_t *) value
, 0, 1);
119 *value
= buf_get_u32((uint8_t *) value
, 8, 8);
122 case ARMV7M_FAULTMASK
:
123 *value
= buf_get_u32((uint8_t *) value
, 16, 1);
127 *value
= buf_get_u32((uint8_t *) value
, 24, 2);
131 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"",
136 return ERROR_COMMAND_SYNTAX_ERROR
;
142 static int adapter_store_core_reg_u32(struct target
*target
,
143 uint32_t num
, uint32_t value
)
147 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
148 struct hl_interface_s
*adapter
= target_to_adapter(target
);
150 LOG_DEBUG("%s", __func__
);
152 /* NOTE: we "know" here that the register identifiers used
153 * in the v7m header match the Cortex-M3 Debug Core Register
154 * Selector values for R0..R15, xPSR, MSP, and PSP.
158 retval
= adapter
->layout
->api
->write_reg(adapter
->handle
, num
, value
);
160 if (retval
!= ERROR_OK
) {
163 LOG_ERROR("JTAG failure");
164 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
166 return ERROR_JTAG_DEVICE_ERROR
;
168 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
172 /* Floating-point Status and Registers */
173 retval
= target_write_u32(target
, ARMV7M_SCS_DCRDR
, value
);
174 if (retval
!= ERROR_OK
)
176 retval
= target_write_u32(target
, ARMV7M_SCS_DCRSR
, 33 | (1<<16));
177 if (retval
!= ERROR_OK
)
179 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
182 case ARMV7M_S0
... ARMV7M_S31
:
183 /* Floating-point Status and Registers */
184 retval
= target_write_u32(target
, ARMV7M_SCS_DCRDR
, value
);
185 if (retval
!= ERROR_OK
)
187 retval
= target_write_u32(target
, ARMV7M_SCS_DCRSR
, (num
-ARMV7M_S0
+64) | (1<<16));
188 if (retval
!= ERROR_OK
)
190 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
191 (int)(num
- ARMV7M_S0
), value
);
196 case ARMV7M_FAULTMASK
:
198 /* Cortex-M3 packages these four registers as bitfields
199 * in one Debug Core register. So say r0 and r2 docs;
200 * it was removed from r1 docs, but still works.
203 adapter
->layout
->api
->read_reg(adapter
->handle
, 20, ®
);
207 buf_set_u32((uint8_t *) ®
, 0, 1, value
);
211 buf_set_u32((uint8_t *) ®
, 8, 8, value
);
214 case ARMV7M_FAULTMASK
:
215 buf_set_u32((uint8_t *) ®
, 16, 1, value
);
219 buf_set_u32((uint8_t *) ®
, 24, 2, value
);
223 adapter
->layout
->api
->write_reg(adapter
->handle
, 20, reg
);
225 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
229 return ERROR_COMMAND_SYNTAX_ERROR
;
235 static int adapter_examine_debug_reason(struct target
*target
)
237 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
238 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
239 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
245 static int hl_dcc_read(struct hl_interface_s
*hl_if
, uint8_t *value
, uint8_t *ctrl
)
248 int retval
= hl_if
->layout
->api
->read_mem(hl_if
->handle
,
249 DCB_DCRDR
, 1, sizeof(dcrdr
), (uint8_t *)&dcrdr
);
250 if (retval
== ERROR_OK
) {
251 *ctrl
= (uint8_t)dcrdr
;
252 *value
= (uint8_t)(dcrdr
>> 8);
254 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
257 /* write ack back to software dcc register
258 * to signify we have read data */
259 /* atomically clear just the byte containing the busy bit */
260 static const uint8_t zero
;
261 retval
= hl_if
->layout
->api
->write_mem(hl_if
->handle
, DCB_DCRDR
, 1, 1, &zero
);
267 static int hl_target_request_data(struct target
*target
,
268 uint32_t size
, uint8_t *buffer
)
270 struct hl_interface_s
*hl_if
= target_to_adapter(target
);
275 for (i
= 0; i
< (size
* 4); i
++) {
276 hl_dcc_read(hl_if
, &data
, &ctrl
);
283 static int hl_handle_target_request(void *priv
)
285 struct target
*target
= priv
;
286 if (!target_was_examined(target
))
288 struct hl_interface_s
*hl_if
= target_to_adapter(target
);
290 if (!target
->dbg_msg_enabled
)
293 if (target
->state
== TARGET_RUNNING
) {
297 hl_dcc_read(hl_if
, &data
, &ctrl
);
299 /* check if we have data */
300 if (ctrl
& (1 << 0)) {
303 /* we assume target is quick enough */
305 hl_dcc_read(hl_if
, &data
, &ctrl
);
306 request
|= (data
<< 8);
307 hl_dcc_read(hl_if
, &data
, &ctrl
);
308 request
|= (data
<< 16);
309 hl_dcc_read(hl_if
, &data
, &ctrl
);
310 request
|= (data
<< 24);
311 target_request(target
, request
);
318 static int adapter_init_arch_info(struct target
*target
,
319 struct cortex_m_common
*cortex_m
,
320 struct jtag_tap
*tap
)
322 struct armv7m_common
*armv7m
;
324 LOG_DEBUG("%s", __func__
);
326 armv7m
= &cortex_m
->armv7m
;
327 armv7m_init_arch_info(target
, armv7m
);
329 armv7m
->load_core_reg_u32
= adapter_load_core_reg_u32
;
330 armv7m
->store_core_reg_u32
= adapter_store_core_reg_u32
;
332 armv7m
->examine_debug_reason
= adapter_examine_debug_reason
;
333 armv7m
->stlink
= true;
335 target_register_timer_callback(hl_handle_target_request
, 1, 1, target
);
340 static int adapter_init_target(struct command_context
*cmd_ctx
,
341 struct target
*target
)
343 LOG_DEBUG("%s", __func__
);
345 armv7m_build_reg_cache(target
);
350 static int adapter_target_create(struct target
*target
,
353 LOG_DEBUG("%s", __func__
);
355 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
358 return ERROR_COMMAND_SYNTAX_ERROR
;
360 adapter_init_arch_info(target
, cortex_m
, target
->tap
);
365 static int adapter_load_context(struct target
*target
)
367 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
368 int num_regs
= armv7m
->arm
.core_cache
->num_regs
;
370 for (int i
= 0; i
< num_regs
; i
++) {
372 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
374 armv7m
->arm
.read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
380 static int adapter_debug_entry(struct target
*target
)
382 struct hl_interface_s
*adapter
= target_to_adapter(target
);
383 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
384 struct arm
*arm
= &armv7m
->arm
;
389 /* preserve the DCRDR across halts */
390 retval
= target_read_u32(target
, DCB_DCRDR
, &target
->savedDCRDR
);
391 if (retval
!= ERROR_OK
)
394 retval
= armv7m
->examine_debug_reason(target
);
395 if (retval
!= ERROR_OK
)
398 adapter_load_context(target
);
400 /* make sure we clear the vector catch bit */
401 adapter
->layout
->api
->write_debug_reg(adapter
->handle
, DCB_DEMCR
, TRCENA
);
404 xPSR
= buf_get_u32(r
->value
, 0, 32);
406 /* Are we in an exception handler */
408 armv7m
->exception_number
= (xPSR
& 0x1FF);
410 arm
->core_mode
= ARM_MODE_HANDLER
;
411 arm
->map
= armv7m_msp_reg_map
;
413 unsigned control
= buf_get_u32(arm
->core_cache
414 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
416 /* is this thread privileged? */
417 arm
->core_mode
= control
& 1
418 ? ARM_MODE_USER_THREAD
421 /* which stack is it using? */
423 arm
->map
= armv7m_psp_reg_map
;
425 arm
->map
= armv7m_msp_reg_map
;
427 armv7m
->exception_number
= 0;
430 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32
", target->state: %s",
431 arm_mode_name(arm
->core_mode
),
432 buf_get_u32(arm
->pc
->value
, 0, 32),
433 target_state_name(target
));
438 static int adapter_poll(struct target
*target
)
440 enum target_state state
;
441 struct hl_interface_s
*adapter
= target_to_adapter(target
);
442 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
443 enum target_state prev_target_state
= target
->state
;
445 state
= adapter
->layout
->api
->state(adapter
->handle
);
447 if (state
== TARGET_UNKNOWN
) {
448 LOG_ERROR("jtag status contains invalid mode value - communication failure");
449 return ERROR_TARGET_FAILURE
;
452 if (prev_target_state
== state
)
455 target
->state
= state
;
457 if (state
== TARGET_HALTED
) {
459 int retval
= adapter_debug_entry(target
);
460 if (retval
!= ERROR_OK
)
463 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
464 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
466 if (arm_semihosting(target
, &retval
) != 0)
469 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
472 LOG_DEBUG("halted: PC: 0x%08" PRIx32
, buf_get_u32(armv7m
->arm
.pc
->value
, 0, 32));
478 static int adapter_assert_reset(struct target
*target
)
481 struct hl_interface_s
*adapter
= target_to_adapter(target
);
482 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
483 bool use_srst_fallback
= true;
485 LOG_DEBUG("%s", __func__
);
487 enum reset_types jtag_reset_config
= jtag_get_reset_config();
489 bool srst_asserted
= false;
491 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
492 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
493 jtag_add_reset(0, 1);
494 res
= adapter
->layout
->api
->assert_srst(adapter
->handle
, 0);
495 srst_asserted
= true;
498 adapter
->layout
->api
->write_debug_reg(adapter
->handle
, DCB_DHCSR
, DBGKEY
|C_DEBUGEN
);
500 /* only set vector catch if halt is requested */
501 if (target
->reset_halt
)
502 adapter
->layout
->api
->write_debug_reg(adapter
->handle
, DCB_DEMCR
, TRCENA
|VC_CORERESET
);
504 adapter
->layout
->api
->write_debug_reg(adapter
->handle
, DCB_DEMCR
, TRCENA
);
506 if (jtag_reset_config
& RESET_HAS_SRST
) {
507 if (!srst_asserted
) {
508 jtag_add_reset(0, 1);
509 res
= adapter
->layout
->api
->assert_srst(adapter
->handle
, 0);
511 if (res
== ERROR_COMMAND_NOTFOUND
)
512 LOG_ERROR("Hardware srst not supported, falling back to software reset");
513 else if (res
== ERROR_OK
) {
514 /* hardware srst supported */
515 use_srst_fallback
= false;
519 if (use_srst_fallback
) {
520 /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
521 adapter
->layout
->api
->write_debug_reg(adapter
->handle
, NVIC_AIRCR
, AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
524 res
= adapter
->layout
->api
->reset(adapter
->handle
);
529 /* registers are now invalid */
530 register_cache_invalidate(armv7m
->arm
.core_cache
);
532 if (target
->reset_halt
) {
533 target
->state
= TARGET_RESET
;
534 target
->debug_reason
= DBG_REASON_DBGRQ
;
536 target
->state
= TARGET_HALTED
;
542 static int adapter_deassert_reset(struct target
*target
)
544 struct hl_interface_s
*adapter
= target_to_adapter(target
);
546 enum reset_types jtag_reset_config
= jtag_get_reset_config();
548 LOG_DEBUG("%s", __func__
);
550 if (jtag_reset_config
& RESET_HAS_SRST
)
551 adapter
->layout
->api
->assert_srst(adapter
->handle
, 1);
553 /* virtual deassert reset, we need it for the internal
556 jtag_add_reset(0, 0);
558 target
->savedDCRDR
= 0; /* clear both DCC busy bits on initial resume */
560 return target
->reset_halt
? ERROR_OK
: target_resume(target
, 1, 0, 0, 0);
563 static int adapter_halt(struct target
*target
)
566 struct hl_interface_s
*adapter
= target_to_adapter(target
);
568 LOG_DEBUG("%s", __func__
);
570 if (target
->state
== TARGET_HALTED
) {
571 LOG_DEBUG("target was already halted");
575 if (target
->state
== TARGET_UNKNOWN
)
576 LOG_WARNING("target was in unknown state when halt was requested");
578 res
= adapter
->layout
->api
->halt(adapter
->handle
);
583 target
->debug_reason
= DBG_REASON_DBGRQ
;
588 static int adapter_resume(struct target
*target
, int current
,
589 uint32_t address
, int handle_breakpoints
,
593 struct hl_interface_s
*adapter
= target_to_adapter(target
);
594 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
596 struct breakpoint
*breakpoint
= NULL
;
599 LOG_DEBUG("%s %d 0x%08" PRIx32
" %d %d", __func__
, current
, address
,
600 handle_breakpoints
, debug_execution
);
602 if (target
->state
!= TARGET_HALTED
) {
603 LOG_WARNING("target not halted");
604 return ERROR_TARGET_NOT_HALTED
;
607 if (!debug_execution
) {
608 target_free_all_working_areas(target
);
609 cortex_m_enable_breakpoints(target
);
610 cortex_m_enable_watchpoints(target
);
615 buf_set_u32(pc
->value
, 0, 32, address
);
620 if (!breakpoint_find(target
, buf_get_u32(pc
->value
, 0, 32))
621 && !debug_execution
) {
622 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
625 resume_pc
= buf_get_u32(pc
->value
, 0, 32);
627 /* write any user vector flags */
628 res
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
632 armv7m_restore_context(target
);
634 /* restore savedDCRDR */
635 res
= target_write_u32(target
, DCB_DCRDR
, target
->savedDCRDR
);
639 /* registers are now invalid */
640 register_cache_invalidate(armv7m
->arm
.core_cache
);
642 /* the front-end may request us not to handle breakpoints */
643 if (handle_breakpoints
) {
644 /* Single step past breakpoint at current address */
645 breakpoint
= breakpoint_find(target
, resume_pc
);
647 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %" PRIu32
")",
649 breakpoint
->unique_id
);
650 cortex_m_unset_breakpoint(target
, breakpoint
);
652 res
= adapter
->layout
->api
->step(adapter
->handle
);
657 cortex_m_set_breakpoint(target
, breakpoint
);
661 res
= adapter
->layout
->api
->run(adapter
->handle
);
666 target
->debug_reason
= DBG_REASON_NOTHALTED
;
668 if (!debug_execution
) {
669 target
->state
= TARGET_RUNNING
;
670 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
672 target
->state
= TARGET_DEBUG_RUNNING
;
673 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
679 static int adapter_step(struct target
*target
, int current
,
680 uint32_t address
, int handle_breakpoints
)
683 struct hl_interface_s
*adapter
= target_to_adapter(target
);
684 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
685 struct breakpoint
*breakpoint
= NULL
;
686 struct reg
*pc
= armv7m
->arm
.pc
;
687 bool bkpt_inst_found
= false;
689 LOG_DEBUG("%s", __func__
);
691 if (target
->state
!= TARGET_HALTED
) {
692 LOG_WARNING("target not halted");
693 return ERROR_TARGET_NOT_HALTED
;
697 buf_set_u32(pc
->value
, 0, 32, address
);
702 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
704 /* the front-end may request us not to handle breakpoints */
705 if (handle_breakpoints
) {
706 breakpoint
= breakpoint_find(target
, pc_value
);
708 cortex_m_unset_breakpoint(target
, breakpoint
);
711 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
713 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
715 armv7m_restore_context(target
);
717 /* restore savedDCRDR */
718 res
= target_write_u32(target
, DCB_DCRDR
, target
->savedDCRDR
);
722 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
724 res
= adapter
->layout
->api
->step(adapter
->handle
);
729 /* registers are now invalid */
730 register_cache_invalidate(armv7m
->arm
.core_cache
);
733 cortex_m_set_breakpoint(target
, breakpoint
);
735 adapter_debug_entry(target
);
736 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
738 LOG_INFO("halted: PC: 0x%08" PRIx32
, buf_get_u32(armv7m
->arm
.pc
->value
, 0, 32));
743 static int adapter_read_memory(struct target
*target
, uint32_t address
,
744 uint32_t size
, uint32_t count
,
747 struct hl_interface_s
*adapter
= target_to_adapter(target
);
749 if (!count
|| !buffer
)
750 return ERROR_COMMAND_SYNTAX_ERROR
;
752 LOG_DEBUG("%s 0x%08" PRIx32
" %" PRIu32
" %" PRIu32
, __func__
, address
, size
, count
);
754 return adapter
->layout
->api
->read_mem(adapter
->handle
, address
, size
, count
, buffer
);
757 static int adapter_write_memory(struct target
*target
, uint32_t address
,
758 uint32_t size
, uint32_t count
,
759 const uint8_t *buffer
)
761 struct hl_interface_s
*adapter
= target_to_adapter(target
);
763 if (!count
|| !buffer
)
764 return ERROR_COMMAND_SYNTAX_ERROR
;
766 LOG_DEBUG("%s 0x%08" PRIx32
" %" PRIu32
" %" PRIu32
, __func__
, address
, size
, count
);
768 return adapter
->layout
->api
->write_mem(adapter
->handle
, address
, size
, count
, buffer
);
771 static const struct command_registration adapter_command_handlers
[] = {
773 .chain
= arm_command_handlers
,
776 .chain
= armv7m_trace_command_handlers
,
778 COMMAND_REGISTRATION_DONE
781 struct target_type hla_target
= {
782 .name
= "hla_target",
783 .deprecated_name
= "stm32_stlink",
785 .init_target
= adapter_init_target
,
786 .deinit_target
= cortex_m_deinit_target
,
787 .target_create
= adapter_target_create
,
788 .examine
= cortex_m_examine
,
789 .commands
= adapter_command_handlers
,
791 .poll
= adapter_poll
,
792 .arch_state
= armv7m_arch_state
,
794 .target_request_data
= hl_target_request_data
,
795 .assert_reset
= adapter_assert_reset
,
796 .deassert_reset
= adapter_deassert_reset
,
798 .halt
= adapter_halt
,
799 .resume
= adapter_resume
,
800 .step
= adapter_step
,
802 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
804 .read_memory
= adapter_read_memory
,
805 .write_memory
= adapter_write_memory
,
806 .checksum_memory
= armv7m_checksum_memory
,
807 .blank_check_memory
= armv7m_blank_check_memory
,
809 .run_algorithm
= armv7m_run_algorithm
,
810 .start_algorithm
= armv7m_start_algorithm
,
811 .wait_algorithm
= armv7m_wait_algorithm
,
813 .add_breakpoint
= cortex_m_add_breakpoint
,
814 .remove_breakpoint
= cortex_m_remove_breakpoint
,
815 .add_watchpoint
= cortex_m_add_watchpoint
,
816 .remove_watchpoint
= cortex_m_remove_watchpoint
,
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