1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
36 char* mips32_core_reg_list
[] =
38 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
39 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
40 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
41 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
42 "status", "lo", "hi", "badvaddr", "cause", "pc"
45 mips32_core_reg_t mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
88 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
89 * we also add 18 unknown registers to handle gdb requests */
91 #define MIPS32NUMFPREGS 34 + 18
93 u8 mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
95 reg_t mips32_gdb_dummy_fp_reg
=
97 "GDB dummy floating-point register", mips32_gdb_dummy_fp_value
, 0, 1, 32, NULL
, 0, NULL
, 0
100 int mips32_core_reg_arch_type
= -1;
102 int mips32_get_core_reg(reg_t
*reg
)
105 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
106 target_t
*target
= mips32_reg
->target
;
107 mips32_common_t
*mips32_target
= target
->arch_info
;
109 if (target
->state
!= TARGET_HALTED
)
111 return ERROR_TARGET_NOT_HALTED
;
114 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
119 int mips32_set_core_reg(reg_t
*reg
, u8
*buf
)
121 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
122 target_t
*target
= mips32_reg
->target
;
123 u32 value
= buf_get_u32(buf
, 0, 32);
125 if (target
->state
!= TARGET_HALTED
)
127 return ERROR_TARGET_NOT_HALTED
;
130 buf_set_u32(reg
->value
, 0, 32, value
);
137 int mips32_read_core_reg(struct target_s
*target
, int num
)
140 mips32_core_reg_t
*mips_core_reg
;
142 /* get pointers to arch-specific information */
143 mips32_common_t
*mips32
= target
->arch_info
;
145 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
146 return ERROR_INVALID_ARGUMENTS
;
148 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
149 reg_value
= mips32
->core_regs
[num
];
150 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
151 mips32
->core_cache
->reg_list
[num
].valid
= 1;
152 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
157 int mips32_write_core_reg(struct target_s
*target
, int num
)
160 mips32_core_reg_t
*mips_core_reg
;
162 /* get pointers to arch-specific information */
163 mips32_common_t
*mips32
= target
->arch_info
;
165 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
166 return ERROR_INVALID_ARGUMENTS
;
168 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
169 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
170 mips32
->core_regs
[num
] = reg_value
;
171 LOG_DEBUG("write core reg %i value 0x%x", num
, reg_value
);
172 mips32
->core_cache
->reg_list
[num
].valid
= 1;
173 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
178 int mips32_invalidate_core_regs(target_t
*target
)
180 /* get pointers to arch-specific information */
181 mips32_common_t
*mips32
= target
->arch_info
;
184 for (i
= 0; i
< mips32
->core_cache
->num_regs
; i
++)
186 mips32
->core_cache
->reg_list
[i
].valid
= 0;
187 mips32
->core_cache
->reg_list
[i
].dirty
= 0;
193 int mips32_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
195 /* get pointers to arch-specific information */
196 mips32_common_t
*mips32
= target
->arch_info
;
199 /* include floating point registers */
200 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
201 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
203 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
205 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
208 /* add dummy floating points regs */
209 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
211 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
217 int mips32_save_context(target_t
*target
)
221 /* get pointers to arch-specific information */
222 mips32_common_t
*mips32
= target
->arch_info
;
223 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
225 /* read core registers */
226 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
228 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
230 if (!mips32
->core_cache
->reg_list
[i
].valid
)
232 mips32
->read_core_reg(target
, i
);
239 int mips32_restore_context(target_t
*target
)
243 /* get pointers to arch-specific information */
244 mips32_common_t
*mips32
= target
->arch_info
;
245 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
247 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
249 if (mips32
->core_cache
->reg_list
[i
].dirty
)
251 mips32
->write_core_reg(target
, i
);
255 /* write core regs */
256 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
261 int mips32_arch_state(struct target_s
*target
)
263 mips32_common_t
*mips32
= target
->arch_info
;
265 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
267 LOG_ERROR("BUG: called for a non-MIPS32 target");
271 LOG_USER("target halted due to %s, pc: 0x%8.8x",
272 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
273 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
278 reg_cache_t
*mips32_build_reg_cache(target_t
*target
)
280 /* get pointers to arch-specific information */
281 mips32_common_t
*mips32
= target
->arch_info
;
283 int num_regs
= MIPS32NUMCOREREGS
;
284 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
285 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
286 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
287 mips32_core_reg_t
*arch_info
= malloc(sizeof(mips32_core_reg_t
) * num_regs
);
290 if (mips32_core_reg_arch_type
== -1)
291 mips32_core_reg_arch_type
= register_reg_arch_type(mips32_get_core_reg
, mips32_set_core_reg
);
293 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
295 /* Build the process context cache */
296 cache
->name
= "mips32 registers";
298 cache
->reg_list
= reg_list
;
299 cache
->num_regs
= num_regs
;
301 mips32
->core_cache
= cache
;
303 for (i
= 0; i
< num_regs
; i
++)
305 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
306 arch_info
[i
].target
= target
;
307 arch_info
[i
].mips32_common
= mips32
;
308 reg_list
[i
].name
= mips32_core_reg_list
[i
];
309 reg_list
[i
].size
= 32;
310 reg_list
[i
].value
= calloc(1, 4);
311 reg_list
[i
].dirty
= 0;
312 reg_list
[i
].valid
= 0;
313 reg_list
[i
].bitfield_desc
= NULL
;
314 reg_list
[i
].num_bitfields
= 0;
315 reg_list
[i
].arch_type
= mips32_core_reg_arch_type
;
316 reg_list
[i
].arch_info
= &arch_info
[i
];
322 int mips32_init_arch_info(target_t
*target
, mips32_common_t
*mips32
, jtag_tap_t
*tap
)
324 target
->arch_info
= mips32
;
325 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
327 /* has breakpoint/watchpint unit been scanned */
328 mips32
->bp_scanned
= 0;
329 mips32
->data_break_list
= NULL
;
331 mips32
->ejtag_info
.tap
= tap
;
332 mips32
->read_core_reg
= mips32_read_core_reg
;
333 mips32
->write_core_reg
= mips32_write_core_reg
;
338 int mips32_register_commands(struct command_context_s
*cmd_ctx
)
343 int mips32_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
349 int mips32_examine(struct target_s
*target
)
351 mips32_common_t
*mips32
= target
->arch_info
;
353 if (!target
->type
->examined
)
355 target
->type
->examined
= 1;
357 /* we will configure later */
358 mips32
->bp_scanned
= 0;
359 mips32
->num_inst_bpoints
= 0;
360 mips32
->num_data_bpoints
= 0;
361 mips32
->num_inst_bpoints_avail
= 0;
362 mips32
->num_data_bpoints_avail
= 0;
368 int mips32_configure_break_unit(struct target_s
*target
)
370 /* get pointers to arch-specific information */
371 mips32_common_t
*mips32
= target
->arch_info
;
376 if (mips32
->bp_scanned
)
379 /* get info about breakpoint support */
380 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
385 /* get number of inst breakpoints */
386 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
389 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
390 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
391 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(mips32_comparator_t
));
392 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
394 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
398 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
404 /* get number of data breakpoints */
405 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
408 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
409 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
410 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(mips32_comparator_t
));
411 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
413 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
417 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
421 LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
423 mips32
->bp_scanned
= 1;
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