1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2008 by Spencer Oliver *
5 * spen@spen-soft.co.uk *
7 * Copyright (C) 2008 by David T.L. Wong *
9 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
11 * Copyright (C) 2011 by Drasko DRASKOVIC *
12 * drasko.draskovic@gmail.com *
13 ***************************************************************************/
19 #include "breakpoints.h"
22 #include "mips32_dmaacc.h"
23 #include "target_type.h"
27 static void mips_m4k_enable_breakpoints(struct target
*target
);
28 static void mips_m4k_enable_watchpoints(struct target
*target
);
29 static int mips_m4k_set_breakpoint(struct target
*target
,
30 struct breakpoint
*breakpoint
);
31 static int mips_m4k_unset_breakpoint(struct target
*target
,
32 struct breakpoint
*breakpoint
);
33 static int mips_m4k_internal_restore(struct target
*target
, int current
,
34 target_addr_t address
, int handle_breakpoints
,
36 static int mips_m4k_halt(struct target
*target
);
37 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
38 uint32_t count
, const uint8_t *buffer
);
39 static int mips_m4k_bulk_read_memory(struct target
*target
, target_addr_t address
,
40 uint32_t count
, uint8_t *buffer
);
42 static int mips_m4k_examine_debug_reason(struct target
*target
)
44 struct mips32_common
*mips32
= target_to_mips32(target
);
45 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
46 uint32_t break_status
;
49 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
50 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
51 if (ejtag_info
->debug_caps
& EJTAG_DCR_IB
) {
52 /* get info about inst breakpoint support */
53 retval
= target_read_u32(target
,
54 ejtag_info
->ejtag_ibs_addr
, &break_status
);
55 if (retval
!= ERROR_OK
)
57 if (break_status
& 0x1f) {
58 /* we have halted on a breakpoint */
59 retval
= target_write_u32(target
,
60 ejtag_info
->ejtag_ibs_addr
, 0);
61 if (retval
!= ERROR_OK
)
63 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
67 if (ejtag_info
->debug_caps
& EJTAG_DCR_DB
) {
68 /* get info about data breakpoint support */
69 retval
= target_read_u32(target
,
70 ejtag_info
->ejtag_dbs_addr
, &break_status
);
71 if (retval
!= ERROR_OK
)
73 if (break_status
& 0x1f) {
74 /* we have halted on a breakpoint */
75 retval
= target_write_u32(target
,
76 ejtag_info
->ejtag_dbs_addr
, 0);
77 if (retval
!= ERROR_OK
)
79 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
87 static int mips_m4k_debug_entry(struct target
*target
)
89 struct mips32_common
*mips32
= target_to_mips32(target
);
90 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
92 mips32_save_context(target
);
94 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
95 mips_ejtag_config_step(ejtag_info
, 0);
97 /* make sure break unit configured */
98 mips32_configure_break_unit(target
);
100 /* attempt to find halt reason */
101 mips_m4k_examine_debug_reason(target
);
103 mips32_read_config_regs(target
);
105 /* default to mips32 isa, it will be changed below if required */
106 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
108 /* other than mips32 only and isa bit set ? */
109 if (mips32
->isa_imp
&& buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1))
110 mips32
->isa_mode
= mips32
->isa_imp
== 2 ? MIPS32_ISA_MIPS16E
: MIPS32_ISA_MMIPS32
;
112 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
113 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
114 target_state_name(target
));
119 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
121 struct target_list
*head
;
123 foreach_smp_target(head
, target
->smp_targets
) {
124 struct target
*curr
= head
->target
;
125 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
131 static int mips_m4k_halt_smp(struct target
*target
)
133 int retval
= ERROR_OK
;
134 struct target_list
*head
;
136 foreach_smp_target(head
, target
->smp_targets
) {
138 struct target
*curr
= head
->target
;
139 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
140 ret
= mips_m4k_halt(curr
);
142 if (ret
!= ERROR_OK
) {
143 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
150 static int update_halt_gdb(struct target
*target
)
152 int retval
= ERROR_OK
;
153 if (target
->gdb_service
->core
[0] == -1) {
154 target
->gdb_service
->target
= target
;
155 target
->gdb_service
->core
[0] = target
->coreid
;
156 retval
= mips_m4k_halt_smp(target
);
161 static int mips_m4k_poll(struct target
*target
)
163 int retval
= ERROR_OK
;
164 struct mips32_common
*mips32
= target_to_mips32(target
);
165 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
166 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
167 enum target_state prev_target_state
= target
->state
;
169 /* toggle to another core is done by gdb as follow */
170 /* maint packet J core_id */
172 /* the next polling trigger an halt event sent to gdb */
173 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
174 (target
->gdb_service
) &&
175 (!target
->gdb_service
->target
)) {
176 target
->gdb_service
->target
=
177 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
178 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
182 /* read ejtag control reg */
183 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
184 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
185 if (retval
!= ERROR_OK
)
188 ejtag_info
->isa
= (ejtag_ctrl
& EJTAG_CTRL_DBGISA
) ? 1 : 0;
190 /* clear this bit before handling polling
191 * as after reset registers will read zero */
192 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
193 /* we have detected a reset, clear flag
194 * otherwise ejtag will not work */
195 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
197 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
198 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
199 if (retval
!= ERROR_OK
)
201 LOG_DEBUG("Reset Detected");
204 /* check for processor halted */
205 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
206 if ((target
->state
!= TARGET_HALTED
)
207 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
208 if (target
->state
== TARGET_UNKNOWN
)
209 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
211 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
212 * (maybe put on by HALT-ing the board in the previous session).
214 * Force enable debug entry for this session.
216 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
217 target
->state
= TARGET_HALTED
;
218 retval
= mips_m4k_debug_entry(target
);
219 if (retval
!= ERROR_OK
)
223 ((prev_target_state
== TARGET_RUNNING
)
224 || (prev_target_state
== TARGET_RESET
))) {
225 retval
= update_halt_gdb(target
);
226 if (retval
!= ERROR_OK
)
229 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
230 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
231 target
->state
= TARGET_HALTED
;
233 retval
= mips_m4k_debug_entry(target
);
234 if (retval
!= ERROR_OK
)
238 retval
= update_halt_gdb(target
);
239 if (retval
!= ERROR_OK
)
243 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
246 target
->state
= TARGET_RUNNING
;
248 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
253 static int mips_m4k_halt(struct target
*target
)
255 struct mips32_common
*mips32
= target_to_mips32(target
);
256 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
258 LOG_DEBUG("target->state: %s", target_state_name(target
));
260 if (target
->state
== TARGET_HALTED
) {
261 LOG_DEBUG("target was already halted");
265 if (target
->state
== TARGET_UNKNOWN
)
266 LOG_WARNING("target was in unknown state when halt was requested");
268 if (target
->state
== TARGET_RESET
) {
269 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
270 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
271 return ERROR_TARGET_FAILURE
;
273 /* we came here in a reset_halt or reset_init sequence
274 * debug entry was already prepared in mips_m4k_assert_reset()
276 target
->debug_reason
= DBG_REASON_DBGRQ
;
282 /* break processor */
283 mips_ejtag_enter_debug(ejtag_info
);
285 target
->debug_reason
= DBG_REASON_DBGRQ
;
290 static int mips_m4k_assert_reset(struct target
*target
)
292 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
293 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
295 /* TODO: apply hw reset signal in not examined state */
296 if (!(target_was_examined(target
))) {
297 LOG_WARNING("Reset is not asserted because the target is not examined.");
298 LOG_WARNING("Use a reset button or power cycle the target.");
299 return ERROR_TARGET_NOT_EXAMINED
;
302 LOG_DEBUG("target->state: %s",
303 target_state_name(target
));
305 enum reset_types jtag_reset_config
= jtag_get_reset_config();
307 /* some cores support connecting while srst is asserted
308 * use that mode is it has been configured */
310 bool srst_asserted
= false;
312 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
313 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
314 jtag_add_reset(0, 1);
315 srst_asserted
= true;
319 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
320 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
) {
321 if (target
->reset_halt
) {
322 /* use hardware to catch reset */
323 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
325 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
328 if (jtag_reset_config
& RESET_HAS_SRST
) {
329 /* here we should issue a srst only, but we may have to assert trst as well */
330 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
331 jtag_add_reset(1, 1);
332 else if (!srst_asserted
)
333 jtag_add_reset(0, 1);
334 } else if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
335 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
337 if (mips_m4k
->is_pic32mx
) {
338 LOG_DEBUG("Using MTAP reset to reset processor...");
340 /* use microchip specific MTAP reset */
341 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
342 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
344 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
345 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
346 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
348 /* use ejtag reset - not supported by all cores */
349 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
350 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
351 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
352 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
356 target
->state
= TARGET_RESET
;
357 jtag_add_sleep(50000);
359 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
361 if (target
->reset_halt
) {
362 int retval
= target_halt(target
);
363 if (retval
!= ERROR_OK
)
370 static int mips_m4k_deassert_reset(struct target
*target
)
372 LOG_DEBUG("target->state: %s", target_state_name(target
));
374 /* deassert reset lines */
375 jtag_add_reset(0, 0);
380 static int mips_m4k_single_step_core(struct target
*target
)
382 struct mips32_common
*mips32
= target_to_mips32(target
);
383 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
385 /* configure single step mode */
386 mips_ejtag_config_step(ejtag_info
, 1);
388 /* disable interrupts while stepping */
389 mips32_enable_interrupts(target
, 0);
391 /* exit debug mode */
392 mips_ejtag_exit_debug(ejtag_info
);
394 mips_m4k_debug_entry(target
);
399 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
401 int retval
= ERROR_OK
;
402 struct target_list
*head
;
404 foreach_smp_target(head
, target
->smp_targets
) {
406 struct target
*curr
= head
->target
;
407 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
408 /* resume current address , not in step mode */
409 ret
= mips_m4k_internal_restore(curr
, 1, address
,
410 handle_breakpoints
, 0);
412 if (ret
!= ERROR_OK
) {
413 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
414 curr
->coreid
, address
);
422 static int mips_m4k_internal_restore(struct target
*target
, int current
,
423 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
425 struct mips32_common
*mips32
= target_to_mips32(target
);
426 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
427 struct breakpoint
*breakpoint
= NULL
;
430 if (target
->state
!= TARGET_HALTED
) {
431 LOG_WARNING("target not halted");
432 return ERROR_TARGET_NOT_HALTED
;
435 if (!debug_execution
) {
436 target_free_all_working_areas(target
);
437 mips_m4k_enable_breakpoints(target
);
438 mips_m4k_enable_watchpoints(target
);
441 /* current = 1: continue on current pc, otherwise continue at <address> */
443 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
444 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
445 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= true;
446 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= true;
449 if ((mips32
->isa_imp
> 1) && debug_execution
) /* if more than one isa supported */
450 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
455 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
457 mips32_restore_context(target
);
459 /* the front-end may request us not to handle breakpoints */
460 if (handle_breakpoints
) {
461 /* Single step past breakpoint at current address */
462 breakpoint
= breakpoint_find(target
, resume_pc
);
464 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
"",
465 breakpoint
->address
);
466 mips_m4k_unset_breakpoint(target
, breakpoint
);
467 mips_m4k_single_step_core(target
);
468 mips_m4k_set_breakpoint(target
, breakpoint
);
472 /* enable interrupts if we are running */
473 mips32_enable_interrupts(target
, !debug_execution
);
475 /* exit debug mode */
476 mips_ejtag_exit_debug(ejtag_info
);
477 target
->debug_reason
= DBG_REASON_NOTHALTED
;
479 /* registers are now invalid */
480 register_cache_invalidate(mips32
->core_cache
);
482 if (!debug_execution
) {
483 target
->state
= TARGET_RUNNING
;
484 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
485 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
487 target
->state
= TARGET_DEBUG_RUNNING
;
488 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
489 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
495 static int mips_m4k_resume(struct target
*target
, int current
,
496 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
498 int retval
= ERROR_OK
;
500 /* dummy resume for smp toggle in order to reduce gdb impact */
501 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
502 /* simulate a start and halt of target */
503 target
->gdb_service
->target
= NULL
;
504 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
505 /* fake resume at next poll we play the target core[1], see poll*/
506 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
510 retval
= mips_m4k_internal_restore(target
, current
, address
,
514 if (retval
== ERROR_OK
&& target
->smp
) {
515 target
->gdb_service
->core
[0] = -1;
516 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
522 static int mips_m4k_step(struct target
*target
, int current
,
523 target_addr_t address
, int handle_breakpoints
)
525 /* get pointers to arch-specific information */
526 struct mips32_common
*mips32
= target_to_mips32(target
);
527 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
528 struct breakpoint
*breakpoint
= NULL
;
530 if (target
->state
!= TARGET_HALTED
) {
531 LOG_WARNING("target not halted");
532 return ERROR_TARGET_NOT_HALTED
;
535 /* current = 1: continue on current pc, otherwise continue at <address> */
537 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
538 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
539 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= true;
540 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= true;
543 /* the front-end may request us not to handle breakpoints */
544 if (handle_breakpoints
) {
545 breakpoint
= breakpoint_find(target
,
546 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
548 mips_m4k_unset_breakpoint(target
, breakpoint
);
551 /* restore context */
552 mips32_restore_context(target
);
554 /* configure single step mode */
555 mips_ejtag_config_step(ejtag_info
, 1);
557 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
559 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
561 /* disable interrupts while stepping */
562 mips32_enable_interrupts(target
, 0);
564 /* exit debug mode */
565 mips_ejtag_exit_debug(ejtag_info
);
567 /* registers are now invalid */
568 register_cache_invalidate(mips32
->core_cache
);
570 LOG_DEBUG("target stepped ");
571 mips_m4k_debug_entry(target
);
574 mips_m4k_set_breakpoint(target
, breakpoint
);
576 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
581 static void mips_m4k_enable_breakpoints(struct target
*target
)
583 struct breakpoint
*breakpoint
= target
->breakpoints
;
585 /* set any pending breakpoints */
587 if (!breakpoint
->is_set
)
588 mips_m4k_set_breakpoint(target
, breakpoint
);
589 breakpoint
= breakpoint
->next
;
593 static int mips_m4k_set_breakpoint(struct target
*target
,
594 struct breakpoint
*breakpoint
)
596 struct mips32_common
*mips32
= target_to_mips32(target
);
597 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
598 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
601 if (breakpoint
->is_set
) {
602 LOG_WARNING("breakpoint already set");
606 if (breakpoint
->type
== BKPT_HARD
) {
609 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
611 if (bp_num
>= mips32
->num_inst_bpoints
) {
612 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
613 breakpoint
->unique_id
);
614 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
616 breakpoint_hw_set(breakpoint
, bp_num
);
617 comparator_list
[bp_num
].used
= 1;
618 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
620 if (breakpoint
->length
!= 4) /* make sure isa bit set */
621 comparator_list
[bp_num
].bp_value
|= 1;
622 else /* make sure isa bit cleared */
623 comparator_list
[bp_num
].bp_value
&= ~1;
625 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
626 * Warning: there is no IB ASID registers in 2.0.
627 * Do not set it! :) */
628 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
629 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
631 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
632 comparator_list
[bp_num
].bp_value
);
633 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
634 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
635 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
636 ejtag_info
->ejtag_ibc_offs
, 1);
637 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
638 breakpoint
->unique_id
,
639 bp_num
, comparator_list
[bp_num
].bp_value
);
640 } else if (breakpoint
->type
== BKPT_SOFT
) {
641 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
643 uint32_t isa_req
= breakpoint
->length
& 1; /* micro mips request bit */
644 uint32_t bplength
= breakpoint
->length
& ~1; /* drop micro mips request bit for length */
645 uint32_t bpaddr
= breakpoint
->address
& ~1; /* drop isa bit from address, if set */
648 uint32_t verify
= 0xffffffff;
649 uint32_t sdbbp32_instr
= MIPS32_SDBBP(isa_req
);
650 if (ejtag_info
->endianness
&& isa_req
)
651 sdbbp32_instr
= SWAP16(sdbbp32_instr
);
653 if ((breakpoint
->address
& 3) == 0) { /* word aligned */
655 retval
= target_read_memory(target
, bpaddr
, bplength
, 1, breakpoint
->orig_instr
);
656 if (retval
!= ERROR_OK
)
659 retval
= target_write_u32(target
, bpaddr
, sdbbp32_instr
);
660 if (retval
!= ERROR_OK
)
663 retval
= target_read_u32(target
, bpaddr
, &verify
);
664 if (retval
!= ERROR_OK
)
667 if (verify
!= sdbbp32_instr
)
670 } else { /* 16 bit aligned */
671 retval
= target_read_memory(target
, bpaddr
, 2, 2, breakpoint
->orig_instr
);
672 if (retval
!= ERROR_OK
)
675 uint8_t sdbbp_buf
[4];
676 target_buffer_set_u32(target
, sdbbp_buf
, sdbbp32_instr
);
678 retval
= target_write_memory(target
, bpaddr
, 2, 2, sdbbp_buf
);
679 if (retval
!= ERROR_OK
)
682 retval
= target_read_memory(target
, bpaddr
, 2, 2, sdbbp_buf
);
683 if (retval
!= ERROR_OK
)
686 if (target_buffer_get_u32(target
, sdbbp_buf
) != sdbbp32_instr
)
691 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
692 " - check that memory is read/writable", breakpoint
->address
);
697 uint16_t verify
= 0xffff;
699 retval
= target_read_memory(target
, bpaddr
, bplength
, 1, breakpoint
->orig_instr
);
700 if (retval
!= ERROR_OK
)
703 retval
= target_write_u16(target
, bpaddr
, MIPS16_SDBBP(isa_req
));
704 if (retval
!= ERROR_OK
)
707 retval
= target_read_u16(target
, bpaddr
, &verify
);
708 if (retval
!= ERROR_OK
)
711 if (verify
!= MIPS16_SDBBP(isa_req
)) {
712 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
713 " - check that memory is read/writable", breakpoint
->address
);
718 breakpoint
->is_set
= true;
724 static int mips_m4k_unset_breakpoint(struct target
*target
,
725 struct breakpoint
*breakpoint
)
727 /* get pointers to arch-specific information */
728 struct mips32_common
*mips32
= target_to_mips32(target
);
729 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
730 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
733 if (!breakpoint
->is_set
) {
734 LOG_WARNING("breakpoint not set");
738 if (breakpoint
->type
== BKPT_HARD
) {
739 int bp_num
= breakpoint
->number
;
740 if (bp_num
>= mips32
->num_inst_bpoints
) {
741 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
742 breakpoint
->unique_id
);
745 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
746 breakpoint
->unique_id
,
748 comparator_list
[bp_num
].used
= 0;
749 comparator_list
[bp_num
].bp_value
= 0;
750 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
751 ejtag_info
->ejtag_ibc_offs
, 0);
754 /* restore original instruction (kept in target endianness) */
755 uint32_t isa_req
= breakpoint
->length
& 1;
756 uint32_t bplength
= breakpoint
->length
& ~1;
757 uint8_t current_instr
[4];
758 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
760 uint32_t sdbbp32_instr
= MIPS32_SDBBP(isa_req
);
761 if (ejtag_info
->endianness
&& isa_req
)
762 sdbbp32_instr
= SWAP16(sdbbp32_instr
);
764 if ((breakpoint
->address
& 3) == 0) { /* 32bit aligned */
765 /* check that user program has not modified breakpoint instruction */
766 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, current_instr
);
767 if (retval
!= ERROR_OK
)
770 * target_read_memory() gets us data in _target_ endianness.
771 * If we want to use this data on the host for comparisons with some macros
772 * we must first transform it to _host_ endianness using target_buffer_get_u16().
774 if (sdbbp32_instr
== target_buffer_get_u32(target
, current_instr
)) {
775 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
776 breakpoint
->orig_instr
);
777 if (retval
!= ERROR_OK
)
780 } else { /* 16bit aligned */
781 retval
= target_read_memory(target
, breakpoint
->address
, 2, 2, current_instr
);
782 if (retval
!= ERROR_OK
)
785 if (sdbbp32_instr
== target_buffer_get_u32(target
, current_instr
)) {
786 retval
= target_write_memory(target
, breakpoint
->address
, 2, 2,
787 breakpoint
->orig_instr
);
788 if (retval
!= ERROR_OK
)
793 /* check that user program has not modified breakpoint instruction */
794 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, current_instr
);
795 if (retval
!= ERROR_OK
)
798 if (target_buffer_get_u16(target
, current_instr
) == MIPS16_SDBBP(isa_req
)) {
799 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
800 breakpoint
->orig_instr
);
801 if (retval
!= ERROR_OK
)
807 breakpoint
->is_set
= false;
812 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
814 struct mips32_common
*mips32
= target_to_mips32(target
);
816 if ((breakpoint
->length
> 5 || breakpoint
->length
< 2) || /* out of range */
817 (breakpoint
->length
== 4 && (breakpoint
->address
& 2)) || /* mips32 unaligned */
818 (mips32
->isa_imp
== MIPS32_ONLY
&& breakpoint
->length
!= 4) || /* misp32 specific */
819 ((mips32
->isa_imp
& 1) != (breakpoint
->length
& 1))) /* isa not implemented */
820 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
822 if (breakpoint
->type
== BKPT_HARD
) {
823 if (mips32
->num_inst_bpoints_avail
< 1) {
824 LOG_INFO("no hardware breakpoint available");
825 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
828 mips32
->num_inst_bpoints_avail
--;
831 return mips_m4k_set_breakpoint(target
, breakpoint
);
834 static int mips_m4k_remove_breakpoint(struct target
*target
,
835 struct breakpoint
*breakpoint
)
837 /* get pointers to arch-specific information */
838 struct mips32_common
*mips32
= target_to_mips32(target
);
840 if (target
->state
!= TARGET_HALTED
) {
841 LOG_WARNING("target not halted");
842 return ERROR_TARGET_NOT_HALTED
;
845 if (breakpoint
->is_set
)
846 mips_m4k_unset_breakpoint(target
, breakpoint
);
848 if (breakpoint
->type
== BKPT_HARD
)
849 mips32
->num_inst_bpoints_avail
++;
854 static int mips_m4k_set_watchpoint(struct target
*target
,
855 struct watchpoint
*watchpoint
)
857 struct mips32_common
*mips32
= target_to_mips32(target
);
858 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
859 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
862 * watchpoint enabled, ignore all byte lanes in value register
863 * and exclude both load and store accesses from watchpoint
864 * condition evaluation
866 int enable
= EJTAG_DBCN_NOSB
| EJTAG_DBCN_NOLB
| EJTAG_DBCN_BE
|
867 (0xff << EJTAG_DBCN_BLM_SHIFT
);
869 if (watchpoint
->is_set
) {
870 LOG_WARNING("watchpoint already set");
874 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
876 if (wp_num
>= mips32
->num_data_bpoints
) {
877 LOG_ERROR("Can not find free FP Comparator");
881 if (watchpoint
->length
!= 4) {
882 LOG_ERROR("Only watchpoints of length 4 are supported");
883 return ERROR_TARGET_UNALIGNED_ACCESS
;
886 if (watchpoint
->address
% 4) {
887 LOG_ERROR("Watchpoints address should be word aligned");
888 return ERROR_TARGET_UNALIGNED_ACCESS
;
891 switch (watchpoint
->rw
) {
893 enable
&= ~EJTAG_DBCN_NOLB
;
896 enable
&= ~EJTAG_DBCN_NOSB
;
899 enable
&= ~(EJTAG_DBCN_NOLB
| EJTAG_DBCN_NOSB
);
902 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
905 watchpoint_set(watchpoint
, wp_num
);
906 comparator_list
[wp_num
].used
= 1;
907 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
909 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
910 * There is as well no ASID register support. */
911 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
912 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
914 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
915 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
917 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
918 comparator_list
[wp_num
].bp_value
);
919 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
920 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
922 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
923 ejtag_info
->ejtag_dbc_offs
, enable
);
924 /* TODO: probably this value is ignored on 2.0 */
925 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
926 ejtag_info
->ejtag_dbv_offs
, 0);
927 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
932 static int mips_m4k_unset_watchpoint(struct target
*target
,
933 struct watchpoint
*watchpoint
)
935 /* get pointers to arch-specific information */
936 struct mips32_common
*mips32
= target_to_mips32(target
);
937 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
938 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
940 if (!watchpoint
->is_set
) {
941 LOG_WARNING("watchpoint not set");
945 int wp_num
= watchpoint
->number
;
946 if (wp_num
>= mips32
->num_data_bpoints
) {
947 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
950 comparator_list
[wp_num
].used
= 0;
951 comparator_list
[wp_num
].bp_value
= 0;
952 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
953 ejtag_info
->ejtag_dbc_offs
, 0);
954 watchpoint
->is_set
= false;
959 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
961 struct mips32_common
*mips32
= target_to_mips32(target
);
963 if (mips32
->num_data_bpoints_avail
< 1) {
964 LOG_INFO("no hardware watchpoints available");
965 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
968 mips32
->num_data_bpoints_avail
--;
970 mips_m4k_set_watchpoint(target
, watchpoint
);
974 static int mips_m4k_remove_watchpoint(struct target
*target
,
975 struct watchpoint
*watchpoint
)
977 /* get pointers to arch-specific information */
978 struct mips32_common
*mips32
= target_to_mips32(target
);
980 if (target
->state
!= TARGET_HALTED
) {
981 LOG_WARNING("target not halted");
982 return ERROR_TARGET_NOT_HALTED
;
985 if (watchpoint
->is_set
)
986 mips_m4k_unset_watchpoint(target
, watchpoint
);
988 mips32
->num_data_bpoints_avail
++;
993 static void mips_m4k_enable_watchpoints(struct target
*target
)
995 struct watchpoint
*watchpoint
= target
->watchpoints
;
997 /* set any pending watchpoints */
999 if (!watchpoint
->is_set
)
1000 mips_m4k_set_watchpoint(target
, watchpoint
);
1001 watchpoint
= watchpoint
->next
;
1005 static int mips_m4k_read_memory(struct target
*target
, target_addr_t address
,
1006 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1008 struct mips32_common
*mips32
= target_to_mips32(target
);
1009 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1011 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1012 address
, size
, count
);
1014 if (target
->state
!= TARGET_HALTED
) {
1015 LOG_WARNING("target not halted");
1016 return ERROR_TARGET_NOT_HALTED
;
1019 /* sanitize arguments */
1020 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1021 return ERROR_COMMAND_SYNTAX_ERROR
;
1023 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1024 return ERROR_TARGET_UNALIGNED_ACCESS
;
1026 if (size
== 4 && count
> 32) {
1027 int retval
= mips_m4k_bulk_read_memory(target
, address
, count
, buffer
);
1028 if (retval
== ERROR_OK
)
1030 LOG_WARNING("Falling back to non-bulk read");
1032 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1036 t
= malloc(count
* size
* sizeof(uint8_t));
1038 LOG_ERROR("Out of memory");
1044 /* if noDMA off, use DMAACC mode for memory read */
1046 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1047 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
1049 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
1051 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1052 /* endianness, but byte array should represent target endianness */
1053 if (retval
== ERROR_OK
) {
1056 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1059 target_buffer_set_u16_array(target
, buffer
, count
, t
);
1070 static int mips_m4k_write_memory(struct target
*target
, target_addr_t address
,
1071 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1073 struct mips32_common
*mips32
= target_to_mips32(target
);
1074 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1076 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1077 address
, size
, count
);
1079 if (target
->state
!= TARGET_HALTED
) {
1080 LOG_WARNING("target not halted");
1081 return ERROR_TARGET_NOT_HALTED
;
1084 if (size
== 4 && count
> 32) {
1085 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1086 if (retval
== ERROR_OK
)
1088 LOG_WARNING("Falling back to non-bulk write");
1091 /* sanitize arguments */
1092 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1093 return ERROR_COMMAND_SYNTAX_ERROR
;
1095 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1096 return ERROR_TARGET_UNALIGNED_ACCESS
;
1098 /** correct endianness if we have word or hword access */
1101 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1102 /* endianness, but byte array represents target endianness */
1103 t
= malloc(count
* size
* sizeof(uint8_t));
1105 LOG_ERROR("Out of memory");
1111 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1114 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1120 /* if noDMA off, use DMAACC mode for memory write */
1122 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1123 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1125 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1129 if (retval
!= ERROR_OK
)
1135 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1136 struct target
*target
)
1138 mips32_build_reg_cache(target
);
1143 static int mips_m4k_init_arch_info(struct target
*target
,
1144 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1146 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1148 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1150 /* initialize mips4k specific info */
1151 mips32_init_arch_info(target
, mips32
, tap
);
1152 mips32
->arch_info
= mips_m4k
;
1157 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1159 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1161 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1166 static int mips_m4k_examine(struct target
*target
)
1168 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1169 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1171 if (!target_was_examined(target
)) {
1172 int retval
= mips_ejtag_get_idcode(ejtag_info
);
1173 if (retval
!= ERROR_OK
) {
1174 LOG_ERROR("idcode read failed");
1177 if (((ejtag_info
->idcode
>> 1) & 0x7FF) == 0x29) {
1178 /* we are using a pic32mx so select ejtag port
1179 * as it is not selected by default */
1180 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1181 LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1182 mips_m4k
->is_pic32mx
= true;
1186 /* init rest of ejtag interface */
1187 int retval
= mips_ejtag_init(ejtag_info
);
1188 if (retval
!= ERROR_OK
)
1191 return mips32_examine(target
);
1194 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
1195 uint32_t count
, const uint8_t *buffer
)
1197 struct mips32_common
*mips32
= target_to_mips32(target
);
1198 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1199 struct working_area
*fast_data_area
;
1203 LOG_DEBUG("address: " TARGET_ADDR_FMT
", count: 0x%8.8" PRIx32
"",
1206 /* check alignment */
1208 return ERROR_TARGET_UNALIGNED_ACCESS
;
1210 if (!mips32
->fast_data_area
) {
1211 /* Get memory for block write handler
1212 * we preserve this area between calls and gain a speed increase
1213 * of about 3kb/sec when writing flash
1214 * this will be released/nulled by the system when the target is resumed or reset */
1215 retval
= target_alloc_working_area(target
,
1216 MIPS32_FASTDATA_HANDLER_SIZE
,
1217 &mips32
->fast_data_area
);
1218 if (retval
!= ERROR_OK
) {
1219 LOG_ERROR("No working area available");
1223 /* reset fastadata state so the algo get reloaded */
1224 ejtag_info
->fast_access_save
= -1;
1227 fast_data_area
= mips32
->fast_data_area
;
1229 if (address
< (fast_data_area
->address
+ fast_data_area
->size
) &&
1230 fast_data_area
->address
< (address
+ count
)) {
1231 LOG_ERROR("fast_data (" TARGET_ADDR_FMT
") is within write area "
1232 "(" TARGET_ADDR_FMT
"-" TARGET_ADDR_FMT
").",
1233 fast_data_area
->address
, address
, address
+ count
);
1234 LOG_ERROR("Change work-area-phys or load_image address!");
1238 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1239 /* but byte array represents target endianness */
1241 t
= malloc(count
* sizeof(uint32_t));
1243 LOG_ERROR("Out of memory");
1247 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1249 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1254 if (retval
!= ERROR_OK
)
1255 LOG_ERROR("Fastdata access Failed");
1260 static int mips_m4k_bulk_read_memory(struct target
*target
, target_addr_t address
,
1261 uint32_t count
, uint8_t *buffer
)
1263 struct mips32_common
*mips32
= target_to_mips32(target
);
1264 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1265 struct working_area
*fast_data_area
;
1269 LOG_DEBUG("address: " TARGET_ADDR_FMT
", count: 0x%8.8" PRIx32
"",
1272 /* check alignment */
1274 return ERROR_TARGET_UNALIGNED_ACCESS
;
1276 if (!mips32
->fast_data_area
) {
1277 /* Get memory for block read handler
1278 * we preserve this area between calls and gain a speed increase
1279 * of about 3kb/sec when reading flash
1280 * this will be released/nulled by the system when the target is resumed or reset */
1281 retval
= target_alloc_working_area(target
,
1282 MIPS32_FASTDATA_HANDLER_SIZE
,
1283 &mips32
->fast_data_area
);
1284 if (retval
!= ERROR_OK
) {
1285 LOG_ERROR("No working area available");
1289 /* reset fastadata state so the algo get reloaded */
1290 ejtag_info
->fast_access_save
= -1;
1293 fast_data_area
= mips32
->fast_data_area
;
1295 if (address
< (fast_data_area
->address
+ fast_data_area
->size
) &&
1296 fast_data_area
->address
< (address
+ count
)) {
1297 LOG_ERROR("fast_data (" TARGET_ADDR_FMT
") is within read area "
1298 "(" TARGET_ADDR_FMT
"-" TARGET_ADDR_FMT
").",
1299 fast_data_area
->address
, address
, address
+ count
);
1300 LOG_ERROR("Change work-area-phys or load_image address!");
1304 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1305 /* but byte array represents target endianness */
1306 uint32_t *t
= malloc(count
* sizeof(uint32_t));
1308 LOG_ERROR("Out of memory");
1312 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1315 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1319 if (retval
!= ERROR_OK
)
1320 LOG_ERROR("Fastdata access Failed");
1325 static int mips_m4k_verify_pointer(struct command_invocation
*cmd
,
1326 struct mips_m4k_common
*mips_m4k
)
1328 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1329 command_print(cmd
, "target is not an MIPS_M4K");
1330 return ERROR_TARGET_INVALID
;
1335 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1338 struct target
*target
= get_current_target(CMD_CTX
);
1339 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1340 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1342 retval
= mips_m4k_verify_pointer(CMD
, mips_m4k
);
1343 if (retval
!= ERROR_OK
)
1346 if (target
->state
!= TARGET_HALTED
) {
1347 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
1351 /* two or more argument, access a single register/select (write if third argument is given) */
1353 return ERROR_COMMAND_SYNTAX_ERROR
;
1355 uint32_t cp0_reg
, cp0_sel
;
1356 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1357 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1359 if (CMD_ARGC
== 2) {
1361 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1362 if (retval
!= ERROR_OK
) {
1364 "couldn't access reg %" PRIu32
,
1368 command_print(CMD
, "cp0 reg %" PRIu32
", select %" PRIu32
": %8.8" PRIx32
,
1369 cp0_reg
, cp0_sel
, value
);
1371 } else if (CMD_ARGC
== 3) {
1373 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1374 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1375 if (retval
!= ERROR_OK
) {
1377 "couldn't access cp0 reg %" PRIu32
", select %" PRIu32
,
1381 command_print(CMD
, "cp0 reg %" PRIu32
", select %" PRIu32
": %8.8" PRIx32
,
1382 cp0_reg
, cp0_sel
, value
);
1389 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1391 struct target
*target
= get_current_target(CMD_CTX
);
1392 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1393 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1396 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1397 else if (CMD_ARGC
> 1)
1398 return ERROR_COMMAND_SYNTAX_ERROR
;
1400 command_print(CMD
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1401 if (ejtag_info
->scan_delay
>= MIPS32_SCAN_DELAY_LEGACY_MODE
) {
1402 ejtag_info
->mode
= 0;
1403 command_print(CMD
, "running in legacy mode");
1405 ejtag_info
->mode
= 1;
1406 command_print(CMD
, "running in fast queued mode");
1412 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1415 .handler
= mips_m4k_handle_cp0_command
,
1416 .mode
= COMMAND_EXEC
,
1417 .usage
= "regnum [value]",
1418 .help
= "display/modify cp0 register",
1421 .name
= "scan_delay",
1422 .handler
= mips_m4k_handle_scan_delay_command
,
1423 .mode
= COMMAND_ANY
,
1424 .help
= "display/set scan delay in nano seconds",
1428 .chain
= smp_command_handlers
,
1430 COMMAND_REGISTRATION_DONE
1433 static const struct command_registration mips_m4k_command_handlers
[] = {
1435 .chain
= mips32_command_handlers
,
1439 .mode
= COMMAND_ANY
,
1440 .help
= "mips_m4k command group",
1442 .chain
= mips_m4k_exec_command_handlers
,
1444 COMMAND_REGISTRATION_DONE
1447 struct target_type mips_m4k_target
= {
1450 .poll
= mips_m4k_poll
,
1451 .arch_state
= mips32_arch_state
,
1453 .halt
= mips_m4k_halt
,
1454 .resume
= mips_m4k_resume
,
1455 .step
= mips_m4k_step
,
1457 .assert_reset
= mips_m4k_assert_reset
,
1458 .deassert_reset
= mips_m4k_deassert_reset
,
1460 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1462 .read_memory
= mips_m4k_read_memory
,
1463 .write_memory
= mips_m4k_write_memory
,
1464 .checksum_memory
= mips32_checksum_memory
,
1465 .blank_check_memory
= mips32_blank_check_memory
,
1467 .run_algorithm
= mips32_run_algorithm
,
1469 .add_breakpoint
= mips_m4k_add_breakpoint
,
1470 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1471 .add_watchpoint
= mips_m4k_add_watchpoint
,
1472 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1474 .commands
= mips_m4k_command_handlers
,
1475 .target_create
= mips_m4k_target_create
,
1476 .init_target
= mips_m4k_init_target
,
1477 .examine
= mips_m4k_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)