1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
32 #include "breakpoints.h"
35 #include "mips32_dmaacc.h"
36 #include "target_type.h"
39 static void mips_m4k_enable_breakpoints(struct target
*target
);
40 static void mips_m4k_enable_watchpoints(struct target
*target
);
41 static int mips_m4k_set_breakpoint(struct target
*target
,
42 struct breakpoint
*breakpoint
);
43 static int mips_m4k_unset_breakpoint(struct target
*target
,
44 struct breakpoint
*breakpoint
);
45 static int mips_m4k_internal_restore(struct target
*target
, int current
,
46 uint32_t address
, int handle_breakpoints
,
48 static int mips_m4k_halt(struct target
*target
);
49 static int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
50 uint32_t count
, const uint8_t *buffer
);
52 static int mips_m4k_examine_debug_reason(struct target
*target
)
54 struct mips32_common
*mips32
= target_to_mips32(target
);
55 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
56 uint32_t break_status
;
59 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
60 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
61 /* get info about inst breakpoint support */
62 retval
= target_read_u32(target
,
63 ejtag_info
->ejtag_ibs_addr
, &break_status
);
64 if (retval
!= ERROR_OK
)
66 if (break_status
& 0x1f) {
67 /* we have halted on a breakpoint */
68 retval
= target_write_u32(target
,
69 ejtag_info
->ejtag_ibs_addr
, 0);
70 if (retval
!= ERROR_OK
)
72 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
75 /* get info about data breakpoint support */
76 retval
= target_read_u32(target
,
77 ejtag_info
->ejtag_dbs_addr
, &break_status
);
78 if (retval
!= ERROR_OK
)
80 if (break_status
& 0x1f) {
81 /* we have halted on a breakpoint */
82 retval
= target_write_u32(target
,
83 ejtag_info
->ejtag_dbs_addr
, 0);
84 if (retval
!= ERROR_OK
)
86 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
93 static int mips_m4k_debug_entry(struct target
*target
)
95 struct mips32_common
*mips32
= target_to_mips32(target
);
96 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
98 mips32_save_context(target
);
100 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
101 mips_ejtag_config_step(ejtag_info
, 0);
103 /* make sure break unit configured */
104 mips32_configure_break_unit(target
);
106 /* attempt to find halt reason */
107 mips_m4k_examine_debug_reason(target
);
109 /* default to mips32 isa, it will be changed below if required */
110 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
112 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
113 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
115 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
116 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
117 target_state_name(target
));
122 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
124 struct target_list
*head
;
128 while (head
!= (struct target_list
*)NULL
) {
130 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
137 static int mips_m4k_halt_smp(struct target
*target
)
139 int retval
= ERROR_OK
;
140 struct target_list
*head
;
143 while (head
!= (struct target_list
*)NULL
) {
146 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
147 ret
= mips_m4k_halt(curr
);
149 if (ret
!= ERROR_OK
) {
150 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
158 static int update_halt_gdb(struct target
*target
)
160 int retval
= ERROR_OK
;
161 if (target
->gdb_service
->core
[0] == -1) {
162 target
->gdb_service
->target
= target
;
163 target
->gdb_service
->core
[0] = target
->coreid
;
164 retval
= mips_m4k_halt_smp(target
);
169 static int mips_m4k_poll(struct target
*target
)
171 int retval
= ERROR_OK
;
172 struct mips32_common
*mips32
= target_to_mips32(target
);
173 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
174 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
175 enum target_state prev_target_state
= target
->state
;
177 /* toggle to another core is done by gdb as follow */
178 /* maint packet J core_id */
180 /* the next polling trigger an halt event sent to gdb */
181 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
182 (target
->gdb_service
) &&
183 (target
->gdb_service
->target
== NULL
)) {
184 target
->gdb_service
->target
=
185 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
186 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
190 /* read ejtag control reg */
191 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
192 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
193 if (retval
!= ERROR_OK
)
196 /* clear this bit before handling polling
197 * as after reset registers will read zero */
198 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
199 /* we have detected a reset, clear flag
200 * otherwise ejtag will not work */
201 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
203 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
204 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
205 if (retval
!= ERROR_OK
)
207 LOG_DEBUG("Reset Detected");
210 /* check for processor halted */
211 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
212 if ((target
->state
!= TARGET_HALTED
)
213 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
214 if (target
->state
== TARGET_UNKNOWN
)
215 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
217 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
218 * (maybe put on by HALT-ing the board in the previous session).
220 * Force enable debug entry for this session.
222 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
223 target
->state
= TARGET_HALTED
;
224 retval
= mips_m4k_debug_entry(target
);
225 if (retval
!= ERROR_OK
)
229 ((prev_target_state
== TARGET_RUNNING
)
230 || (prev_target_state
== TARGET_RESET
))) {
231 retval
= update_halt_gdb(target
);
232 if (retval
!= ERROR_OK
)
235 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
236 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
237 target
->state
= TARGET_HALTED
;
239 retval
= mips_m4k_debug_entry(target
);
240 if (retval
!= ERROR_OK
)
244 retval
= update_halt_gdb(target
);
245 if (retval
!= ERROR_OK
)
249 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
252 target
->state
= TARGET_RUNNING
;
254 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
259 static int mips_m4k_halt(struct target
*target
)
261 struct mips32_common
*mips32
= target_to_mips32(target
);
262 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
264 LOG_DEBUG("target->state: %s", target_state_name(target
));
266 if (target
->state
== TARGET_HALTED
) {
267 LOG_DEBUG("target was already halted");
271 if (target
->state
== TARGET_UNKNOWN
)
272 LOG_WARNING("target was in unknown state when halt was requested");
274 if (target
->state
== TARGET_RESET
) {
275 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
276 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
277 return ERROR_TARGET_FAILURE
;
279 /* we came here in a reset_halt or reset_init sequence
280 * debug entry was already prepared in mips_m4k_assert_reset()
282 target
->debug_reason
= DBG_REASON_DBGRQ
;
288 /* break processor */
289 mips_ejtag_enter_debug(ejtag_info
);
291 target
->debug_reason
= DBG_REASON_DBGRQ
;
296 static int mips_m4k_assert_reset(struct target
*target
)
298 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
299 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
301 LOG_DEBUG("target->state: %s",
302 target_state_name(target
));
304 enum reset_types jtag_reset_config
= jtag_get_reset_config();
306 /* some cores support connecting while srst is asserted
307 * use that mode is it has been configured */
309 bool srst_asserted
= false;
311 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
312 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
313 jtag_add_reset(0, 1);
314 srst_asserted
= true;
317 if (target
->reset_halt
) {
318 /* use hardware to catch reset */
319 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
321 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
323 if (jtag_reset_config
& RESET_HAS_SRST
) {
324 /* here we should issue a srst only, but we may have to assert trst as well */
325 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
326 jtag_add_reset(1, 1);
327 else if (!srst_asserted
)
328 jtag_add_reset(0, 1);
330 if (mips_m4k
->is_pic32mx
) {
331 LOG_DEBUG("Using MTAP reset to reset processor...");
333 /* use microchip specific MTAP reset */
334 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
335 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
337 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
338 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
339 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
341 /* use ejtag reset - not supported by all cores */
342 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
343 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
344 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
345 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
349 target
->state
= TARGET_RESET
;
350 jtag_add_sleep(50000);
352 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
354 if (target
->reset_halt
) {
355 int retval
= target_halt(target
);
356 if (retval
!= ERROR_OK
)
363 static int mips_m4k_deassert_reset(struct target
*target
)
365 LOG_DEBUG("target->state: %s", target_state_name(target
));
367 /* deassert reset lines */
368 jtag_add_reset(0, 0);
373 static int mips_m4k_single_step_core(struct target
*target
)
375 struct mips32_common
*mips32
= target_to_mips32(target
);
376 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
378 /* configure single step mode */
379 mips_ejtag_config_step(ejtag_info
, 1);
381 /* disable interrupts while stepping */
382 mips32_enable_interrupts(target
, 0);
384 /* exit debug mode */
385 mips_ejtag_exit_debug(ejtag_info
);
387 mips_m4k_debug_entry(target
);
392 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
394 int retval
= ERROR_OK
;
395 struct target_list
*head
;
399 while (head
!= (struct target_list
*)NULL
) {
402 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
403 /* resume current address , not in step mode */
404 ret
= mips_m4k_internal_restore(curr
, 1, address
,
405 handle_breakpoints
, 0);
407 if (ret
!= ERROR_OK
) {
408 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
409 curr
->coreid
, address
);
418 static int mips_m4k_internal_restore(struct target
*target
, int current
,
419 uint32_t address
, int handle_breakpoints
, int debug_execution
)
421 struct mips32_common
*mips32
= target_to_mips32(target
);
422 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
423 struct breakpoint
*breakpoint
= NULL
;
426 if (target
->state
!= TARGET_HALTED
) {
427 LOG_WARNING("target not halted");
428 return ERROR_TARGET_NOT_HALTED
;
431 if (!debug_execution
) {
432 target_free_all_working_areas(target
);
433 mips_m4k_enable_breakpoints(target
);
434 mips_m4k_enable_watchpoints(target
);
437 /* current = 1: continue on current pc, otherwise continue at <address> */
439 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
440 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
441 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
444 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
445 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
450 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
452 mips32_restore_context(target
);
454 /* the front-end may request us not to handle breakpoints */
455 if (handle_breakpoints
) {
456 /* Single step past breakpoint at current address */
457 breakpoint
= breakpoint_find(target
, resume_pc
);
459 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
460 mips_m4k_unset_breakpoint(target
, breakpoint
);
461 mips_m4k_single_step_core(target
);
462 mips_m4k_set_breakpoint(target
, breakpoint
);
466 /* enable interrupts if we are running */
467 mips32_enable_interrupts(target
, !debug_execution
);
469 /* exit debug mode */
470 mips_ejtag_exit_debug(ejtag_info
);
471 target
->debug_reason
= DBG_REASON_NOTHALTED
;
473 /* registers are now invalid */
474 register_cache_invalidate(mips32
->core_cache
);
476 if (!debug_execution
) {
477 target
->state
= TARGET_RUNNING
;
478 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
479 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
481 target
->state
= TARGET_DEBUG_RUNNING
;
482 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
483 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
489 static int mips_m4k_resume(struct target
*target
, int current
,
490 uint32_t address
, int handle_breakpoints
, int debug_execution
)
492 int retval
= ERROR_OK
;
494 /* dummy resume for smp toggle in order to reduce gdb impact */
495 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
496 /* simulate a start and halt of target */
497 target
->gdb_service
->target
= NULL
;
498 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
499 /* fake resume at next poll we play the target core[1], see poll*/
500 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
504 retval
= mips_m4k_internal_restore(target
, current
, address
,
508 if (retval
== ERROR_OK
&& target
->smp
) {
509 target
->gdb_service
->core
[0] = -1;
510 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
516 static int mips_m4k_step(struct target
*target
, int current
,
517 uint32_t address
, int handle_breakpoints
)
519 /* get pointers to arch-specific information */
520 struct mips32_common
*mips32
= target_to_mips32(target
);
521 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
522 struct breakpoint
*breakpoint
= NULL
;
524 if (target
->state
!= TARGET_HALTED
) {
525 LOG_WARNING("target not halted");
526 return ERROR_TARGET_NOT_HALTED
;
529 /* current = 1: continue on current pc, otherwise continue at <address> */
531 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
532 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
533 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
536 /* the front-end may request us not to handle breakpoints */
537 if (handle_breakpoints
) {
538 breakpoint
= breakpoint_find(target
,
539 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
541 mips_m4k_unset_breakpoint(target
, breakpoint
);
544 /* restore context */
545 mips32_restore_context(target
);
547 /* configure single step mode */
548 mips_ejtag_config_step(ejtag_info
, 1);
550 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
552 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
554 /* disable interrupts while stepping */
555 mips32_enable_interrupts(target
, 0);
557 /* exit debug mode */
558 mips_ejtag_exit_debug(ejtag_info
);
560 /* registers are now invalid */
561 register_cache_invalidate(mips32
->core_cache
);
563 LOG_DEBUG("target stepped ");
564 mips_m4k_debug_entry(target
);
567 mips_m4k_set_breakpoint(target
, breakpoint
);
569 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
574 static void mips_m4k_enable_breakpoints(struct target
*target
)
576 struct breakpoint
*breakpoint
= target
->breakpoints
;
578 /* set any pending breakpoints */
580 if (breakpoint
->set
== 0)
581 mips_m4k_set_breakpoint(target
, breakpoint
);
582 breakpoint
= breakpoint
->next
;
586 static int mips_m4k_set_breakpoint(struct target
*target
,
587 struct breakpoint
*breakpoint
)
589 struct mips32_common
*mips32
= target_to_mips32(target
);
590 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
591 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
594 if (breakpoint
->set
) {
595 LOG_WARNING("breakpoint already set");
599 if (breakpoint
->type
== BKPT_HARD
) {
602 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
604 if (bp_num
>= mips32
->num_inst_bpoints
) {
605 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
606 breakpoint
->unique_id
);
607 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
609 breakpoint
->set
= bp_num
+ 1;
610 comparator_list
[bp_num
].used
= 1;
611 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
613 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
614 * Warning: there is no IB ASID registers in 2.0.
615 * Do not set it! :) */
616 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
617 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
619 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
620 comparator_list
[bp_num
].bp_value
);
621 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
622 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
623 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
624 ejtag_info
->ejtag_ibc_offs
, 1);
625 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
626 breakpoint
->unique_id
,
627 bp_num
, comparator_list
[bp_num
].bp_value
);
628 } else if (breakpoint
->type
== BKPT_SOFT
) {
629 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
630 if (breakpoint
->length
== 4) {
631 uint32_t verify
= 0xffffffff;
633 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
634 breakpoint
->orig_instr
);
635 if (retval
!= ERROR_OK
)
637 retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
);
638 if (retval
!= ERROR_OK
)
641 retval
= target_read_u32(target
, breakpoint
->address
, &verify
);
642 if (retval
!= ERROR_OK
)
644 if (verify
!= MIPS32_SDBBP
) {
645 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
646 " - check that memory is read/writable", breakpoint
->address
);
650 uint16_t verify
= 0xffff;
652 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
653 breakpoint
->orig_instr
);
654 if (retval
!= ERROR_OK
)
656 retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
);
657 if (retval
!= ERROR_OK
)
660 retval
= target_read_u16(target
, breakpoint
->address
, &verify
);
661 if (retval
!= ERROR_OK
)
663 if (verify
!= MIPS16_SDBBP
) {
664 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
665 " - check that memory is read/writable", breakpoint
->address
);
670 breakpoint
->set
= 20; /* Any nice value but 0 */
676 static int mips_m4k_unset_breakpoint(struct target
*target
,
677 struct breakpoint
*breakpoint
)
679 /* get pointers to arch-specific information */
680 struct mips32_common
*mips32
= target_to_mips32(target
);
681 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
682 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
685 if (!breakpoint
->set
) {
686 LOG_WARNING("breakpoint not set");
690 if (breakpoint
->type
== BKPT_HARD
) {
691 int bp_num
= breakpoint
->set
- 1;
692 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
)) {
693 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
694 breakpoint
->unique_id
);
697 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
698 breakpoint
->unique_id
,
700 comparator_list
[bp_num
].used
= 0;
701 comparator_list
[bp_num
].bp_value
= 0;
702 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
703 ejtag_info
->ejtag_ibc_offs
, 0);
706 /* restore original instruction (kept in target endianness) */
707 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
708 if (breakpoint
->length
== 4) {
709 uint32_t current_instr
;
711 /* check that user program has not modified breakpoint instruction */
712 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
713 (uint8_t *)¤t_instr
);
714 if (retval
!= ERROR_OK
)
718 * target_read_memory() gets us data in _target_ endianess.
719 * If we want to use this data on the host for comparisons with some macros
720 * we must first transform it to _host_ endianess using target_buffer_get_u32().
722 current_instr
= target_buffer_get_u32(target
, (uint8_t *)¤t_instr
);
724 if (current_instr
== MIPS32_SDBBP
) {
725 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
726 breakpoint
->orig_instr
);
727 if (retval
!= ERROR_OK
)
731 uint16_t current_instr
;
733 /* check that user program has not modified breakpoint instruction */
734 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
735 (uint8_t *)¤t_instr
);
736 if (retval
!= ERROR_OK
)
738 current_instr
= target_buffer_get_u16(target
, (uint8_t *)¤t_instr
);
739 if (current_instr
== MIPS16_SDBBP
) {
740 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
741 breakpoint
->orig_instr
);
742 if (retval
!= ERROR_OK
)
752 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
754 struct mips32_common
*mips32
= target_to_mips32(target
);
756 if (breakpoint
->type
== BKPT_HARD
) {
757 if (mips32
->num_inst_bpoints_avail
< 1) {
758 LOG_INFO("no hardware breakpoint available");
759 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
762 mips32
->num_inst_bpoints_avail
--;
765 return mips_m4k_set_breakpoint(target
, breakpoint
);
768 static int mips_m4k_remove_breakpoint(struct target
*target
,
769 struct breakpoint
*breakpoint
)
771 /* get pointers to arch-specific information */
772 struct mips32_common
*mips32
= target_to_mips32(target
);
774 if (target
->state
!= TARGET_HALTED
) {
775 LOG_WARNING("target not halted");
776 return ERROR_TARGET_NOT_HALTED
;
780 mips_m4k_unset_breakpoint(target
, breakpoint
);
782 if (breakpoint
->type
== BKPT_HARD
)
783 mips32
->num_inst_bpoints_avail
++;
788 static int mips_m4k_set_watchpoint(struct target
*target
,
789 struct watchpoint
*watchpoint
)
791 struct mips32_common
*mips32
= target_to_mips32(target
);
792 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
793 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
796 * watchpoint enabled, ignore all byte lanes in value register
797 * and exclude both load and store accesses from watchpoint
798 * condition evaluation
800 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
801 (0xff << EJTAG_DBCn_BLM_SHIFT
);
803 if (watchpoint
->set
) {
804 LOG_WARNING("watchpoint already set");
808 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
810 if (wp_num
>= mips32
->num_data_bpoints
) {
811 LOG_ERROR("Can not find free FP Comparator");
815 if (watchpoint
->length
!= 4) {
816 LOG_ERROR("Only watchpoints of length 4 are supported");
817 return ERROR_TARGET_UNALIGNED_ACCESS
;
820 if (watchpoint
->address
% 4) {
821 LOG_ERROR("Watchpoints address should be word aligned");
822 return ERROR_TARGET_UNALIGNED_ACCESS
;
825 switch (watchpoint
->rw
) {
827 enable
&= ~EJTAG_DBCn_NOLB
;
830 enable
&= ~EJTAG_DBCn_NOSB
;
833 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
836 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
839 watchpoint
->set
= wp_num
+ 1;
840 comparator_list
[wp_num
].used
= 1;
841 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
843 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
844 * There is as well no ASID register support. */
845 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
846 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
848 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
849 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
851 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
852 comparator_list
[wp_num
].bp_value
);
853 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
854 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
856 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
857 ejtag_info
->ejtag_dbc_offs
, enable
);
858 /* TODO: probably this value is ignored on 2.0 */
859 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
860 ejtag_info
->ejtag_dbv_offs
, 0);
861 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
866 static int mips_m4k_unset_watchpoint(struct target
*target
,
867 struct watchpoint
*watchpoint
)
869 /* get pointers to arch-specific information */
870 struct mips32_common
*mips32
= target_to_mips32(target
);
871 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
872 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
874 if (!watchpoint
->set
) {
875 LOG_WARNING("watchpoint not set");
879 int wp_num
= watchpoint
->set
- 1;
880 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
)) {
881 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
884 comparator_list
[wp_num
].used
= 0;
885 comparator_list
[wp_num
].bp_value
= 0;
886 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
887 ejtag_info
->ejtag_dbc_offs
, 0);
893 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
895 struct mips32_common
*mips32
= target_to_mips32(target
);
897 if (mips32
->num_data_bpoints_avail
< 1) {
898 LOG_INFO("no hardware watchpoints available");
899 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
902 mips32
->num_data_bpoints_avail
--;
904 mips_m4k_set_watchpoint(target
, watchpoint
);
908 static int mips_m4k_remove_watchpoint(struct target
*target
,
909 struct watchpoint
*watchpoint
)
911 /* get pointers to arch-specific information */
912 struct mips32_common
*mips32
= target_to_mips32(target
);
914 if (target
->state
!= TARGET_HALTED
) {
915 LOG_WARNING("target not halted");
916 return ERROR_TARGET_NOT_HALTED
;
920 mips_m4k_unset_watchpoint(target
, watchpoint
);
922 mips32
->num_data_bpoints_avail
++;
927 static void mips_m4k_enable_watchpoints(struct target
*target
)
929 struct watchpoint
*watchpoint
= target
->watchpoints
;
931 /* set any pending watchpoints */
933 if (watchpoint
->set
== 0)
934 mips_m4k_set_watchpoint(target
, watchpoint
);
935 watchpoint
= watchpoint
->next
;
939 static int mips_m4k_read_memory(struct target
*target
, uint32_t address
,
940 uint32_t size
, uint32_t count
, uint8_t *buffer
)
942 struct mips32_common
*mips32
= target_to_mips32(target
);
943 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
945 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
946 address
, size
, count
);
948 if (target
->state
!= TARGET_HALTED
) {
949 LOG_WARNING("target not halted");
950 return ERROR_TARGET_NOT_HALTED
;
953 /* sanitize arguments */
954 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
955 return ERROR_COMMAND_SYNTAX_ERROR
;
957 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
958 return ERROR_TARGET_UNALIGNED_ACCESS
;
960 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
964 t
= malloc(count
* size
* sizeof(uint8_t));
966 LOG_ERROR("Out of memory");
972 /* if noDMA off, use DMAACC mode for memory read */
974 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
975 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
977 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
979 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
980 /* endianness, but byte array should represent target endianness */
981 if (ERROR_OK
== retval
) {
984 target_buffer_set_u32_array(target
, buffer
, count
, t
);
987 target_buffer_set_u16_array(target
, buffer
, count
, t
);
992 if ((size
> 1) && (t
!= NULL
))
998 static int mips_m4k_write_memory(struct target
*target
, uint32_t address
,
999 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1001 struct mips32_common
*mips32
= target_to_mips32(target
);
1002 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1004 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1005 address
, size
, count
);
1007 if (target
->state
!= TARGET_HALTED
) {
1008 LOG_WARNING("target not halted");
1009 return ERROR_TARGET_NOT_HALTED
;
1012 if (size
== 4 && count
> 32) {
1013 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1014 if (retval
== ERROR_OK
)
1016 LOG_WARNING("Falling back to non-bulk write");
1019 /* sanitize arguments */
1020 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1021 return ERROR_COMMAND_SYNTAX_ERROR
;
1023 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1024 return ERROR_TARGET_UNALIGNED_ACCESS
;
1026 /** correct endianess if we have word or hword access */
1029 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1030 /* endianness, but byte array represents target endianness */
1031 t
= malloc(count
* size
* sizeof(uint8_t));
1033 LOG_ERROR("Out of memory");
1039 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1042 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1048 /* if noDMA off, use DMAACC mode for memory write */
1050 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1051 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
1053 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
1058 if (ERROR_OK
!= retval
)
1064 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1065 struct target
*target
)
1067 mips32_build_reg_cache(target
);
1072 static int mips_m4k_init_arch_info(struct target
*target
,
1073 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1075 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1077 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1079 /* initialize mips4k specific info */
1080 mips32_init_arch_info(target
, mips32
, tap
);
1081 mips32
->arch_info
= mips_m4k
;
1086 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1088 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1090 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1095 static int mips_m4k_examine(struct target
*target
)
1098 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1099 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1100 uint32_t idcode
= 0;
1102 if (!target_was_examined(target
)) {
1103 retval
= mips_ejtag_get_idcode(ejtag_info
, &idcode
);
1104 if (retval
!= ERROR_OK
)
1106 ejtag_info
->idcode
= idcode
;
1108 if (((idcode
>> 1) & 0x7FF) == 0x29) {
1109 /* we are using a pic32mx so select ejtag port
1110 * as it is not selected by default */
1111 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1112 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1113 mips_m4k
->is_pic32mx
= true;
1117 /* init rest of ejtag interface */
1118 retval
= mips_ejtag_init(ejtag_info
);
1119 if (retval
!= ERROR_OK
)
1122 retval
= mips32_examine(target
);
1123 if (retval
!= ERROR_OK
)
1129 static int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
,
1130 uint32_t count
, const uint8_t *buffer
)
1132 struct mips32_common
*mips32
= target_to_mips32(target
);
1133 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1137 LOG_DEBUG("address: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, count
);
1139 /* check alignment */
1141 return ERROR_TARGET_UNALIGNED_ACCESS
;
1143 if (mips32
->fast_data_area
== NULL
) {
1144 /* Get memory for block write handler
1145 * we preserve this area between calls and gain a speed increase
1146 * of about 3kb/sec when writing flash
1147 * this will be released/nulled by the system when the target is resumed or reset */
1148 retval
= target_alloc_working_area(target
,
1149 MIPS32_FASTDATA_HANDLER_SIZE
,
1150 &mips32
->fast_data_area
);
1151 if (retval
!= ERROR_OK
) {
1152 LOG_ERROR("No working area available");
1156 /* reset fastadata state so the algo get reloaded */
1157 ejtag_info
->fast_access_save
= -1;
1160 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1161 /* but byte array represents target endianness */
1163 t
= malloc(count
* sizeof(uint32_t));
1165 LOG_ERROR("Out of memory");
1169 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1171 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1177 if (retval
!= ERROR_OK
)
1178 LOG_ERROR("Fastdata access Failed");
1183 static int mips_m4k_verify_pointer(struct command_context
*cmd_ctx
,
1184 struct mips_m4k_common
*mips_m4k
)
1186 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1187 command_print(cmd_ctx
, "target is not an MIPS_M4K");
1188 return ERROR_TARGET_INVALID
;
1193 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1196 struct target
*target
= get_current_target(CMD_CTX
);
1197 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1198 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1200 retval
= mips_m4k_verify_pointer(CMD_CTX
, mips_m4k
);
1201 if (retval
!= ERROR_OK
)
1204 if (target
->state
!= TARGET_HALTED
) {
1205 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1209 /* two or more argument, access a single register/select (write if third argument is given) */
1211 return ERROR_COMMAND_SYNTAX_ERROR
;
1213 uint32_t cp0_reg
, cp0_sel
;
1214 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1215 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1217 if (CMD_ARGC
== 2) {
1219 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1220 if (retval
!= ERROR_OK
) {
1221 command_print(CMD_CTX
,
1222 "couldn't access reg %" PRIi32
,
1226 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1227 cp0_reg
, cp0_sel
, value
);
1229 } else if (CMD_ARGC
== 3) {
1231 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1232 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1233 if (retval
!= ERROR_OK
) {
1234 command_print(CMD_CTX
,
1235 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
1239 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1240 cp0_reg
, cp0_sel
, value
);
1247 COMMAND_HANDLER(mips_m4k_handle_smp_off_command
)
1249 struct target
*target
= get_current_target(CMD_CTX
);
1250 /* check target is an smp target */
1251 struct target_list
*head
;
1252 struct target
*curr
;
1253 head
= target
->head
;
1255 if (head
!= (struct target_list
*)NULL
) {
1256 while (head
!= (struct target_list
*)NULL
) {
1257 curr
= head
->target
;
1261 /* fixes the target display to the debugger */
1262 target
->gdb_service
->target
= target
;
1267 COMMAND_HANDLER(mips_m4k_handle_smp_on_command
)
1269 struct target
*target
= get_current_target(CMD_CTX
);
1270 struct target_list
*head
;
1271 struct target
*curr
;
1272 head
= target
->head
;
1273 if (head
!= (struct target_list
*)NULL
) {
1275 while (head
!= (struct target_list
*)NULL
) {
1276 curr
= head
->target
;
1284 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command
)
1286 struct target
*target
= get_current_target(CMD_CTX
);
1287 int retval
= ERROR_OK
;
1288 struct target_list
*head
;
1289 head
= target
->head
;
1290 if (head
!= (struct target_list
*)NULL
) {
1291 if (CMD_ARGC
== 1) {
1293 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
1294 if (ERROR_OK
!= retval
)
1296 target
->gdb_service
->core
[1] = coreid
;
1299 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
1300 , target
->gdb_service
->core
[1]);
1305 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1307 struct target
*target
= get_current_target(CMD_CTX
);
1308 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1309 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1312 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1313 else if (CMD_ARGC
> 1)
1314 return ERROR_COMMAND_SYNTAX_ERROR
;
1316 command_print(CMD_CTX
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1317 if (ejtag_info
->scan_delay
>= 20000000) {
1318 ejtag_info
->mode
= 0;
1319 command_print(CMD_CTX
, "running in legacy mode");
1321 ejtag_info
->mode
= 1;
1322 command_print(CMD_CTX
, "running in fast queued mode");
1328 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1331 .handler
= mips_m4k_handle_cp0_command
,
1332 .mode
= COMMAND_EXEC
,
1333 .usage
= "regnum [value]",
1334 .help
= "display/modify cp0 register",
1338 .handler
= mips_m4k_handle_smp_off_command
,
1339 .mode
= COMMAND_EXEC
,
1340 .help
= "Stop smp handling",
1345 .handler
= mips_m4k_handle_smp_on_command
,
1346 .mode
= COMMAND_EXEC
,
1347 .help
= "Restart smp handling",
1352 .handler
= mips_m4k_handle_smp_gdb_command
,
1353 .mode
= COMMAND_EXEC
,
1354 .help
= "display/fix current core played to gdb",
1358 .name
= "scan_delay",
1359 .handler
= mips_m4k_handle_scan_delay_command
,
1360 .mode
= COMMAND_ANY
,
1361 .help
= "display/set scan delay in nano seconds",
1364 COMMAND_REGISTRATION_DONE
1367 const struct command_registration mips_m4k_command_handlers
[] = {
1369 .chain
= mips32_command_handlers
,
1373 .mode
= COMMAND_ANY
,
1374 .help
= "mips_m4k command group",
1376 .chain
= mips_m4k_exec_command_handlers
,
1378 COMMAND_REGISTRATION_DONE
1381 struct target_type mips_m4k_target
= {
1384 .poll
= mips_m4k_poll
,
1385 .arch_state
= mips32_arch_state
,
1387 .halt
= mips_m4k_halt
,
1388 .resume
= mips_m4k_resume
,
1389 .step
= mips_m4k_step
,
1391 .assert_reset
= mips_m4k_assert_reset
,
1392 .deassert_reset
= mips_m4k_deassert_reset
,
1394 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1396 .read_memory
= mips_m4k_read_memory
,
1397 .write_memory
= mips_m4k_write_memory
,
1398 .checksum_memory
= mips32_checksum_memory
,
1399 .blank_check_memory
= mips32_blank_check_memory
,
1401 .run_algorithm
= mips32_run_algorithm
,
1403 .add_breakpoint
= mips_m4k_add_breakpoint
,
1404 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1405 .add_watchpoint
= mips_m4k_add_watchpoint
,
1406 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1408 .commands
= mips_m4k_command_handlers
,
1409 .target_create
= mips_m4k_target_create
,
1410 .init_target
= mips_m4k_init_target
,
1411 .examine
= mips_m4k_examine
,
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