1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
37 /* forward declarations */
38 int mips_m4k_poll(target_t
*target
);
39 int mips_m4k_halt(struct target_s
*target
);
40 int mips_m4k_soft_reset_halt(struct target_s
*target
);
41 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
44 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
45 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
46 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int mips_m4k_quit(void);
48 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
50 int mips_m4k_examine(struct target_s
*target
);
51 int mips_m4k_assert_reset(target_t
*target
);
52 int mips_m4k_deassert_reset(target_t
*target
);
54 target_type_t mips_m4k_target
=
58 .poll
= mips_m4k_poll
,
59 .arch_state
= mips32_arch_state
,
61 .target_request_data
= NULL
,
63 .halt
= mips_m4k_halt
,
64 .resume
= mips_m4k_resume
,
65 .step
= mips_m4k_step
,
67 .assert_reset
= mips_m4k_assert_reset
,
68 .deassert_reset
= mips_m4k_deassert_reset
,
69 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
71 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
73 .read_memory
= mips_m4k_read_memory
,
74 .write_memory
= mips_m4k_write_memory
,
75 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
76 .checksum_memory
= NULL
,
77 .blank_check_memory
= NULL
,
79 .run_algorithm
= mips32_run_algorithm
,
81 .add_breakpoint
= mips_m4k_add_breakpoint
,
82 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
83 .add_watchpoint
= mips_m4k_add_watchpoint
,
84 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
86 .register_commands
= mips_m4k_register_commands
,
87 .target_create
= mips_m4k_target_create
,
88 .init_target
= mips_m4k_init_target
,
89 .examine
= mips_m4k_examine
,
93 int mips_m4k_debug_entry(target_t
*target
)
96 mips32_common_t
*mips32
= target
->arch_info
;
97 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
99 /* read debug register */
100 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
102 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
103 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
105 // if (cortex_m3->nvic_dfsr & DFSR_BKPT)
107 // target->debug_reason = DBG_REASON_BREAKPOINT;
108 // if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
109 // target->debug_reason = DBG_REASON_WPTANDBKPT;
111 // else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
112 // target->debug_reason = DBG_REASON_WATCHPOINT;
115 if (debug_reg
& EJTAG_DEBUG_DSS
)
117 /* stopped due to single step - clear step bit */
118 mips_ejtag_config_step(ejtag_info
, 0);
121 mips32_save_context(target
);
123 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
124 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
125 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
130 int mips_m4k_poll(target_t
*target
)
133 mips32_common_t
*mips32
= target
->arch_info
;
134 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
135 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
137 /* read ejtag control reg */
138 jtag_add_end_state(TAP_RTI
);
139 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
140 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
142 /* clear this bit before handling polling
143 * as after reset registers will read zero */
144 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
146 /* we have detected a reset, clear flag
147 * otherwise ejtag will not work */
148 jtag_add_end_state(TAP_RTI
);
149 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
151 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
152 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
153 LOG_DEBUG("Reset Detected");
156 /* check for processor halted */
157 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
159 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
161 jtag_add_end_state(TAP_RTI
);
162 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
164 target
->state
= TARGET_HALTED
;
166 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
169 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
171 else if (target
->state
== TARGET_DEBUG_RUNNING
)
173 target
->state
= TARGET_HALTED
;
175 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
178 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
183 target
->state
= TARGET_RUNNING
;
186 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
191 int mips_m4k_halt(struct target_s
*target
)
193 mips32_common_t
*mips32
= target
->arch_info
;
194 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
196 LOG_DEBUG("target->state: %s",
197 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
199 if (target
->state
== TARGET_HALTED
)
201 LOG_DEBUG("target was already halted");
205 if (target
->state
== TARGET_UNKNOWN
)
207 LOG_WARNING("target was in unknown state when halt was requested");
210 if (target
->state
== TARGET_RESET
)
212 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
214 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
215 return ERROR_TARGET_FAILURE
;
219 /* we came here in a reset_halt or reset_init sequence
220 * debug entry was already prepared in mips32_prepare_reset_halt()
222 target
->debug_reason
= DBG_REASON_DBGRQ
;
228 /* break processor */
229 mips_ejtag_enter_debug(ejtag_info
);
231 target
->debug_reason
= DBG_REASON_DBGRQ
;
236 int mips_m4k_assert_reset(target_t
*target
)
238 mips32_common_t
*mips32
= target
->arch_info
;
239 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
240 mips_m4k_common_t
*mips_m4k
= mips32
->arch_info
;
242 LOG_DEBUG("target->state: %s",
243 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
245 if (!(jtag_reset_config
& RESET_HAS_SRST
))
247 LOG_ERROR("Can't assert SRST");
251 if (target
->reset_halt
)
253 /* use hardware to catch reset */
254 jtag_add_end_state(TAP_RTI
);
255 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
259 jtag_add_end_state(TAP_RTI
);
260 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
263 if (strcmp(mips_m4k
->variant
, "ejtag_srst") == 0)
265 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
266 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
267 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
268 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
272 /* here we should issue a srst only, but we may have to assert trst as well */
273 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
275 jtag_add_reset(1, 1);
279 jtag_add_reset(0, 1);
283 target
->state
= TARGET_RESET
;
284 jtag_add_sleep(50000);
286 mips32_invalidate_core_regs(target
);
288 if (target
->reset_halt
)
291 if ((retval
= target_halt(target
))!=ERROR_OK
)
298 int mips_m4k_deassert_reset(target_t
*target
)
300 LOG_DEBUG("target->state: %s",
301 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
303 /* deassert reset lines */
304 jtag_add_reset(0, 0);
309 int mips_m4k_soft_reset_halt(struct target_s
*target
)
315 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
317 mips32_common_t
*mips32
= target
->arch_info
;
318 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
319 breakpoint_t
*breakpoint
= NULL
;
322 if (target
->state
!= TARGET_HALTED
)
324 LOG_WARNING("target not halted");
325 return ERROR_TARGET_NOT_HALTED
;
328 if (!debug_execution
)
330 target_free_all_working_areas(target
);
331 mips_m4k_enable_breakpoints(target
);
332 mips_m4k_enable_watchpoints(target
);
335 /* current = 1: continue on current pc, otherwise continue at <address> */
338 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
339 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
340 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
343 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
345 mips32_restore_context(target
);
347 /* the front-end may request us not to handle breakpoints */
348 if (handle_breakpoints
)
350 /* Single step past breakpoint at current address */
351 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
353 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
354 mips_m4k_unset_breakpoint(target
, breakpoint
);
355 //mips_m4k_single_step_core(target);
356 mips_m4k_set_breakpoint(target
, breakpoint
);
360 /* exit debug mode - enable interrupts if required */
361 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
363 /* registers are now invalid */
364 mips32_invalidate_core_regs(target
);
366 if (!debug_execution
)
368 target
->state
= TARGET_RUNNING
;
369 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
370 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
374 target
->state
= TARGET_DEBUG_RUNNING
;
375 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
376 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
382 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
384 /* get pointers to arch-specific information */
385 mips32_common_t
*mips32
= target
->arch_info
;
386 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
387 breakpoint_t
*breakpoint
= NULL
;
389 if (target
->state
!= TARGET_HALTED
)
391 LOG_WARNING("target not halted");
392 return ERROR_TARGET_NOT_HALTED
;
395 /* current = 1: continue on current pc, otherwise continue at <address> */
397 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
399 /* the front-end may request us not to handle breakpoints */
400 if (handle_breakpoints
)
401 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
402 mips_m4k_unset_breakpoint(target
, breakpoint
);
404 /* restore context */
405 mips32_restore_context(target
);
407 /* configure single step mode */
408 mips_ejtag_config_step(ejtag_info
, 1);
410 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
412 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
414 /* exit debug mode */
415 mips_ejtag_exit_debug(ejtag_info
, 1);
417 /* registers are now invalid */
418 mips32_invalidate_core_regs(target
);
421 mips_m4k_set_breakpoint(target
, breakpoint
);
423 LOG_DEBUG("target stepped ");
425 mips_m4k_debug_entry(target
);
426 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
431 void mips_m4k_enable_breakpoints(struct target_s
*target
)
433 breakpoint_t
*breakpoint
= target
->breakpoints
;
435 /* set any pending breakpoints */
438 if (breakpoint
->set
== 0)
439 mips_m4k_set_breakpoint(target
, breakpoint
);
440 breakpoint
= breakpoint
->next
;
444 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
450 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
456 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
462 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
468 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
474 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
480 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
486 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
492 void mips_m4k_enable_watchpoints(struct target_s
*target
)
494 watchpoint_t
*watchpoint
= target
->watchpoints
;
496 /* set any pending watchpoints */
499 if (watchpoint
->set
== 0)
500 mips_m4k_set_watchpoint(target
, watchpoint
);
501 watchpoint
= watchpoint
->next
;
505 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
507 mips32_common_t
*mips32
= target
->arch_info
;
508 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
510 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
512 if (target
->state
!= TARGET_HALTED
)
514 LOG_WARNING("target not halted");
515 return ERROR_TARGET_NOT_HALTED
;
518 /* sanitize arguments */
519 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
520 return ERROR_INVALID_ARGUMENTS
;
522 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
523 return ERROR_TARGET_UNALIGNED_ACCESS
;
530 /* if noDMA off, use DMAACC mode for memory read */
531 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
532 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
534 return mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
536 LOG_ERROR("BUG: we shouldn't get here");
544 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
546 mips32_common_t
*mips32
= target
->arch_info
;
547 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
549 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
551 if (target
->state
!= TARGET_HALTED
)
553 LOG_WARNING("target not halted");
554 return ERROR_TARGET_NOT_HALTED
;
557 /* sanitize arguments */
558 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
559 return ERROR_INVALID_ARGUMENTS
;
561 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
562 return ERROR_TARGET_UNALIGNED_ACCESS
;
569 /* if noDMA off, use DMAACC mode for memory write */
570 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
571 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
573 mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
576 LOG_ERROR("BUG: we shouldn't get here");
584 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
588 retval
= mips32_register_commands(cmd_ctx
);
592 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
594 mips32_build_reg_cache(target
);
599 int mips_m4k_quit(void)
604 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, int chain_pos
, const char *variant
)
606 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
610 mips_m4k
->variant
= strdup(variant
);
614 mips_m4k
->variant
= strdup("");
617 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
619 /* initialize mips4k specific info */
620 mips32_init_arch_info(target
, mips32
, chain_pos
, variant
);
621 mips32
->arch_info
= mips_m4k
;
626 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
628 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
630 mips_m4k_init_arch_info(target
, mips_m4k
, target
->chain_position
, target
->variant
);
635 int mips_m4k_examine(struct target_s
*target
)
638 mips32_common_t
*mips32
= target
->arch_info
;
639 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
642 target
->type
->examined
= 1;
644 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
646 if (((idcode
>> 1) & 0x7FF) == 0x29)
648 /* we are using a pic32mx so select ejtag port
649 * as it is not selected by default */
650 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
651 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
654 /* init rest of ejtag interface */
655 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
661 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
663 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
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