1 /***************************************************************************
2 * Copyright (C) 2011 by Julius Baxter *
3 * julius@opencores.org *
5 * Copyright (C) 2013 by Marek Czerski *
6 * ma.czerski@gmail.com *
8 * Copyright (C) 2013 by Franck Jullien *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
26 #ifndef OPENOCD_TARGET_OPENRISC_OR1K_H
27 #define OPENOCD_TARGET_OPENRISC_OR1K_H
33 #include <target/target.h>
35 /* SPR groups start address */
36 #define GROUP0 (0 << 11)
37 #define GROUP1 (1 << 11)
38 #define GROUP2 (2 << 11)
39 #define GROUP3 (3 << 11)
40 #define GROUP4 (4 << 11)
41 #define GROUP5 (5 << 11)
42 #define GROUP6 (6 << 11)
43 #define GROUP7 (7 << 11)
44 #define GROUP8 (8 << 11)
45 #define GROUP9 (9 << 11)
46 #define GROUP10 (10 << 11)
91 int or1k_jtag_module_selected
;
92 uint8_t *current_reg_idx
;
93 struct or1k_tap_ip
*tap_ip
;
94 struct or1k_du
*du_core
;
95 struct target
*target
;
99 struct or1k_jtag jtag
;
100 struct reg_cache
*core_cache
;
101 uint32_t core_regs
[OR1KNUMCOREREGS
];
103 struct or1k_core_reg
*arch_info
;
106 static inline struct or1k_common
*
107 target_to_or1k(struct target
*target
)
109 return (struct or1k_common
*)target
->arch_info
;
112 struct or1k_core_reg
{
114 uint32_t list_num
; /* Index in register cache */
115 uint32_t spr_num
; /* Number in architecture's SPR space */
116 struct target
*target
;
117 struct or1k_common
*or1k_common
;
118 const char *feature
; /* feature name in XML tdesc file */
119 const char *group
; /* register group in XML tdesc file */
122 struct or1k_core_reg_init
{
124 uint32_t spr_num
; /* Number in architecture's SPR space */
125 const char *feature
; /* feature name in XML tdesc file */
126 const char *group
; /* register group in XML tdesc file */
129 /* ORBIS32 Trap instruction */
130 #define OR1K_TRAP_INSTR 0x21000001
132 enum or1k_debug_reg_nums
{
133 OR1K_DEBUG_REG_DMR1
= 0,
135 OR1K_DEBUG_REG_DCWR0
,
136 OR1K_DEBUG_REG_DCWR1
,
142 #define NO_SINGLE_STEP 0
143 #define SINGLE_STEP 1
145 /* OR1K Debug registers and bits needed for resuming */
146 #define OR1K_DEBUG_REG_BASE GROUP6 /* Debug registers Base address */
147 #define OR1K_DMR1_CPU_REG_ADD (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
148 #define OR1K_DMR1_ST 0x00400000 /* Single-step trace */
149 #define OR1K_DMR1_BT 0x00800000 /* Branch trace */
150 #define OR1K_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
151 #define OR1K_DSR_TE 0x00002000 /* Trap exception */
153 /* OR1K Instruction cache registers needed for invalidating instruction
154 * memory during adding and removing breakpoints.
156 #define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2) /* IC Block Invalidate Register 0x2002 */
158 #endif /* OPENOCD_TARGET_OPENRISC_OR1K_H */
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