1 /***************************************************************************
2 * Copyright (C) 2013-2014 by Franck Jullien *
5 * Inspired from adv_jtag_bridge which is: *
6 * Copyright (C) 2008-2010 Nathan Yawn *
7 * nyawn@opencores.net *
9 * And the Mohor interface version of this file which is: *
10 * Copyright (C) 2011 by Julius Baxter *
11 * julius@opencores.org *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 ***************************************************************************/
34 #include "jsp_server.h"
36 #include <target/target.h>
37 #include <jtag/jtag.h>
39 #define JSP_BANNER "\n\r" \
40 "******************************\n\r" \
41 "** JTAG Serial Port **\n\r" \
42 "******************************\n\r" \
47 /* This an option to the adv debug unit.
48 * If this is defined, status bits will be skipped on burst
49 * reads and writes to improve download speeds.
50 * This option must match the RTL configured option.
52 #define ADBG_USE_HISPEED 1
54 /* This an option to the adv debug unit.
55 * If this is defined, the JTAG Serial Port Server is started.
56 * This option must match the RTL configured option.
58 #define ENABLE_JSP_SERVER 2
60 /* Define this if you intend to use the JSP in a system with multiple
61 * devices on the JTAG chain
63 #define ENABLE_JSP_MULTI 4
65 /* Definitions for the top-level debug unit. This really just consists
66 * of a single register, used to select the active debug module ("chain").
68 #define DBG_MODULE_SELECT_REG_SIZE 2
69 #define DBG_MAX_MODULES 4
77 /* CPU control register bits mask */
78 #define DBG_CPU_CR_STALL 0x01
79 #define DBG_CPU_CR_RESET 0x02
81 /* Polynomial for the CRC calculation
82 * Yes, it's backwards. Yes, this is on purpose.
83 * The hardware is designed this way to save on logic and routing,
84 * and it's really all the same to us here.
86 #define ADBG_CRC_POLY 0xedb88320
88 /* These are for the internal registers in the Wishbone module
89 * The first is the length of the index register,
90 * the indexes of the various registers are defined after that.
92 #define DBG_WB_REG_SEL_LEN 1
93 #define DBG_WB_REG_ERROR 0
95 /* Opcode definitions for the Wishbone module. */
96 #define DBG_WB_OPCODE_LEN 4
97 #define DBG_WB_CMD_NOP 0x0
98 #define DBG_WB_CMD_BWRITE8 0x1
99 #define DBG_WB_CMD_BWRITE16 0x2
100 #define DBG_WB_CMD_BWRITE32 0x3
101 #define DBG_WB_CMD_BREAD8 0x5
102 #define DBG_WB_CMD_BREAD16 0x6
103 #define DBG_WB_CMD_BREAD32 0x7
104 #define DBG_WB_CMD_IREG_WR 0x9
105 #define DBG_WB_CMD_IREG_SEL 0xd
107 /* Internal register definitions for the CPU0 module. */
108 #define DBG_CPU0_REG_SEL_LEN 1
109 #define DBG_CPU0_REG_STATUS 0
111 /* Opcode definitions for the first CPU module. */
112 #define DBG_CPU0_OPCODE_LEN 4
113 #define DBG_CPU0_CMD_NOP 0x0
114 #define DBG_CPU0_CMD_BWRITE32 0x3
115 #define DBG_CPU0_CMD_BREAD32 0x7
116 #define DBG_CPU0_CMD_IREG_WR 0x9
117 #define DBG_CPU0_CMD_IREG_SEL 0xd
119 /* Internal register definitions for the CPU1 module. */
120 #define DBG_CPU1_REG_SEL_LEN 1
121 #define DBG_CPU1_REG_STATUS 0
123 /* Opcode definitions for the second CPU module. */
124 #define DBG_CPU1_OPCODE_LEN 4
125 #define DBG_CPU1_CMD_NOP 0x0
126 #define DBG_CPU1_CMD_BWRITE32 0x3
127 #define DBG_CPU1_CMD_BREAD32 0x7
128 #define DBG_CPU1_CMD_IREG_WR 0x9
129 #define DBG_CPU1_CMD_IREG_SEL 0xd
131 #define MAX_READ_STATUS_WAIT 10
132 #define MAX_READ_BUSY_RETRY 2
133 #define MAX_READ_CRC_RETRY 2
134 #define MAX_WRITE_CRC_RETRY 2
135 #define BURST_READ_READY 1
136 #define MAX_BUS_ERRORS 2
138 #define MAX_BURST_SIZE (4 * 1024)
140 #define STATUS_BYTES 1
143 static struct or1k_du or1k_du_adv
;
145 static const char * const chain_name
[] = {"WISHBONE", "CPU0", "CPU1", "JSP"};
147 static uint32_t adbg_compute_crc(uint32_t crc
, uint32_t data_in
,
150 for (int i
= 0; i
< length_bits
; i
++) {
152 d
= ((data_in
>> i
) & 0x1) ? 0xffffffff : 0;
153 c
= (crc
& 0x1) ? 0xffffffff : 0;
155 crc
= crc
^ ((d
^ c
) & ADBG_CRC_POLY
);
161 static int find_status_bit(void *_buf
, int len
)
168 while (!(buf
[i
] & (1 << count
++)) && (i
< len
)) {
176 ret
= (i
* 8) + count
;
181 static int or1k_adv_jtag_init(struct or1k_jtag
*jtag_info
)
183 struct or1k_tap_ip
*tap_ip
= jtag_info
->tap_ip
;
185 int retval
= tap_ip
->init(jtag_info
);
186 if (retval
!= ERROR_OK
) {
187 LOG_ERROR("TAP initialization failed");
191 /* TAP is now configured to communicate with debug interface */
192 jtag_info
->or1k_jtag_inited
= 1;
194 /* TAP reset - not sure what state debug module chain is in now */
195 jtag_info
->or1k_jtag_module_selected
= DC_NONE
;
197 jtag_info
->current_reg_idx
= malloc(DBG_MAX_MODULES
* sizeof(uint8_t));
198 memset(jtag_info
->current_reg_idx
, 0, DBG_MAX_MODULES
* sizeof(uint8_t));
200 if (or1k_du_adv
.options
& ADBG_USE_HISPEED
)
201 LOG_INFO("adv debug unit is configured with option ADBG_USE_HISPEED");
203 if (or1k_du_adv
.options
& ENABLE_JSP_SERVER
) {
204 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
)
205 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_MULTI");
206 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_SERVER");
207 retval
= jsp_init(jtag_info
, JSP_BANNER
);
208 if (retval
!= ERROR_OK
) {
209 LOG_ERROR("Couldn't start the JSP server");
214 LOG_DEBUG("Init done");
220 /* Selects one of the modules in the debug unit
221 * (e.g. wishbone unit, CPU0, etc.)
223 static int adbg_select_module(struct or1k_jtag
*jtag_info
, int chain
)
225 if (jtag_info
->or1k_jtag_module_selected
== chain
)
228 /* MSB of the data out must be set to 1, indicating a module
231 uint8_t data
= chain
| (1 << DBG_MODULE_SELECT_REG_SIZE
);
233 LOG_DEBUG("Select module: %s", chain_name
[chain
]);
235 struct scan_field field
;
237 field
.num_bits
= (DBG_MODULE_SELECT_REG_SIZE
+ 1);
238 field
.out_value
= &data
;
239 field
.in_value
= NULL
;
240 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
242 int retval
= jtag_execute_queue();
243 if (retval
!= ERROR_OK
)
246 jtag_info
->or1k_jtag_module_selected
= chain
;
251 /* Set the index of the desired register in the currently selected module
252 * 1 bit module select command
256 static int adbg_select_ctrl_reg(struct or1k_jtag
*jtag_info
, uint8_t regidx
)
262 /* If this reg is already selected, don't do a JTAG transaction */
263 if (jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] == regidx
)
266 switch (jtag_info
->or1k_jtag_module_selected
) {
268 index_len
= DBG_WB_REG_SEL_LEN
;
269 opcode
= DBG_WB_CMD_IREG_SEL
;
270 opcode_len
= DBG_WB_OPCODE_LEN
;
273 index_len
= DBG_CPU0_REG_SEL_LEN
;
274 opcode
= DBG_CPU0_CMD_IREG_SEL
;
275 opcode_len
= DBG_CPU0_OPCODE_LEN
;
278 index_len
= DBG_CPU1_REG_SEL_LEN
;
279 opcode
= DBG_CPU1_CMD_IREG_SEL
;
280 opcode_len
= DBG_CPU1_OPCODE_LEN
;
283 LOG_ERROR("Illegal debug chain selected (%i) while selecting control register",
284 jtag_info
->or1k_jtag_module_selected
);
288 /* MSB must be 0 to access modules */
289 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
292 struct scan_field field
;
294 field
.num_bits
= (opcode_len
+ 1) + index_len
;
295 field
.out_value
= (uint8_t *)&data
;
296 field
.in_value
= NULL
;
297 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
299 int retval
= jtag_execute_queue();
300 if (retval
!= ERROR_OK
)
303 jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] = regidx
;
308 /* Write control register (internal to the debug unit) */
309 static int adbg_ctrl_write(struct or1k_jtag
*jtag_info
, uint8_t regidx
,
310 uint32_t *cmd_data
, int length_bits
)
316 LOG_DEBUG("Write control register %" PRId8
": 0x%08" PRIx32
, regidx
, cmd_data
[0]);
318 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
319 if (retval
!= ERROR_OK
) {
320 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
324 switch (jtag_info
->or1k_jtag_module_selected
) {
326 index_len
= DBG_WB_REG_SEL_LEN
;
327 opcode
= DBG_WB_CMD_IREG_WR
;
328 opcode_len
= DBG_WB_OPCODE_LEN
;
331 index_len
= DBG_CPU0_REG_SEL_LEN
;
332 opcode
= DBG_CPU0_CMD_IREG_WR
;
333 opcode_len
= DBG_CPU0_OPCODE_LEN
;
336 index_len
= DBG_CPU1_REG_SEL_LEN
;
337 opcode
= DBG_CPU1_CMD_IREG_WR
;
338 opcode_len
= DBG_CPU1_OPCODE_LEN
;
341 LOG_ERROR("Illegal debug chain selected (%i) while doing control write",
342 jtag_info
->or1k_jtag_module_selected
);
346 struct scan_field field
[2];
348 /* MSB must be 0 to access modules */
349 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
352 field
[0].num_bits
= length_bits
;
353 field
[0].out_value
= (uint8_t *)cmd_data
;
354 field
[0].in_value
= NULL
;
356 field
[1].num_bits
= (opcode_len
+ 1) + index_len
;
357 field
[1].out_value
= (uint8_t *)&data
;
358 field
[1].in_value
= NULL
;
360 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
362 return jtag_execute_queue();
365 /* Reads control register (internal to the debug unit) */
366 static int adbg_ctrl_read(struct or1k_jtag
*jtag_info
, uint32_t regidx
,
367 uint32_t *data
, int length_bits
)
370 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
371 if (retval
!= ERROR_OK
) {
372 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
379 /* There is no 'read' command, We write a NOP to read */
380 switch (jtag_info
->or1k_jtag_module_selected
) {
382 opcode
= DBG_WB_CMD_NOP
;
383 opcode_len
= DBG_WB_OPCODE_LEN
;
386 opcode
= DBG_CPU0_CMD_NOP
;
387 opcode_len
= DBG_CPU0_OPCODE_LEN
;
390 opcode
= DBG_CPU1_CMD_NOP
;
391 opcode_len
= DBG_CPU1_OPCODE_LEN
;
394 LOG_ERROR("Illegal debug chain selected (%i) while doing control read",
395 jtag_info
->or1k_jtag_module_selected
);
399 /* Zero MSB = op for module, not top-level debug unit */
400 uint32_t outdata
= opcode
& ~(0x1 << opcode_len
);
402 struct scan_field field
[2];
404 field
[0].num_bits
= length_bits
;
405 field
[0].out_value
= NULL
;
406 field
[0].in_value
= (uint8_t *)data
;
408 field
[1].num_bits
= opcode_len
+ 1;
409 field
[1].out_value
= (uint8_t *)&outdata
;
410 field
[1].in_value
= NULL
;
412 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
414 return jtag_execute_queue();
417 /* sends out a burst command to the selected module in the debug unit (MSB to LSB):
418 * 1-bit module command
421 * 16-bit length (of the burst, in words)
423 static int adbg_burst_command(struct or1k_jtag
*jtag_info
, uint32_t opcode
,
424 uint32_t address
, uint16_t length_words
)
428 /* Set up the data */
429 data
[0] = length_words
| (address
<< 16);
430 /* MSB must be 0 to access modules */
431 data
[1] = ((address
>> 16) | ((opcode
& 0xf) << 16)) & ~(0x1 << 20);
433 struct scan_field field
;
436 field
.out_value
= (uint8_t *)&data
[0];
437 field
.in_value
= NULL
;
439 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
441 return jtag_execute_queue();
444 static int adbg_wb_burst_read(struct or1k_jtag
*jtag_info
, int size
,
445 int count
, uint32_t start_address
, uint8_t *data
)
447 int retry_full_crc
= 0;
448 int retry_full_busy
= 0;
452 LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32
,
453 size
, count
, start_address
);
455 /* Select the appropriate opcode */
456 switch (jtag_info
->or1k_jtag_module_selected
) {
459 opcode
= DBG_WB_CMD_BREAD8
;
461 opcode
= DBG_WB_CMD_BREAD16
;
463 opcode
= DBG_WB_CMD_BREAD32
;
465 LOG_WARNING("Tried burst read with invalid word size (%d),"
466 "defaulting to 4-byte words", size
);
467 opcode
= DBG_WB_CMD_BREAD32
;
472 opcode
= DBG_CPU0_CMD_BREAD32
;
474 LOG_WARNING("Tried burst read with invalid word size (%d),"
475 "defaulting to 4-byte words", size
);
476 opcode
= DBG_CPU0_CMD_BREAD32
;
481 opcode
= DBG_CPU1_CMD_BREAD32
;
483 LOG_WARNING("Tried burst read with invalid word size (%d),"
484 "defaulting to 4-byte words", size
);
485 opcode
= DBG_CPU0_CMD_BREAD32
;
489 LOG_ERROR("Illegal debug chain selected (%i) while doing burst read",
490 jtag_info
->or1k_jtag_module_selected
);
494 int total_size_bytes
= count
* size
;
495 struct scan_field field
;
496 uint8_t *in_buffer
= malloc(total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
);
500 /* Send the BURST READ command, returns TAP to idle state */
501 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
502 if (retval
!= ERROR_OK
)
505 field
.num_bits
= (total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
) * 8;
506 field
.out_value
= NULL
;
507 field
.in_value
= in_buffer
;
509 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
511 retval
= jtag_execute_queue();
512 if (retval
!= ERROR_OK
)
515 /* Look for the start bit in the first (STATUS_BYTES * 8) bits */
516 int shift
= find_status_bit(in_buffer
, STATUS_BYTES
);
518 /* We expect the status bit to be in the first byte */
520 if (retry_full_busy
++ < MAX_READ_BUSY_RETRY
) {
521 LOG_WARNING("Burst read timed out");
522 goto retry_read_full
;
524 LOG_ERROR("Burst read failed");
530 buffer_shr(in_buffer
, total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
, shift
);
533 memcpy(data
, in_buffer
, total_size_bytes
);
534 memcpy(&crc_read
, &in_buffer
[total_size_bytes
], 4);
536 uint32_t crc_calc
= 0xffffffff;
537 for (int i
= 0; i
< total_size_bytes
; i
++)
538 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
540 if (crc_calc
!= crc_read
) {
541 LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32
", read CRC 0x%08" PRIx32
, crc_calc
, crc_read
);
542 if (retry_full_crc
++ < MAX_READ_CRC_RETRY
)
543 goto retry_read_full
;
545 LOG_ERROR("Burst read failed");
550 LOG_DEBUG("CRC OK!");
552 /* Now, read the error register, and retry/recompute as necessary */
553 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
554 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
556 uint32_t err_data
[2] = {0, 0};
558 int bus_error_retries
= 0;
560 /* First, just get 1 bit...read address only if necessary */
561 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
562 if (retval
!= ERROR_OK
)
565 /* Then we have a problem */
566 if (err_data
[0] & 0x1) {
568 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
569 if (retval
!= ERROR_OK
)
572 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
573 LOG_WARNING("WB bus error during burst read, address 0x%08" PRIx32
", retrying!", addr
);
576 if (bus_error_retries
> MAX_BUS_ERRORS
) {
577 LOG_ERROR("Max WB bus errors reached during burst read");
582 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
583 /* Write 1 bit, to reset the error register */
585 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
586 if (retval
!= ERROR_OK
)
589 goto retry_read_full
;
599 /* Set up and execute a burst write to a contiguous set of addresses */
600 static int adbg_wb_burst_write(struct or1k_jtag
*jtag_info
, const uint8_t *data
, int size
,
601 int count
, unsigned long start_address
)
603 int retry_full_crc
= 0;
607 LOG_DEBUG("Doing burst write, word size %d, word count %d,"
608 "start address 0x%08lx", size
, count
, start_address
);
610 /* Select the appropriate opcode */
611 switch (jtag_info
->or1k_jtag_module_selected
) {
614 opcode
= DBG_WB_CMD_BWRITE8
;
616 opcode
= DBG_WB_CMD_BWRITE16
;
618 opcode
= DBG_WB_CMD_BWRITE32
;
620 LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
621 "defaulting to 4-byte words", size
);
622 opcode
= DBG_WB_CMD_BWRITE32
;
627 opcode
= DBG_CPU0_CMD_BWRITE32
;
629 LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
630 "defaulting to 4-byte words", size
);
631 opcode
= DBG_CPU0_CMD_BWRITE32
;
636 opcode
= DBG_CPU1_CMD_BWRITE32
;
638 LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
639 "defaulting to 4-byte words", size
);
640 opcode
= DBG_CPU0_CMD_BWRITE32
;
644 LOG_ERROR("Illegal debug chain selected (%i) while doing burst write",
645 jtag_info
->or1k_jtag_module_selected
);
651 /* Send the BURST WRITE command, returns TAP to idle state */
652 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
653 if (retval
!= ERROR_OK
)
656 struct scan_field field
[3];
658 /* Write a start bit so it knows when to start counting */
660 field
[0].num_bits
= 1;
661 field
[0].out_value
= &value
;
662 field
[0].in_value
= NULL
;
664 uint32_t crc_calc
= 0xffffffff;
665 for (int i
= 0; i
< (count
* size
); i
++)
666 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
668 field
[1].num_bits
= count
* size
* 8;
669 field
[1].out_value
= data
;
670 field
[1].in_value
= NULL
;
672 field
[2].num_bits
= 32;
673 field
[2].out_value
= (uint8_t *)&crc_calc
;
674 field
[2].in_value
= NULL
;
676 jtag_add_dr_scan(jtag_info
->tap
, 3, field
, TAP_DRSHIFT
);
678 /* Read the 'CRC match' bit, and go to idle */
679 field
[0].num_bits
= 1;
680 field
[0].out_value
= NULL
;
681 field
[0].in_value
= &value
;
682 jtag_add_dr_scan(jtag_info
->tap
, 1, field
, TAP_IDLE
);
684 retval
= jtag_execute_queue();
685 if (retval
!= ERROR_OK
)
689 LOG_WARNING("CRC ERROR! match bit after write is %" PRIi8
" (computed CRC 0x%08" PRIx32
")", value
, crc_calc
);
690 if (retry_full_crc
++ < MAX_WRITE_CRC_RETRY
)
691 goto retry_full_write
;
695 LOG_DEBUG("CRC OK!\n");
697 /* Now, read the error register, and retry/recompute as necessary */
698 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
699 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
701 int bus_error_retries
= 0;
702 uint32_t err_data
[2] = {0, 0};
704 /* First, just get 1 bit...read address only if necessary */
705 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
706 if (retval
!= ERROR_OK
)
709 /* Then we have a problem */
710 if (err_data
[0] & 0x1) {
712 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
713 if (retval
!= ERROR_OK
)
716 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
717 LOG_WARNING("WB bus error during burst write, address 0x%08" PRIx32
", retrying!", addr
);
720 if (bus_error_retries
> MAX_BUS_ERRORS
) {
721 LOG_ERROR("Max WB bus errors reached during burst read");
726 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
727 /* Write 1 bit, to reset the error register */
729 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
730 if (retval
!= ERROR_OK
)
733 goto retry_full_write
;
740 /* Currently hard set in functions to 32-bits */
741 static int or1k_adv_jtag_read_cpu(struct or1k_jtag
*jtag_info
,
742 uint32_t addr
, int count
, uint32_t *value
)
745 if (!jtag_info
->or1k_jtag_inited
) {
746 retval
= or1k_adv_jtag_init(jtag_info
);
747 if (retval
!= ERROR_OK
)
751 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
752 if (retval
!= ERROR_OK
)
755 return adbg_wb_burst_read(jtag_info
, 4, count
, addr
, (uint8_t *)value
);
758 static int or1k_adv_jtag_write_cpu(struct or1k_jtag
*jtag_info
,
759 uint32_t addr
, int count
, const uint32_t *value
)
762 if (!jtag_info
->or1k_jtag_inited
) {
763 retval
= or1k_adv_jtag_init(jtag_info
);
764 if (retval
!= ERROR_OK
)
768 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
769 if (retval
!= ERROR_OK
)
772 return adbg_wb_burst_write(jtag_info
, (uint8_t *)value
, 4, count
, addr
);
775 static int or1k_adv_cpu_stall(struct or1k_jtag
*jtag_info
, int action
)
778 if (!jtag_info
->or1k_jtag_inited
) {
779 retval
= or1k_adv_jtag_init(jtag_info
);
780 if (retval
!= ERROR_OK
)
784 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
785 if (retval
!= ERROR_OK
)
789 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
790 if (retval
!= ERROR_OK
)
793 if (action
== CPU_STALL
)
794 cpu_cr
|= DBG_CPU_CR_STALL
;
796 cpu_cr
&= ~DBG_CPU_CR_STALL
;
798 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
799 if (retval
!= ERROR_OK
)
802 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
805 static int or1k_adv_is_cpu_running(struct or1k_jtag
*jtag_info
, int *running
)
808 if (!jtag_info
->or1k_jtag_inited
) {
809 retval
= or1k_adv_jtag_init(jtag_info
);
810 if (retval
!= ERROR_OK
)
814 int current
= jtag_info
->or1k_jtag_module_selected
;
816 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
817 if (retval
!= ERROR_OK
)
821 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
822 if (retval
!= ERROR_OK
)
825 if (cpu_cr
& DBG_CPU_CR_STALL
)
830 if (current
!= DC_NONE
) {
831 retval
= adbg_select_module(jtag_info
, current
);
832 if (retval
!= ERROR_OK
)
839 static int or1k_adv_cpu_reset(struct or1k_jtag
*jtag_info
, int action
)
842 if (!jtag_info
->or1k_jtag_inited
) {
843 retval
= or1k_adv_jtag_init(jtag_info
);
844 if (retval
!= ERROR_OK
)
848 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
849 if (retval
!= ERROR_OK
)
853 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
854 if (retval
!= ERROR_OK
)
857 if (action
== CPU_RESET
)
858 cpu_cr
|= DBG_CPU_CR_RESET
;
860 cpu_cr
&= ~DBG_CPU_CR_RESET
;
862 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
863 if (retval
!= ERROR_OK
)
866 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
869 static int or1k_adv_jtag_read_memory(struct or1k_jtag
*jtag_info
,
870 uint32_t addr
, uint32_t size
, int count
, uint8_t *buffer
)
872 LOG_DEBUG("Reading WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
875 if (!jtag_info
->or1k_jtag_inited
) {
876 retval
= or1k_adv_jtag_init(jtag_info
);
877 if (retval
!= ERROR_OK
)
881 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
882 if (retval
!= ERROR_OK
)
885 int block_count_left
= count
;
886 uint32_t block_count_address
= addr
;
887 uint8_t *block_count_buffer
= buffer
;
889 while (block_count_left
) {
891 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
892 MAX_BURST_SIZE
: block_count_left
;
894 retval
= adbg_wb_burst_read(jtag_info
, size
, blocks_this_round
,
895 block_count_address
, block_count_buffer
);
896 if (retval
!= ERROR_OK
)
899 block_count_left
-= blocks_this_round
;
900 block_count_address
+= size
* MAX_BURST_SIZE
;
901 block_count_buffer
+= size
* MAX_BURST_SIZE
;
904 /* The adv_debug_if always return words and half words in
905 * little-endian order no matter what the target endian is.
906 * So if the target endian is big, change the order.
909 struct target
*target
= jtag_info
->target
;
910 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
913 buf_bswap32(buffer
, buffer
, size
* count
);
916 buf_bswap16(buffer
, buffer
, size
* count
);
924 static int or1k_adv_jtag_write_memory(struct or1k_jtag
*jtag_info
,
925 uint32_t addr
, uint32_t size
, int count
, const uint8_t *buffer
)
927 LOG_DEBUG("Writing WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
930 if (!jtag_info
->or1k_jtag_inited
) {
931 retval
= or1k_adv_jtag_init(jtag_info
);
932 if (retval
!= ERROR_OK
)
936 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
937 if (retval
!= ERROR_OK
)
940 /* The adv_debug_if wants words and half words in little-endian
941 * order no matter what the target endian is. So if the target
942 * endian is big, change the order.
946 struct target
*target
= jtag_info
->target
;
947 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
948 t
= malloc(count
* size
* sizeof(uint8_t));
950 LOG_ERROR("Out of memory");
956 buf_bswap32(t
, buffer
, size
* count
);
959 buf_bswap16(t
, buffer
, size
* count
);
965 int block_count_left
= count
;
966 uint32_t block_count_address
= addr
;
967 uint8_t *block_count_buffer
= (uint8_t *)buffer
;
969 while (block_count_left
) {
971 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
972 MAX_BURST_SIZE
: block_count_left
;
974 retval
= adbg_wb_burst_write(jtag_info
, block_count_buffer
,
975 size
, blocks_this_round
,
976 block_count_address
);
977 if (retval
!= ERROR_OK
) {
983 block_count_left
-= blocks_this_round
;
984 block_count_address
+= size
* MAX_BURST_SIZE
;
985 block_count_buffer
+= size
* MAX_BURST_SIZE
;
994 int or1k_adv_jtag_jsp_xfer(struct or1k_jtag
*jtag_info
,
995 int *out_len
, unsigned char *out_buffer
,
996 int *in_len
, unsigned char *in_buffer
)
998 LOG_DEBUG("JSP transfert");
1001 if (!jtag_info
->or1k_jtag_inited
)
1004 retval
= adbg_select_module(jtag_info
, DC_JSP
);
1005 if (retval
!= ERROR_OK
)
1008 /* return nb char xmit */
1013 xmitsize
= *out_len
;
1015 uint8_t out_data
[10];
1016 uint8_t in_data
[10];
1017 struct scan_field field
;
1018 int startbit
, stopbit
, wrapbit
;
1020 memset(out_data
, 0, 10);
1022 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
) {
1025 wrapbit
= (xmitsize
>> 3) & 0x1;
1026 out_data
[0] = (xmitsize
<< 5) | 0x1; /* set the start bit */
1029 /* don't copy off the end of the input array */
1030 for (i
= 0; i
< xmitsize
; i
++) {
1031 out_data
[i
+ 1] = (out_buffer
[i
] << 1) | wrapbit
;
1032 wrapbit
= (out_buffer
[i
] >> 7) & 0x1;
1036 out_data
[i
+ 1] = wrapbit
;
1038 out_data
[9] = wrapbit
;
1040 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1041 * won't treat the burst as a 'module select' command.
1043 stopbit
= !!(out_data
[9] & 0x01);
1047 /* First byte out has write count in upper nibble */
1048 out_data
[0] = 0x0 | (xmitsize
<< 4);
1050 memcpy(&out_data
[1], out_buffer
, xmitsize
);
1052 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1053 * won't treat the burst as a 'module select' command.
1055 stopbit
= !!(out_data
[8] & 0x80);
1058 field
.num_bits
= 72 + startbit
+ stopbit
;
1059 field
.out_value
= out_data
;
1060 field
.in_value
= in_data
;
1062 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
1064 retval
= jtag_execute_queue();
1065 if (retval
!= ERROR_OK
)
1068 /* bytes available is in the upper nibble */
1069 *in_len
= (in_data
[0] >> 4) & 0xF;
1070 memcpy(in_buffer
, &in_data
[1], *in_len
);
1072 int bytes_free
= in_data
[0] & 0x0F;
1073 *out_len
= (bytes_free
< xmitsize
) ? bytes_free
: xmitsize
;
1078 static struct or1k_du or1k_du_adv
= {
1080 .options
= NO_OPTION
,
1081 .or1k_jtag_init
= or1k_adv_jtag_init
,
1083 .or1k_is_cpu_running
= or1k_adv_is_cpu_running
,
1084 .or1k_cpu_stall
= or1k_adv_cpu_stall
,
1085 .or1k_cpu_reset
= or1k_adv_cpu_reset
,
1087 .or1k_jtag_read_cpu
= or1k_adv_jtag_read_cpu
,
1088 .or1k_jtag_write_cpu
= or1k_adv_jtag_write_cpu
,
1090 .or1k_jtag_read_memory
= or1k_adv_jtag_read_memory
,
1091 .or1k_jtag_write_memory
= or1k_adv_jtag_write_memory
1094 int or1k_du_adv_register(void)
1096 list_add_tail(&or1k_du_adv
.list
, &du_list
);
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