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target/hla_target: set cortex_m->common_magic
[openocd.git] / src / target / riscv / riscv-013.c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /*
4 * Support for RISC-V, debug version 0.13, which is currently (2/4/17) the
5 * latest draft.
6 */
7
8 #include <assert.h>
9 #include <stdlib.h>
10 #include <time.h>
11
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15
16 #include "target/target.h"
17 #include "target/algorithm.h"
18 #include "target/target_type.h"
19 #include <helper/log.h>
20 #include "jtag/jtag.h"
21 #include "target/register.h"
22 #include "target/breakpoints.h"
23 #include "helper/time_support.h"
24 #include "helper/list.h"
25 #include "riscv.h"
26 #include "debug_defines.h"
27 #include "rtos/rtos.h"
28 #include "program.h"
29 #include "asm.h"
30 #include "batch.h"
31
32 static int riscv013_on_step_or_resume(struct target *target, bool step);
33 static int riscv013_step_or_resume_current_hart(struct target *target,
34 bool step, bool use_hasel);
35 static void riscv013_clear_abstract_error(struct target *target);
36
37 /* Implementations of the functions in riscv_info_t. */
38 static int riscv013_get_register(struct target *target,
39 riscv_reg_t *value, int rid);
40 static int riscv013_set_register(struct target *target, int regid, uint64_t value);
41 static int riscv013_select_current_hart(struct target *target);
42 static int riscv013_halt_prep(struct target *target);
43 static int riscv013_halt_go(struct target *target);
44 static int riscv013_resume_go(struct target *target);
45 static int riscv013_step_current_hart(struct target *target);
46 static int riscv013_on_halt(struct target *target);
47 static int riscv013_on_step(struct target *target);
48 static int riscv013_resume_prep(struct target *target);
49 static bool riscv013_is_halted(struct target *target);
50 static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
51 static int riscv013_write_debug_buffer(struct target *target, unsigned index,
52 riscv_insn_t d);
53 static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
54 index);
55 static int riscv013_execute_debug_buffer(struct target *target);
56 static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
57 static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
58 static int riscv013_dmi_write_u64_bits(struct target *target);
59 static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
60 static int register_read(struct target *target, uint64_t *value, uint32_t number);
61 static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
62 static int register_write_direct(struct target *target, unsigned number,
63 uint64_t value);
64 static int read_memory(struct target *target, target_addr_t address,
65 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
66 static int write_memory(struct target *target, target_addr_t address,
67 uint32_t size, uint32_t count, const uint8_t *buffer);
68 static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address,
69 uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
70 void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t *write_data,
71 uint32_t write_size, uint32_t sbcs);
72 void read_memory_sba_simple(struct target *target, target_addr_t addr,
73 uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs);
74
75 /**
76 * Since almost everything can be accomplish by scanning the dbus register, all
77 * functions here assume dbus is already selected. The exception are functions
78 * called directly by OpenOCD, which can't assume anything about what's
79 * currently in IR. They should set IR to dbus explicitly.
80 */
81
82 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
83 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
84
85 #define CSR_DCSR_CAUSE_SWBP 1
86 #define CSR_DCSR_CAUSE_TRIGGER 2
87 #define CSR_DCSR_CAUSE_DEBUGINT 3
88 #define CSR_DCSR_CAUSE_STEP 4
89 #define CSR_DCSR_CAUSE_HALT 5
90 #define CSR_DCSR_CAUSE_GROUP 6
91
92 #define RISCV013_INFO(r) riscv013_info_t *r = get_info(target)
93
94 /*** JTAG registers. ***/
95
96 typedef enum {
97 DMI_OP_NOP = 0,
98 DMI_OP_READ = 1,
99 DMI_OP_WRITE = 2
100 } dmi_op_t;
101 typedef enum {
102 DMI_STATUS_SUCCESS = 0,
103 DMI_STATUS_FAILED = 2,
104 DMI_STATUS_BUSY = 3
105 } dmi_status_t;
106
107 typedef enum slot {
108 SLOT0,
109 SLOT1,
110 SLOT_LAST,
111 } slot_t;
112
113 /*** Debug Bus registers. ***/
114
115 #define CMDERR_NONE 0
116 #define CMDERR_BUSY 1
117 #define CMDERR_NOT_SUPPORTED 2
118 #define CMDERR_EXCEPTION 3
119 #define CMDERR_HALT_RESUME 4
120 #define CMDERR_OTHER 7
121
122 /*** Info about the core being debugged. ***/
123
124 struct trigger {
125 uint64_t address;
126 uint32_t length;
127 uint64_t mask;
128 uint64_t value;
129 bool read, write, execute;
130 int unique_id;
131 };
132
133 typedef enum {
134 YNM_MAYBE,
135 YNM_YES,
136 YNM_NO
137 } yes_no_maybe_t;
138
139 typedef struct {
140 struct list_head list;
141 int abs_chain_position;
142
143 /* The number of harts connected to this DM. */
144 int hart_count;
145 /* Indicates we already reset this DM, so don't need to do it again. */
146 bool was_reset;
147 /* Targets that are connected to this DM. */
148 struct list_head target_list;
149 /* The currently selected hartid on this DM. */
150 int current_hartid;
151 bool hasel_supported;
152
153 /* The program buffer stores executable code. 0 is an illegal instruction,
154 * so we use 0 to mean the cached value is invalid. */
155 uint32_t progbuf_cache[16];
156 } dm013_info_t;
157
158 typedef struct {
159 struct list_head list;
160 struct target *target;
161 } target_list_t;
162
163 typedef struct {
164 /* The indexed used to address this hart in its DM. */
165 unsigned index;
166 /* Number of address bits in the dbus register. */
167 unsigned abits;
168 /* Number of abstract command data registers. */
169 unsigned datacount;
170 /* Number of words in the Program Buffer. */
171 unsigned progbufsize;
172
173 /* We cache the read-only bits of sbcs here. */
174 uint32_t sbcs;
175
176 yes_no_maybe_t progbuf_writable;
177 /* We only need the address so that we know the alignment of the buffer. */
178 riscv_addr_t progbuf_address;
179
180 /* Number of run-test/idle cycles the target requests we do after each dbus
181 * access. */
182 unsigned int dtmcs_idle;
183
184 /* This value is incremented every time a dbus access comes back as "busy".
185 * It's used to determine how many run-test/idle cycles to feed the target
186 * in between accesses. */
187 unsigned int dmi_busy_delay;
188
189 /* Number of run-test/idle cycles to add between consecutive bus master
190 * reads/writes respectively. */
191 unsigned int bus_master_write_delay, bus_master_read_delay;
192
193 /* This value is increased every time we tried to execute two commands
194 * consecutively, and the second one failed because the previous hadn't
195 * completed yet. It's used to add extra run-test/idle cycles after
196 * starting a command, so we don't have to waste time checking for busy to
197 * go low. */
198 unsigned int ac_busy_delay;
199
200 bool abstract_read_csr_supported;
201 bool abstract_write_csr_supported;
202 bool abstract_read_fpr_supported;
203 bool abstract_write_fpr_supported;
204
205 yes_no_maybe_t has_aampostincrement;
206
207 /* When a function returns some error due to a failure indicated by the
208 * target in cmderr, the caller can look here to see what that error was.
209 * (Compare with errno.) */
210 uint8_t cmderr;
211
212 /* Some fields from hartinfo. */
213 uint8_t datasize;
214 uint8_t dataaccess;
215 int16_t dataaddr;
216
217 /* The width of the hartsel field. */
218 unsigned hartsellen;
219
220 /* DM that provides access to this target. */
221 dm013_info_t *dm;
222 } riscv013_info_t;
223
224 LIST_HEAD(dm_list);
225
226 static riscv013_info_t *get_info(const struct target *target)
227 {
228 riscv_info_t *info = (riscv_info_t *) target->arch_info;
229 assert(info);
230 assert(info->version_specific);
231 return (riscv013_info_t *) info->version_specific;
232 }
233
234 /**
235 * Return the DM structure for this target. If there isn't one, find it in the
236 * global list of DMs. If it's not in there, then create one and initialize it
237 * to 0.
238 */
239 dm013_info_t *get_dm(struct target *target)
240 {
241 RISCV013_INFO(info);
242 if (info->dm)
243 return info->dm;
244
245 int abs_chain_position = target->tap->abs_chain_position;
246
247 dm013_info_t *entry;
248 dm013_info_t *dm = NULL;
249 list_for_each_entry(entry, &dm_list, list) {
250 if (entry->abs_chain_position == abs_chain_position) {
251 dm = entry;
252 break;
253 }
254 }
255
256 if (!dm) {
257 LOG_DEBUG("[%d] Allocating new DM", target->coreid);
258 dm = calloc(1, sizeof(dm013_info_t));
259 if (!dm)
260 return NULL;
261 dm->abs_chain_position = abs_chain_position;
262 dm->current_hartid = -1;
263 dm->hart_count = -1;
264 INIT_LIST_HEAD(&dm->target_list);
265 list_add(&dm->list, &dm_list);
266 }
267
268 info->dm = dm;
269 target_list_t *target_entry;
270 list_for_each_entry(target_entry, &dm->target_list, list) {
271 if (target_entry->target == target)
272 return dm;
273 }
274 target_entry = calloc(1, sizeof(*target_entry));
275 if (!target_entry) {
276 info->dm = NULL;
277 return NULL;
278 }
279 target_entry->target = target;
280 list_add(&target_entry->list, &dm->target_list);
281
282 return dm;
283 }
284
285 static uint32_t set_hartsel(uint32_t initial, uint32_t index)
286 {
287 initial &= ~DM_DMCONTROL_HARTSELLO;
288 initial &= ~DM_DMCONTROL_HARTSELHI;
289
290 uint32_t index_lo = index & ((1 << DM_DMCONTROL_HARTSELLO_LENGTH) - 1);
291 initial |= index_lo << DM_DMCONTROL_HARTSELLO_OFFSET;
292 uint32_t index_hi = index >> DM_DMCONTROL_HARTSELLO_LENGTH;
293 assert(index_hi < 1 << DM_DMCONTROL_HARTSELHI_LENGTH);
294 initial |= index_hi << DM_DMCONTROL_HARTSELHI_OFFSET;
295
296 return initial;
297 }
298
299 static void decode_dmi(char *text, unsigned address, unsigned data)
300 {
301 static const struct {
302 unsigned address;
303 uint64_t mask;
304 const char *name;
305 } description[] = {
306 { DM_DMCONTROL, DM_DMCONTROL_HALTREQ, "haltreq" },
307 { DM_DMCONTROL, DM_DMCONTROL_RESUMEREQ, "resumereq" },
308 { DM_DMCONTROL, DM_DMCONTROL_HARTRESET, "hartreset" },
309 { DM_DMCONTROL, DM_DMCONTROL_HASEL, "hasel" },
310 { DM_DMCONTROL, DM_DMCONTROL_HARTSELHI, "hartselhi" },
311 { DM_DMCONTROL, DM_DMCONTROL_HARTSELLO, "hartsello" },
312 { DM_DMCONTROL, DM_DMCONTROL_NDMRESET, "ndmreset" },
313 { DM_DMCONTROL, DM_DMCONTROL_DMACTIVE, "dmactive" },
314 { DM_DMCONTROL, DM_DMCONTROL_ACKHAVERESET, "ackhavereset" },
315
316 { DM_DMSTATUS, DM_DMSTATUS_IMPEBREAK, "impebreak" },
317 { DM_DMSTATUS, DM_DMSTATUS_ALLHAVERESET, "allhavereset" },
318 { DM_DMSTATUS, DM_DMSTATUS_ANYHAVERESET, "anyhavereset" },
319 { DM_DMSTATUS, DM_DMSTATUS_ALLRESUMEACK, "allresumeack" },
320 { DM_DMSTATUS, DM_DMSTATUS_ANYRESUMEACK, "anyresumeack" },
321 { DM_DMSTATUS, DM_DMSTATUS_ALLNONEXISTENT, "allnonexistent" },
322 { DM_DMSTATUS, DM_DMSTATUS_ANYNONEXISTENT, "anynonexistent" },
323 { DM_DMSTATUS, DM_DMSTATUS_ALLUNAVAIL, "allunavail" },
324 { DM_DMSTATUS, DM_DMSTATUS_ANYUNAVAIL, "anyunavail" },
325 { DM_DMSTATUS, DM_DMSTATUS_ALLRUNNING, "allrunning" },
326 { DM_DMSTATUS, DM_DMSTATUS_ANYRUNNING, "anyrunning" },
327 { DM_DMSTATUS, DM_DMSTATUS_ALLHALTED, "allhalted" },
328 { DM_DMSTATUS, DM_DMSTATUS_ANYHALTED, "anyhalted" },
329 { DM_DMSTATUS, DM_DMSTATUS_AUTHENTICATED, "authenticated" },
330 { DM_DMSTATUS, DM_DMSTATUS_AUTHBUSY, "authbusy" },
331 { DM_DMSTATUS, DM_DMSTATUS_HASRESETHALTREQ, "hasresethaltreq" },
332 { DM_DMSTATUS, DM_DMSTATUS_CONFSTRPTRVALID, "confstrptrvalid" },
333 { DM_DMSTATUS, DM_DMSTATUS_VERSION, "version" },
334
335 { DM_ABSTRACTCS, DM_ABSTRACTCS_PROGBUFSIZE, "progbufsize" },
336 { DM_ABSTRACTCS, DM_ABSTRACTCS_BUSY, "busy" },
337 { DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR, "cmderr" },
338 { DM_ABSTRACTCS, DM_ABSTRACTCS_DATACOUNT, "datacount" },
339
340 { DM_COMMAND, DM_COMMAND_CMDTYPE, "cmdtype" },
341
342 { DM_SBCS, DM_SBCS_SBVERSION, "sbversion" },
343 { DM_SBCS, DM_SBCS_SBBUSYERROR, "sbbusyerror" },
344 { DM_SBCS, DM_SBCS_SBBUSY, "sbbusy" },
345 { DM_SBCS, DM_SBCS_SBREADONADDR, "sbreadonaddr" },
346 { DM_SBCS, DM_SBCS_SBACCESS, "sbaccess" },
347 { DM_SBCS, DM_SBCS_SBAUTOINCREMENT, "sbautoincrement" },
348 { DM_SBCS, DM_SBCS_SBREADONDATA, "sbreadondata" },
349 { DM_SBCS, DM_SBCS_SBERROR, "sberror" },
350 { DM_SBCS, DM_SBCS_SBASIZE, "sbasize" },
351 { DM_SBCS, DM_SBCS_SBACCESS128, "sbaccess128" },
352 { DM_SBCS, DM_SBCS_SBACCESS64, "sbaccess64" },
353 { DM_SBCS, DM_SBCS_SBACCESS32, "sbaccess32" },
354 { DM_SBCS, DM_SBCS_SBACCESS16, "sbaccess16" },
355 { DM_SBCS, DM_SBCS_SBACCESS8, "sbaccess8" },
356 };
357
358 text[0] = 0;
359 for (unsigned i = 0; i < ARRAY_SIZE(description); i++) {
360 if (description[i].address == address) {
361 uint64_t mask = description[i].mask;
362 unsigned value = get_field(data, mask);
363 if (value) {
364 if (i > 0)
365 *(text++) = ' ';
366 if (mask & (mask >> 1)) {
367 /* If the field is more than 1 bit wide. */
368 sprintf(text, "%s=%d", description[i].name, value);
369 } else {
370 strcpy(text, description[i].name);
371 }
372 text += strlen(text);
373 }
374 }
375 }
376 }
377
378 static void dump_field(int idle, const struct scan_field *field)
379 {
380 static const char * const op_string[] = {"-", "r", "w", "?"};
381 static const char * const status_string[] = {"+", "?", "F", "b"};
382
383 if (debug_level < LOG_LVL_DEBUG)
384 return;
385
386 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
387 unsigned int out_op = get_field(out, DTM_DMI_OP);
388 unsigned int out_data = get_field(out, DTM_DMI_DATA);
389 unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
390
391 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
392 unsigned int in_op = get_field(in, DTM_DMI_OP);
393 unsigned int in_data = get_field(in, DTM_DMI_DATA);
394 unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
395
396 log_printf_lf(LOG_LVL_DEBUG,
397 __FILE__, __LINE__, "scan",
398 "%db %s %08x @%02x -> %s %08x @%02x; %di",
399 field->num_bits, op_string[out_op], out_data, out_address,
400 status_string[in_op], in_data, in_address, idle);
401
402 char out_text[500];
403 char in_text[500];
404 decode_dmi(out_text, out_address, out_data);
405 decode_dmi(in_text, in_address, in_data);
406 if (in_text[0] || out_text[0]) {
407 log_printf_lf(LOG_LVL_DEBUG, __FILE__, __LINE__, "scan", "%s -> %s",
408 out_text, in_text);
409 }
410 }
411
412 /*** Utility functions. ***/
413
414 static void select_dmi(struct target *target)
415 {
416 if (bscan_tunnel_ir_width != 0) {
417 select_dmi_via_bscan(target);
418 return;
419 }
420 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
421 }
422
423 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
424 {
425 struct scan_field field;
426 uint8_t in_value[4];
427 uint8_t out_value[4] = { 0 };
428
429 if (bscan_tunnel_ir_width != 0)
430 return dtmcontrol_scan_via_bscan(target, out);
431
432 buf_set_u32(out_value, 0, 32, out);
433
434 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
435
436 field.num_bits = 32;
437 field.out_value = out_value;
438 field.in_value = in_value;
439 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
440
441 /* Always return to dmi. */
442 select_dmi(target);
443
444 int retval = jtag_execute_queue();
445 if (retval != ERROR_OK) {
446 LOG_ERROR("failed jtag scan: %d", retval);
447 return retval;
448 }
449
450 uint32_t in = buf_get_u32(field.in_value, 0, 32);
451 LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
452
453 return in;
454 }
455
456 static void increase_dmi_busy_delay(struct target *target)
457 {
458 riscv013_info_t *info = get_info(target);
459 info->dmi_busy_delay += info->dmi_busy_delay / 10 + 1;
460 LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
461 info->dtmcs_idle, info->dmi_busy_delay,
462 info->ac_busy_delay);
463
464 dtmcontrol_scan(target, DTM_DTMCS_DMIRESET);
465 }
466
467 /**
468 * exec: If this is set, assume the scan results in an execution, so more
469 * run-test/idle cycles may be required.
470 */
471 static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
472 uint32_t *data_in, dmi_op_t op, uint32_t address_out, uint32_t data_out,
473 bool exec)
474 {
475 riscv013_info_t *info = get_info(target);
476 RISCV_INFO(r);
477 unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH;
478 size_t num_bytes = (num_bits + 7) / 8;
479 uint8_t in[num_bytes];
480 uint8_t out[num_bytes];
481 struct scan_field field = {
482 .num_bits = num_bits,
483 .out_value = out,
484 .in_value = in
485 };
486 riscv_bscan_tunneled_scan_context_t bscan_ctxt;
487
488 if (r->reset_delays_wait >= 0) {
489 r->reset_delays_wait--;
490 if (r->reset_delays_wait < 0) {
491 info->dmi_busy_delay = 0;
492 info->ac_busy_delay = 0;
493 }
494 }
495
496 memset(in, 0, num_bytes);
497 memset(out, 0, num_bytes);
498
499 assert(info->abits != 0);
500
501 buf_set_u32(out, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, op);
502 buf_set_u32(out, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, data_out);
503 buf_set_u32(out, DTM_DMI_ADDRESS_OFFSET, info->abits, address_out);
504
505 /* I wanted to place this code in a different function, but the way JTAG command
506 queueing works in the jtag handling functions, the scan fields either have to be
507 heap allocated, global/static, or else they need to stay on the stack until
508 the jtag_execute_queue() call. Heap or static fields in this case doesn't seem
509 the best fit. Declaring stack based field values in a subsidiary function call wouldn't
510 work. */
511 if (bscan_tunnel_ir_width != 0) {
512 riscv_add_bscan_tunneled_scan(target, &field, &bscan_ctxt);
513 } else {
514 /* Assume dbus is already selected. */
515 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
516 }
517
518 int idle_count = info->dmi_busy_delay;
519 if (exec)
520 idle_count += info->ac_busy_delay;
521
522 if (idle_count)
523 jtag_add_runtest(idle_count, TAP_IDLE);
524
525 int retval = jtag_execute_queue();
526 if (retval != ERROR_OK) {
527 LOG_ERROR("dmi_scan failed jtag scan");
528 if (data_in)
529 *data_in = ~0;
530 return DMI_STATUS_FAILED;
531 }
532
533 if (bscan_tunnel_ir_width != 0) {
534 /* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
535 buffer_shr(in, num_bytes, 1);
536 }
537
538 if (data_in)
539 *data_in = buf_get_u32(in, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH);
540
541 if (address_in)
542 *address_in = buf_get_u32(in, DTM_DMI_ADDRESS_OFFSET, info->abits);
543 dump_field(idle_count, &field);
544 return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
545 }
546
547 /**
548 * @param target
549 * @param data_in The data we received from the target.
550 * @param dmi_busy_encountered
551 * If non-NULL, will be updated to reflect whether DMI busy was
552 * encountered while executing this operation or not.
553 * @param dmi_op The operation to perform (read/write/nop).
554 * @param address The address argument to that operation.
555 * @param data_out The data to send to the target.
556 * @param timeout_sec
557 * @param exec When true, this scan will execute something, so extra RTI
558 * cycles may be added.
559 * @param ensure_success
560 * Scan a nop after the requested operation, ensuring the
561 * DMI operation succeeded.
562 */
563 static int dmi_op_timeout(struct target *target, uint32_t *data_in,
564 bool *dmi_busy_encountered, int dmi_op, uint32_t address,
565 uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
566 {
567 select_dmi(target);
568
569 dmi_status_t status;
570 uint32_t address_in;
571
572 if (dmi_busy_encountered)
573 *dmi_busy_encountered = false;
574
575 const char *op_name;
576 switch (dmi_op) {
577 case DMI_OP_NOP:
578 op_name = "nop";
579 break;
580 case DMI_OP_READ:
581 op_name = "read";
582 break;
583 case DMI_OP_WRITE:
584 op_name = "write";
585 break;
586 default:
587 LOG_ERROR("Invalid DMI operation: %d", dmi_op);
588 return ERROR_FAIL;
589 }
590
591 keep_alive();
592
593 time_t start = time(NULL);
594 /* This first loop performs the request. Note that if for some reason this
595 * stays busy, it is actually due to the previous access. */
596 while (1) {
597 status = dmi_scan(target, NULL, NULL, dmi_op, address, data_out,
598 exec);
599 if (status == DMI_STATUS_BUSY) {
600 increase_dmi_busy_delay(target);
601 if (dmi_busy_encountered)
602 *dmi_busy_encountered = true;
603 } else if (status == DMI_STATUS_SUCCESS) {
604 break;
605 } else {
606 LOG_ERROR("failed %s at 0x%x, status=%d", op_name, address, status);
607 return ERROR_FAIL;
608 }
609 if (time(NULL) - start > timeout_sec)
610 return ERROR_TIMEOUT_REACHED;
611 }
612
613 if (status != DMI_STATUS_SUCCESS) {
614 LOG_ERROR("Failed %s at 0x%x; status=%d", op_name, address, status);
615 return ERROR_FAIL;
616 }
617
618 if (ensure_success) {
619 /* This second loop ensures the request succeeded, and gets back data.
620 * Note that NOP can result in a 'busy' result as well, but that would be
621 * noticed on the next DMI access we do. */
622 while (1) {
623 status = dmi_scan(target, &address_in, data_in, DMI_OP_NOP, address, 0,
624 false);
625 if (status == DMI_STATUS_BUSY) {
626 increase_dmi_busy_delay(target);
627 if (dmi_busy_encountered)
628 *dmi_busy_encountered = true;
629 } else if (status == DMI_STATUS_SUCCESS) {
630 break;
631 } else {
632 if (data_in) {
633 LOG_ERROR("Failed %s (NOP) at 0x%x; value=0x%x, status=%d",
634 op_name, address, *data_in, status);
635 } else {
636 LOG_ERROR("Failed %s (NOP) at 0x%x; status=%d", op_name, address,
637 status);
638 }
639 return ERROR_FAIL;
640 }
641 if (time(NULL) - start > timeout_sec)
642 return ERROR_TIMEOUT_REACHED;
643 }
644 }
645
646 return ERROR_OK;
647 }
648
649 static int dmi_op(struct target *target, uint32_t *data_in,
650 bool *dmi_busy_encountered, int dmi_op, uint32_t address,
651 uint32_t data_out, bool exec, bool ensure_success)
652 {
653 int result = dmi_op_timeout(target, data_in, dmi_busy_encountered, dmi_op,
654 address, data_out, riscv_command_timeout_sec, exec, ensure_success);
655 if (result == ERROR_TIMEOUT_REACHED) {
656 LOG_ERROR("DMI operation didn't complete in %d seconds. The target is "
657 "either really slow or broken. You could increase the "
658 "timeout with riscv set_command_timeout_sec.",
659 riscv_command_timeout_sec);
660 return ERROR_FAIL;
661 }
662 return result;
663 }
664
665 static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
666 {
667 return dmi_op(target, value, NULL, DMI_OP_READ, address, 0, false, true);
668 }
669
670 static int dmi_read_exec(struct target *target, uint32_t *value, uint32_t address)
671 {
672 return dmi_op(target, value, NULL, DMI_OP_READ, address, 0, true, true);
673 }
674
675 static int dmi_write(struct target *target, uint32_t address, uint32_t value)
676 {
677 return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, false, true);
678 }
679
680 static int dmi_write_exec(struct target *target, uint32_t address,
681 uint32_t value, bool ensure_success)
682 {
683 return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, true, ensure_success);
684 }
685
686 int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus,
687 bool authenticated, unsigned timeout_sec)
688 {
689 int result = dmi_op_timeout(target, dmstatus, NULL, DMI_OP_READ,
690 DM_DMSTATUS, 0, timeout_sec, false, true);
691 if (result != ERROR_OK)
692 return result;
693 int dmstatus_version = get_field(*dmstatus, DM_DMSTATUS_VERSION);
694 if (dmstatus_version != 2 && dmstatus_version != 3) {
695 LOG_ERROR("OpenOCD only supports Debug Module version 2 (0.13) and 3 (1.0), not "
696 "%d (dmstatus=0x%x). This error might be caused by a JTAG "
697 "signal issue. Try reducing the JTAG clock speed.",
698 get_field(*dmstatus, DM_DMSTATUS_VERSION), *dmstatus);
699 } else if (authenticated && !get_field(*dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
700 LOG_ERROR("Debugger is not authenticated to target Debug Module. "
701 "(dmstatus=0x%x). Use `riscv authdata_read` and "
702 "`riscv authdata_write` commands to authenticate.", *dmstatus);
703 return ERROR_FAIL;
704 }
705 return ERROR_OK;
706 }
707
708 int dmstatus_read(struct target *target, uint32_t *dmstatus,
709 bool authenticated)
710 {
711 return dmstatus_read_timeout(target, dmstatus, authenticated,
712 riscv_command_timeout_sec);
713 }
714
715 static void increase_ac_busy_delay(struct target *target)
716 {
717 riscv013_info_t *info = get_info(target);
718 info->ac_busy_delay += info->ac_busy_delay / 10 + 1;
719 LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
720 info->dtmcs_idle, info->dmi_busy_delay,
721 info->ac_busy_delay);
722 }
723
724 uint32_t abstract_register_size(unsigned width)
725 {
726 switch (width) {
727 case 32:
728 return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
729 case 64:
730 return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
731 case 128:
732 return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
733 default:
734 LOG_ERROR("Unsupported register width: %d", width);
735 return 0;
736 }
737 }
738
739 static int wait_for_idle(struct target *target, uint32_t *abstractcs)
740 {
741 RISCV013_INFO(info);
742 time_t start = time(NULL);
743 while (1) {
744 if (dmi_read(target, abstractcs, DM_ABSTRACTCS) != ERROR_OK)
745 return ERROR_FAIL;
746
747 if (get_field(*abstractcs, DM_ABSTRACTCS_BUSY) == 0)
748 return ERROR_OK;
749
750 if (time(NULL) - start > riscv_command_timeout_sec) {
751 info->cmderr = get_field(*abstractcs, DM_ABSTRACTCS_CMDERR);
752 if (info->cmderr != CMDERR_NONE) {
753 const char *errors[8] = {
754 "none",
755 "busy",
756 "not supported",
757 "exception",
758 "halt/resume",
759 "reserved",
760 "reserved",
761 "other" };
762
763 LOG_ERROR("Abstract command ended in error '%s' (abstractcs=0x%x)",
764 errors[info->cmderr], *abstractcs);
765 }
766
767 LOG_ERROR("Timed out after %ds waiting for busy to go low (abstractcs=0x%x). "
768 "Increase the timeout with riscv set_command_timeout_sec.",
769 riscv_command_timeout_sec,
770 *abstractcs);
771 return ERROR_FAIL;
772 }
773 }
774 }
775
776 static int execute_abstract_command(struct target *target, uint32_t command)
777 {
778 RISCV013_INFO(info);
779 if (debug_level >= LOG_LVL_DEBUG) {
780 switch (get_field(command, DM_COMMAND_CMDTYPE)) {
781 case 0:
782 LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, "
783 "transfer=%d, write=%d, regno=0x%x",
784 command,
785 8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE),
786 get_field(command, AC_ACCESS_REGISTER_POSTEXEC),
787 get_field(command, AC_ACCESS_REGISTER_TRANSFER),
788 get_field(command, AC_ACCESS_REGISTER_WRITE),
789 get_field(command, AC_ACCESS_REGISTER_REGNO));
790 break;
791 default:
792 LOG_DEBUG("command=0x%x", command);
793 break;
794 }
795 }
796
797 if (dmi_write_exec(target, DM_COMMAND, command, false) != ERROR_OK)
798 return ERROR_FAIL;
799
800 uint32_t abstractcs = 0;
801 int result = wait_for_idle(target, &abstractcs);
802
803 info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
804 if (info->cmderr != 0 || result != ERROR_OK) {
805 LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, abstractcs);
806 /* Clear the error. */
807 dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR);
808 return ERROR_FAIL;
809 }
810
811 return ERROR_OK;
812 }
813
814 static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
815 unsigned size_bits)
816 {
817 riscv_reg_t value = 0;
818 uint32_t v;
819 unsigned offset = index * size_bits / 32;
820 switch (size_bits) {
821 default:
822 LOG_ERROR("Unsupported size: %d bits", size_bits);
823 return ~0;
824 case 64:
825 dmi_read(target, &v, DM_DATA0 + offset + 1);
826 value |= ((uint64_t) v) << 32;
827 /* falls through */
828 case 32:
829 dmi_read(target, &v, DM_DATA0 + offset);
830 value |= v;
831 }
832 return value;
833 }
834
835 static int write_abstract_arg(struct target *target, unsigned index,
836 riscv_reg_t value, unsigned size_bits)
837 {
838 unsigned offset = index * size_bits / 32;
839 switch (size_bits) {
840 default:
841 LOG_ERROR("Unsupported size: %d bits", size_bits);
842 return ERROR_FAIL;
843 case 64:
844 dmi_write(target, DM_DATA0 + offset + 1, value >> 32);
845 /* falls through */
846 case 32:
847 dmi_write(target, DM_DATA0 + offset, value);
848 }
849 return ERROR_OK;
850 }
851
852 /**
853 * @par size in bits
854 */
855 static uint32_t access_register_command(struct target *target, uint32_t number,
856 unsigned size, uint32_t flags)
857 {
858 uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
859 switch (size) {
860 case 32:
861 command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
862 break;
863 case 64:
864 command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
865 break;
866 default:
867 LOG_ERROR("%d-bit register %s not supported.", size,
868 gdb_regno_name(number));
869 assert(0);
870 }
871
872 if (number <= GDB_REGNO_XPR31) {
873 command = set_field(command, AC_ACCESS_REGISTER_REGNO,
874 0x1000 + number - GDB_REGNO_ZERO);
875 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
876 command = set_field(command, AC_ACCESS_REGISTER_REGNO,
877 0x1020 + number - GDB_REGNO_FPR0);
878 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
879 command = set_field(command, AC_ACCESS_REGISTER_REGNO,
880 number - GDB_REGNO_CSR0);
881 } else if (number >= GDB_REGNO_COUNT) {
882 /* Custom register. */
883 assert(target->reg_cache->reg_list[number].arch_info);
884 riscv_reg_info_t *reg_info = target->reg_cache->reg_list[number].arch_info;
885 assert(reg_info);
886 command = set_field(command, AC_ACCESS_REGISTER_REGNO,
887 0xc000 + reg_info->custom_number);
888 } else {
889 assert(0);
890 }
891
892 command |= flags;
893
894 return command;
895 }
896
897 static int register_read_abstract(struct target *target, uint64_t *value,
898 uint32_t number, unsigned size)
899 {
900 RISCV013_INFO(info);
901
902 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
903 !info->abstract_read_fpr_supported)
904 return ERROR_FAIL;
905 if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
906 !info->abstract_read_csr_supported)
907 return ERROR_FAIL;
908 /* The spec doesn't define abstract register numbers for vector registers. */
909 if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31)
910 return ERROR_FAIL;
911
912 uint32_t command = access_register_command(target, number, size,
913 AC_ACCESS_REGISTER_TRANSFER);
914
915 int result = execute_abstract_command(target, command);
916 if (result != ERROR_OK) {
917 if (info->cmderr == CMDERR_NOT_SUPPORTED) {
918 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
919 info->abstract_read_fpr_supported = false;
920 LOG_INFO("Disabling abstract command reads from FPRs.");
921 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
922 info->abstract_read_csr_supported = false;
923 LOG_INFO("Disabling abstract command reads from CSRs.");
924 }
925 }
926 return result;
927 }
928
929 if (value)
930 *value = read_abstract_arg(target, 0, size);
931
932 return ERROR_OK;
933 }
934
935 static int register_write_abstract(struct target *target, uint32_t number,
936 uint64_t value, unsigned size)
937 {
938 RISCV013_INFO(info);
939
940 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
941 !info->abstract_write_fpr_supported)
942 return ERROR_FAIL;
943 if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
944 !info->abstract_write_csr_supported)
945 return ERROR_FAIL;
946
947 uint32_t command = access_register_command(target, number, size,
948 AC_ACCESS_REGISTER_TRANSFER |
949 AC_ACCESS_REGISTER_WRITE);
950
951 if (write_abstract_arg(target, 0, value, size) != ERROR_OK)
952 return ERROR_FAIL;
953
954 int result = execute_abstract_command(target, command);
955 if (result != ERROR_OK) {
956 if (info->cmderr == CMDERR_NOT_SUPPORTED) {
957 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
958 info->abstract_write_fpr_supported = false;
959 LOG_INFO("Disabling abstract command writes to FPRs.");
960 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
961 info->abstract_write_csr_supported = false;
962 LOG_INFO("Disabling abstract command writes to CSRs.");
963 }
964 }
965 return result;
966 }
967
968 return ERROR_OK;
969 }
970
971 /*
972 * Sets the AAMSIZE field of a memory access abstract command based on
973 * the width (bits).
974 */
975 static uint32_t abstract_memory_size(unsigned width)
976 {
977 switch (width) {
978 case 8:
979 return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
980 case 16:
981 return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
982 case 32:
983 return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
984 case 64:
985 return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
986 case 128:
987 return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
988 default:
989 LOG_ERROR("Unsupported memory width: %d", width);
990 return 0;
991 }
992 }
993
994 /*
995 * Creates a memory access abstract command.
996 */
997 static uint32_t access_memory_command(struct target *target, bool virtual,
998 unsigned width, bool postincrement, bool write)
999 {
1000 uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
1001 command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
1002 command |= abstract_memory_size(width);
1003 command = set_field(command, AC_ACCESS_MEMORY_AAMPOSTINCREMENT,
1004 postincrement);
1005 command = set_field(command, AC_ACCESS_MEMORY_WRITE, write);
1006
1007 return command;
1008 }
1009
1010 static int examine_progbuf(struct target *target)
1011 {
1012 riscv013_info_t *info = get_info(target);
1013
1014 if (info->progbuf_writable != YNM_MAYBE)
1015 return ERROR_OK;
1016
1017 /* Figure out if progbuf is writable. */
1018
1019 if (info->progbufsize < 1) {
1020 info->progbuf_writable = YNM_NO;
1021 LOG_INFO("No program buffer present.");
1022 return ERROR_OK;
1023 }
1024
1025 uint64_t s0;
1026 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
1027 return ERROR_FAIL;
1028
1029 struct riscv_program program;
1030 riscv_program_init(&program, target);
1031 riscv_program_insert(&program, auipc(S0));
1032 if (riscv_program_exec(&program, target) != ERROR_OK)
1033 return ERROR_FAIL;
1034
1035 if (register_read_direct(target, &info->progbuf_address, GDB_REGNO_S0) != ERROR_OK)
1036 return ERROR_FAIL;
1037
1038 riscv_program_init(&program, target);
1039 riscv_program_insert(&program, sw(S0, S0, 0));
1040 int result = riscv_program_exec(&program, target);
1041
1042 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
1043 return ERROR_FAIL;
1044
1045 if (result != ERROR_OK) {
1046 /* This program might have failed if the program buffer is not
1047 * writable. */
1048 info->progbuf_writable = YNM_NO;
1049 return ERROR_OK;
1050 }
1051
1052 uint32_t written;
1053 if (dmi_read(target, &written, DM_PROGBUF0) != ERROR_OK)
1054 return ERROR_FAIL;
1055 if (written == (uint32_t) info->progbuf_address) {
1056 LOG_INFO("progbuf is writable at 0x%" PRIx64,
1057 info->progbuf_address);
1058 info->progbuf_writable = YNM_YES;
1059
1060 } else {
1061 LOG_INFO("progbuf is not writeable at 0x%" PRIx64,
1062 info->progbuf_address);
1063 info->progbuf_writable = YNM_NO;
1064 }
1065
1066 return ERROR_OK;
1067 }
1068
1069 static int is_fpu_reg(uint32_t gdb_regno)
1070 {
1071 return (gdb_regno >= GDB_REGNO_FPR0 && gdb_regno <= GDB_REGNO_FPR31) ||
1072 (gdb_regno == GDB_REGNO_CSR0 + CSR_FFLAGS) ||
1073 (gdb_regno == GDB_REGNO_CSR0 + CSR_FRM) ||
1074 (gdb_regno == GDB_REGNO_CSR0 + CSR_FCSR);
1075 }
1076
1077 static int is_vector_reg(uint32_t gdb_regno)
1078 {
1079 return (gdb_regno >= GDB_REGNO_V0 && gdb_regno <= GDB_REGNO_V31) ||
1080 gdb_regno == GDB_REGNO_VSTART ||
1081 gdb_regno == GDB_REGNO_VXSAT ||
1082 gdb_regno == GDB_REGNO_VXRM ||
1083 gdb_regno == GDB_REGNO_VL ||
1084 gdb_regno == GDB_REGNO_VTYPE ||
1085 gdb_regno == GDB_REGNO_VLENB;
1086 }
1087
1088 static int prep_for_register_access(struct target *target, uint64_t *mstatus,
1089 int regno)
1090 {
1091 if (is_fpu_reg(regno) || is_vector_reg(regno)) {
1092 if (register_read(target, mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
1093 return ERROR_FAIL;
1094 if (is_fpu_reg(regno) && (*mstatus & MSTATUS_FS) == 0) {
1095 if (register_write_direct(target, GDB_REGNO_MSTATUS,
1096 set_field(*mstatus, MSTATUS_FS, 1)) != ERROR_OK)
1097 return ERROR_FAIL;
1098 } else if (is_vector_reg(regno) && (*mstatus & MSTATUS_VS) == 0) {
1099 if (register_write_direct(target, GDB_REGNO_MSTATUS,
1100 set_field(*mstatus, MSTATUS_VS, 1)) != ERROR_OK)
1101 return ERROR_FAIL;
1102 }
1103 } else {
1104 *mstatus = 0;
1105 }
1106 return ERROR_OK;
1107 }
1108
1109 static int cleanup_after_register_access(struct target *target,
1110 uint64_t mstatus, int regno)
1111 {
1112 if ((is_fpu_reg(regno) && (mstatus & MSTATUS_FS) == 0) ||
1113 (is_vector_reg(regno) && (mstatus & MSTATUS_VS) == 0))
1114 if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
1115 return ERROR_FAIL;
1116 return ERROR_OK;
1117 }
1118
1119 typedef enum {
1120 SPACE_DM_DATA,
1121 SPACE_DMI_PROGBUF,
1122 SPACE_DMI_RAM
1123 } memory_space_t;
1124
1125 typedef struct {
1126 /* How can the debugger access this memory? */
1127 memory_space_t memory_space;
1128 /* Memory address to access the scratch memory from the hart. */
1129 riscv_addr_t hart_address;
1130 /* Memory address to access the scratch memory from the debugger. */
1131 riscv_addr_t debug_address;
1132 struct working_area *area;
1133 } scratch_mem_t;
1134
1135 /**
1136 * Find some scratch memory to be used with the given program.
1137 */
1138 static int scratch_reserve(struct target *target,
1139 scratch_mem_t *scratch,
1140 struct riscv_program *program,
1141 unsigned size_bytes)
1142 {
1143 riscv_addr_t alignment = 1;
1144 while (alignment < size_bytes)
1145 alignment *= 2;
1146
1147 scratch->area = NULL;
1148
1149 riscv013_info_t *info = get_info(target);
1150
1151 /* Option 1: See if data# registers can be used as the scratch memory */
1152 if (info->dataaccess == 1) {
1153 /* Sign extend dataaddr. */
1154 scratch->hart_address = info->dataaddr;
1155 if (info->dataaddr & (1<<11))
1156 scratch->hart_address |= 0xfffffffffffff000ULL;
1157 /* Align. */
1158 scratch->hart_address = (scratch->hart_address + alignment - 1) & ~(alignment - 1);
1159
1160 if ((size_bytes + scratch->hart_address - info->dataaddr + 3) / 4 >=
1161 info->datasize) {
1162 scratch->memory_space = SPACE_DM_DATA;
1163 scratch->debug_address = (scratch->hart_address - info->dataaddr) / 4;
1164 return ERROR_OK;
1165 }
1166 }
1167
1168 /* Option 2: See if progbuf can be used as the scratch memory */
1169 if (examine_progbuf(target) != ERROR_OK)
1170 return ERROR_FAIL;
1171
1172 /* Allow for ebreak at the end of the program. */
1173 unsigned program_size = (program->instruction_count + 1) * 4;
1174 scratch->hart_address = (info->progbuf_address + program_size + alignment - 1) &
1175 ~(alignment - 1);
1176 if ((info->progbuf_writable == YNM_YES) &&
1177 ((size_bytes + scratch->hart_address - info->progbuf_address + 3) / 4 >=
1178 info->progbufsize)) {
1179 scratch->memory_space = SPACE_DMI_PROGBUF;
1180 scratch->debug_address = (scratch->hart_address - info->progbuf_address) / 4;
1181 return ERROR_OK;
1182 }
1183
1184 /* Option 3: User-configured memory area as scratch RAM */
1185 if (target_alloc_working_area(target, size_bytes + alignment - 1,
1186 &scratch->area) == ERROR_OK) {
1187 scratch->hart_address = (scratch->area->address + alignment - 1) &
1188 ~(alignment - 1);
1189 scratch->memory_space = SPACE_DMI_RAM;
1190 scratch->debug_address = scratch->hart_address;
1191 return ERROR_OK;
1192 }
1193
1194 LOG_ERROR("Couldn't find %d bytes of scratch RAM to use. Please configure "
1195 "a work area with 'configure -work-area-phys'.", size_bytes);
1196 return ERROR_FAIL;
1197 }
1198
1199 static int scratch_release(struct target *target,
1200 scratch_mem_t *scratch)
1201 {
1202 if (scratch->area)
1203 return target_free_working_area(target, scratch->area);
1204
1205 return ERROR_OK;
1206 }
1207
1208 static int scratch_read64(struct target *target, scratch_mem_t *scratch,
1209 uint64_t *value)
1210 {
1211 uint32_t v;
1212 switch (scratch->memory_space) {
1213 case SPACE_DM_DATA:
1214 if (dmi_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
1215 return ERROR_FAIL;
1216 *value = v;
1217 if (dmi_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
1218 return ERROR_FAIL;
1219 *value |= ((uint64_t) v) << 32;
1220 break;
1221 case SPACE_DMI_PROGBUF:
1222 if (dmi_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
1223 return ERROR_FAIL;
1224 *value = v;
1225 if (dmi_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
1226 return ERROR_FAIL;
1227 *value |= ((uint64_t) v) << 32;
1228 break;
1229 case SPACE_DMI_RAM:
1230 {
1231 uint8_t buffer[8] = {0};
1232 if (read_memory(target, scratch->debug_address, 4, 2, buffer, 4) != ERROR_OK)
1233 return ERROR_FAIL;
1234 *value = buffer[0] |
1235 (((uint64_t) buffer[1]) << 8) |
1236 (((uint64_t) buffer[2]) << 16) |
1237 (((uint64_t) buffer[3]) << 24) |
1238 (((uint64_t) buffer[4]) << 32) |
1239 (((uint64_t) buffer[5]) << 40) |
1240 (((uint64_t) buffer[6]) << 48) |
1241 (((uint64_t) buffer[7]) << 56);
1242 }
1243 break;
1244 }
1245 return ERROR_OK;
1246 }
1247
1248 static int scratch_write64(struct target *target, scratch_mem_t *scratch,
1249 uint64_t value)
1250 {
1251 switch (scratch->memory_space) {
1252 case SPACE_DM_DATA:
1253 dmi_write(target, DM_DATA0 + scratch->debug_address, value);
1254 dmi_write(target, DM_DATA1 + scratch->debug_address, value >> 32);
1255 break;
1256 case SPACE_DMI_PROGBUF:
1257 dmi_write(target, DM_PROGBUF0 + scratch->debug_address, value);
1258 dmi_write(target, DM_PROGBUF1 + scratch->debug_address, value >> 32);
1259 break;
1260 case SPACE_DMI_RAM:
1261 {
1262 uint8_t buffer[8] = {
1263 value,
1264 value >> 8,
1265 value >> 16,
1266 value >> 24,
1267 value >> 32,
1268 value >> 40,
1269 value >> 48,
1270 value >> 56
1271 };
1272 if (write_memory(target, scratch->debug_address, 4, 2, buffer) != ERROR_OK)
1273 return ERROR_FAIL;
1274 }
1275 break;
1276 }
1277 return ERROR_OK;
1278 }
1279
1280 /** Return register size in bits. */
1281 static unsigned register_size(struct target *target, unsigned number)
1282 {
1283 /* If reg_cache hasn't been initialized yet, make a guess. We need this for
1284 * when this function is called during examine(). */
1285 if (target->reg_cache)
1286 return target->reg_cache->reg_list[number].size;
1287 else
1288 return riscv_xlen(target);
1289 }
1290
1291 static bool has_sufficient_progbuf(struct target *target, unsigned size)
1292 {
1293 RISCV013_INFO(info);
1294 RISCV_INFO(r);
1295
1296 return info->progbufsize + r->impebreak >= size;
1297 }
1298
1299 /**
1300 * Immediately write the new value to the requested register. This mechanism
1301 * bypasses any caches.
1302 */
1303 static int register_write_direct(struct target *target, unsigned number,
1304 uint64_t value)
1305 {
1306 LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
1307 gdb_regno_name(number), value);
1308
1309 int result = register_write_abstract(target, number, value,
1310 register_size(target, number));
1311 if (result == ERROR_OK || !has_sufficient_progbuf(target, 2) ||
1312 !riscv_is_halted(target))
1313 return result;
1314
1315 struct riscv_program program;
1316 riscv_program_init(&program, target);
1317
1318 uint64_t s0;
1319 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
1320 return ERROR_FAIL;
1321
1322 uint64_t mstatus;
1323 if (prep_for_register_access(target, &mstatus, number) != ERROR_OK)
1324 return ERROR_FAIL;
1325
1326 scratch_mem_t scratch;
1327 bool use_scratch = false;
1328 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
1329 riscv_supports_extension(target, 'D') &&
1330 riscv_xlen(target) < 64) {
1331 /* There are no instructions to move all the bits from a register, so
1332 * we need to use some scratch RAM. */
1333 use_scratch = true;
1334 riscv_program_insert(&program, fld(number - GDB_REGNO_FPR0, S0, 0));
1335
1336 if (scratch_reserve(target, &scratch, &program, 8) != ERROR_OK)
1337 return ERROR_FAIL;
1338
1339 if (register_write_direct(target, GDB_REGNO_S0, scratch.hart_address)
1340 != ERROR_OK) {
1341 scratch_release(target, &scratch);
1342 return ERROR_FAIL;
1343 }
1344
1345 if (scratch_write64(target, &scratch, value) != ERROR_OK) {
1346 scratch_release(target, &scratch);
1347 return ERROR_FAIL;
1348 }
1349
1350 } else if (number == GDB_REGNO_VTYPE) {
1351 riscv_program_insert(&program, csrr(S0, CSR_VL));
1352 riscv_program_insert(&program, vsetvli(ZERO, S0, value));
1353
1354 } else {
1355 if (register_write_direct(target, GDB_REGNO_S0, value) != ERROR_OK)
1356 return ERROR_FAIL;
1357
1358 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1359 if (riscv_supports_extension(target, 'D'))
1360 riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0));
1361 else
1362 riscv_program_insert(&program, fmv_w_x(number - GDB_REGNO_FPR0, S0));
1363 } else if (number == GDB_REGNO_VL) {
1364 /* "The XLEN-bit-wide read-only vl CSR can only be updated by the
1365 * vsetvli and vsetvl instructions, and the fault-only-rst vector
1366 * load instruction variants." */
1367 riscv_reg_t vtype;
1368 if (register_read(target, &vtype, GDB_REGNO_VTYPE) != ERROR_OK)
1369 return ERROR_FAIL;
1370 if (riscv_program_insert(&program, vsetvli(ZERO, S0, vtype)) != ERROR_OK)
1371 return ERROR_FAIL;
1372 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1373 riscv_program_csrw(&program, S0, number);
1374 } else {
1375 LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number);
1376 return ERROR_FAIL;
1377 }
1378 }
1379
1380 int exec_out = riscv_program_exec(&program, target);
1381 /* Don't message on error. Probably the register doesn't exist. */
1382 if (exec_out == ERROR_OK && target->reg_cache) {
1383 struct reg *reg = &target->reg_cache->reg_list[number];
1384 buf_set_u64(reg->value, 0, reg->size, value);
1385 }
1386
1387 if (use_scratch)
1388 scratch_release(target, &scratch);
1389
1390 if (cleanup_after_register_access(target, mstatus, number) != ERROR_OK)
1391 return ERROR_FAIL;
1392
1393 /* Restore S0. */
1394 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
1395 return ERROR_FAIL;
1396
1397 return exec_out;
1398 }
1399
1400 /** Read register value from the target. Also update the cached value. */
1401 static int register_read(struct target *target, uint64_t *value, uint32_t number)
1402 {
1403 if (number == GDB_REGNO_ZERO) {
1404 *value = 0;
1405 return ERROR_OK;
1406 }
1407 int result = register_read_direct(target, value, number);
1408 if (result != ERROR_OK)
1409 return ERROR_FAIL;
1410 if (target->reg_cache) {
1411 struct reg *reg = &target->reg_cache->reg_list[number];
1412 buf_set_u64(reg->value, 0, reg->size, *value);
1413 }
1414 return ERROR_OK;
1415 }
1416
1417 /** Actually read registers from the target right now. */
1418 static int register_read_direct(struct target *target, uint64_t *value, uint32_t number)
1419 {
1420 int result = register_read_abstract(target, value, number,
1421 register_size(target, number));
1422
1423 if (result != ERROR_OK &&
1424 has_sufficient_progbuf(target, 2) &&
1425 number > GDB_REGNO_XPR31) {
1426 struct riscv_program program;
1427 riscv_program_init(&program, target);
1428
1429 scratch_mem_t scratch;
1430 bool use_scratch = false;
1431
1432 riscv_reg_t s0;
1433 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
1434 return ERROR_FAIL;
1435
1436 /* Write program to move data into s0. */
1437
1438 uint64_t mstatus;
1439 if (prep_for_register_access(target, &mstatus, number) != ERROR_OK)
1440 return ERROR_FAIL;
1441
1442 if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1443 if (riscv_supports_extension(target, 'D')
1444 && riscv_xlen(target) < 64) {
1445 /* There are no instructions to move all the bits from a
1446 * register, so we need to use some scratch RAM. */
1447 riscv_program_insert(&program, fsd(number - GDB_REGNO_FPR0, S0,
1448 0));
1449
1450 if (scratch_reserve(target, &scratch, &program, 8) != ERROR_OK)
1451 return ERROR_FAIL;
1452 use_scratch = true;
1453
1454 if (register_write_direct(target, GDB_REGNO_S0,
1455 scratch.hart_address) != ERROR_OK) {
1456 scratch_release(target, &scratch);
1457 return ERROR_FAIL;
1458 }
1459 } else if (riscv_supports_extension(target, 'D')) {
1460 riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0));
1461 } else {
1462 riscv_program_insert(&program, fmv_x_w(S0, number - GDB_REGNO_FPR0));
1463 }
1464 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1465 riscv_program_csrr(&program, S0, number);
1466 } else {
1467 LOG_ERROR("Unsupported register: %s", gdb_regno_name(number));
1468 return ERROR_FAIL;
1469 }
1470
1471 /* Execute program. */
1472 result = riscv_program_exec(&program, target);
1473 /* Don't message on error. Probably the register doesn't exist. */
1474
1475 if (use_scratch) {
1476 result = scratch_read64(target, &scratch, value);
1477 scratch_release(target, &scratch);
1478 if (result != ERROR_OK)
1479 return result;
1480 } else {
1481 /* Read S0 */
1482 if (register_read_direct(target, value, GDB_REGNO_S0) != ERROR_OK)
1483 return ERROR_FAIL;
1484 }
1485
1486 if (cleanup_after_register_access(target, mstatus, number) != ERROR_OK)
1487 return ERROR_FAIL;
1488
1489 /* Restore S0. */
1490 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
1491 return ERROR_FAIL;
1492 }
1493
1494 if (result == ERROR_OK) {
1495 LOG_DEBUG("{%d} %s = 0x%" PRIx64, riscv_current_hartid(target),
1496 gdb_regno_name(number), *value);
1497 }
1498
1499 return result;
1500 }
1501
1502 static int wait_for_authbusy(struct target *target, uint32_t *dmstatus)
1503 {
1504 time_t start = time(NULL);
1505 while (1) {
1506 uint32_t value;
1507 if (dmstatus_read(target, &value, false) != ERROR_OK)
1508 return ERROR_FAIL;
1509 if (dmstatus)
1510 *dmstatus = value;
1511 if (!get_field(value, DM_DMSTATUS_AUTHBUSY))
1512 break;
1513 if (time(NULL) - start > riscv_command_timeout_sec) {
1514 LOG_ERROR("Timed out after %ds waiting for authbusy to go low (dmstatus=0x%x). "
1515 "Increase the timeout with riscv set_command_timeout_sec.",
1516 riscv_command_timeout_sec,
1517 value);
1518 return ERROR_FAIL;
1519 }
1520 }
1521
1522 return ERROR_OK;
1523 }
1524
1525 /*** OpenOCD target functions. ***/
1526
1527 static void deinit_target(struct target *target)
1528 {
1529 LOG_DEBUG("riscv_deinit_target()");
1530 riscv_info_t *info = (riscv_info_t *) target->arch_info;
1531 free(info->version_specific);
1532 /* TODO: free register arch_info */
1533 info->version_specific = NULL;
1534 }
1535
1536 static int set_haltgroup(struct target *target, bool *supported)
1537 {
1538 uint32_t write = set_field(DM_DMCS2_HGWRITE, DM_DMCS2_GROUP, target->smp);
1539 if (dmi_write(target, DM_DMCS2, write) != ERROR_OK)
1540 return ERROR_FAIL;
1541 uint32_t read;
1542 if (dmi_read(target, &read, DM_DMCS2) != ERROR_OK)
1543 return ERROR_FAIL;
1544 *supported = get_field(read, DM_DMCS2_GROUP) == (unsigned)target->smp;
1545 return ERROR_OK;
1546 }
1547
1548 static int discover_vlenb(struct target *target)
1549 {
1550 RISCV_INFO(r);
1551 riscv_reg_t vlenb;
1552
1553 if (register_read(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) {
1554 LOG_WARNING("Couldn't read vlenb for %s; vector register access won't work.",
1555 target_name(target));
1556 r->vlenb = 0;
1557 return ERROR_OK;
1558 }
1559 r->vlenb = vlenb;
1560
1561 LOG_INFO("Vector support with vlenb=%d", r->vlenb);
1562
1563 return ERROR_OK;
1564 }
1565
1566 static int examine(struct target *target)
1567 {
1568 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1569
1570 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1571 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1572 LOG_DEBUG(" dmireset=%d", get_field(dtmcontrol, DTM_DTMCS_DMIRESET));
1573 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCS_IDLE));
1574 LOG_DEBUG(" dmistat=%d", get_field(dtmcontrol, DTM_DTMCS_DMISTAT));
1575 LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCS_ABITS));
1576 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCS_VERSION));
1577 if (dtmcontrol == 0) {
1578 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1579 return ERROR_FAIL;
1580 }
1581 if (get_field(dtmcontrol, DTM_DTMCS_VERSION) != 1) {
1582 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1583 get_field(dtmcontrol, DTM_DTMCS_VERSION), dtmcontrol);
1584 return ERROR_FAIL;
1585 }
1586
1587 riscv013_info_t *info = get_info(target);
1588 /* TODO: This won't be true if there are multiple DMs. */
1589 info->index = target->coreid;
1590 info->abits = get_field(dtmcontrol, DTM_DTMCS_ABITS);
1591 info->dtmcs_idle = get_field(dtmcontrol, DTM_DTMCS_IDLE);
1592
1593 /* Reset the Debug Module. */
1594 dm013_info_t *dm = get_dm(target);
1595 if (!dm)
1596 return ERROR_FAIL;
1597 if (!dm->was_reset) {
1598 dmi_write(target, DM_DMCONTROL, 0);
1599 dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_DMACTIVE);
1600 dm->was_reset = true;
1601 }
1602
1603 dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO |
1604 DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE |
1605 DM_DMCONTROL_HASEL);
1606 uint32_t dmcontrol;
1607 if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK)
1608 return ERROR_FAIL;
1609
1610 if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
1611 LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x",
1612 dmcontrol);
1613 return ERROR_FAIL;
1614 }
1615
1616 dm->hasel_supported = get_field(dmcontrol, DM_DMCONTROL_HASEL);
1617
1618 uint32_t dmstatus;
1619 if (dmstatus_read(target, &dmstatus, false) != ERROR_OK)
1620 return ERROR_FAIL;
1621 LOG_DEBUG("dmstatus: 0x%08x", dmstatus);
1622 int dmstatus_version = get_field(dmstatus, DM_DMSTATUS_VERSION);
1623 if (dmstatus_version != 2 && dmstatus_version != 3) {
1624 /* Error was already printed out in dmstatus_read(). */
1625 return ERROR_FAIL;
1626 }
1627
1628 uint32_t hartsel =
1629 (get_field(dmcontrol, DM_DMCONTROL_HARTSELHI) <<
1630 DM_DMCONTROL_HARTSELLO_LENGTH) |
1631 get_field(dmcontrol, DM_DMCONTROL_HARTSELLO);
1632 info->hartsellen = 0;
1633 while (hartsel & 1) {
1634 info->hartsellen++;
1635 hartsel >>= 1;
1636 }
1637 LOG_DEBUG("hartsellen=%d", info->hartsellen);
1638
1639 uint32_t hartinfo;
1640 if (dmi_read(target, &hartinfo, DM_HARTINFO) != ERROR_OK)
1641 return ERROR_FAIL;
1642
1643 info->datasize = get_field(hartinfo, DM_HARTINFO_DATASIZE);
1644 info->dataaccess = get_field(hartinfo, DM_HARTINFO_DATAACCESS);
1645 info->dataaddr = get_field(hartinfo, DM_HARTINFO_DATAADDR);
1646
1647 if (!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
1648 LOG_ERROR("Debugger is not authenticated to target Debug Module. "
1649 "(dmstatus=0x%x). Use `riscv authdata_read` and "
1650 "`riscv authdata_write` commands to authenticate.", dmstatus);
1651 /* If we return ERROR_FAIL here, then in a multicore setup the next
1652 * core won't be examined, which means we won't set up the
1653 * authentication commands for them, which means the config script
1654 * needs to be a lot more complex. */
1655 return ERROR_OK;
1656 }
1657
1658 if (dmi_read(target, &info->sbcs, DM_SBCS) != ERROR_OK)
1659 return ERROR_FAIL;
1660
1661 /* Check that abstract data registers are accessible. */
1662 uint32_t abstractcs;
1663 if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK)
1664 return ERROR_FAIL;
1665 info->datacount = get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT);
1666 info->progbufsize = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE);
1667
1668 LOG_INFO("datacount=%d progbufsize=%d", info->datacount, info->progbufsize);
1669
1670 RISCV_INFO(r);
1671 r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK);
1672
1673 if (!has_sufficient_progbuf(target, 2)) {
1674 LOG_WARNING("We won't be able to execute fence instructions on this "
1675 "target. Memory may not always appear consistent. "
1676 "(progbufsize=%d, impebreak=%d)", info->progbufsize,
1677 r->impebreak);
1678 }
1679
1680 if (info->progbufsize < 4 && riscv_enable_virtual) {
1681 LOG_ERROR("set_enable_virtual is not available on this target. It "
1682 "requires a program buffer size of at least 4. (progbufsize=%d) "
1683 "Use `riscv set_enable_virtual off` to continue."
1684 , info->progbufsize);
1685 }
1686
1687 /* Before doing anything else we must first enumerate the harts. */
1688 if (dm->hart_count < 0) {
1689 for (int i = 0; i < MIN(RISCV_MAX_HARTS, 1 << info->hartsellen); ++i) {
1690 r->current_hartid = i;
1691 if (riscv013_select_current_hart(target) != ERROR_OK)
1692 return ERROR_FAIL;
1693
1694 uint32_t s;
1695 if (dmstatus_read(target, &s, true) != ERROR_OK)
1696 return ERROR_FAIL;
1697 if (get_field(s, DM_DMSTATUS_ANYNONEXISTENT))
1698 break;
1699 dm->hart_count = i + 1;
1700
1701 if (get_field(s, DM_DMSTATUS_ANYHAVERESET))
1702 dmi_write(target, DM_DMCONTROL,
1703 set_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i));
1704 }
1705
1706 LOG_DEBUG("Detected %d harts.", dm->hart_count);
1707 }
1708
1709 r->current_hartid = target->coreid;
1710
1711 if (dm->hart_count == 0) {
1712 LOG_ERROR("No harts found!");
1713 return ERROR_FAIL;
1714 }
1715
1716 /* Don't call any riscv_* functions until after we've counted the number of
1717 * cores and initialized registers. */
1718
1719 if (riscv013_select_current_hart(target) != ERROR_OK)
1720 return ERROR_FAIL;
1721
1722 bool halted = riscv_is_halted(target);
1723 if (!halted) {
1724 if (riscv013_halt_go(target) != ERROR_OK) {
1725 LOG_ERROR("Fatal: Hart %d failed to halt during examine()", r->current_hartid);
1726 return ERROR_FAIL;
1727 }
1728 }
1729
1730 /* Without knowing anything else we can at least mess with the
1731 * program buffer. */
1732 r->debug_buffer_size = info->progbufsize;
1733
1734 int result = register_read_abstract(target, NULL, GDB_REGNO_S0, 64);
1735 if (result == ERROR_OK)
1736 r->xlen = 64;
1737 else
1738 r->xlen = 32;
1739
1740 if (register_read(target, &r->misa, GDB_REGNO_MISA)) {
1741 LOG_ERROR("Fatal: Failed to read MISA from hart %d.", r->current_hartid);
1742 return ERROR_FAIL;
1743 }
1744
1745 if (riscv_supports_extension(target, 'V')) {
1746 if (discover_vlenb(target) != ERROR_OK)
1747 return ERROR_FAIL;
1748 }
1749
1750 /* Now init registers based on what we discovered. */
1751 if (riscv_init_registers(target) != ERROR_OK)
1752 return ERROR_FAIL;
1753
1754 /* Display this as early as possible to help people who are using
1755 * really slow simulators. */
1756 LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
1757 r->misa);
1758
1759 if (!halted)
1760 riscv013_step_or_resume_current_hart(target, false, false);
1761
1762 target_set_examined(target);
1763
1764 if (target->smp) {
1765 bool haltgroup_supported;
1766 if (set_haltgroup(target, &haltgroup_supported) != ERROR_OK)
1767 return ERROR_FAIL;
1768 if (haltgroup_supported)
1769 LOG_INFO("Core %d made part of halt group %d.", target->coreid,
1770 target->smp);
1771 else
1772 LOG_INFO("Core %d could not be made part of halt group %d.",
1773 target->coreid, target->smp);
1774 }
1775
1776 /* Some regression suites rely on seeing 'Examined RISC-V core' to know
1777 * when they can connect with gdb/telnet.
1778 * We will need to update those suites if we want to change that text. */
1779 LOG_INFO("Examined RISC-V core; found %d harts",
1780 riscv_count_harts(target));
1781 LOG_INFO(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
1782 r->misa);
1783 return ERROR_OK;
1784 }
1785
1786 static int riscv013_authdata_read(struct target *target, uint32_t *value, unsigned int index)
1787 {
1788 if (index > 0) {
1789 LOG_ERROR("Spec 0.13 only has a single authdata register.");
1790 return ERROR_FAIL;
1791 }
1792
1793 if (wait_for_authbusy(target, NULL) != ERROR_OK)
1794 return ERROR_FAIL;
1795
1796 return dmi_read(target, value, DM_AUTHDATA);
1797 }
1798
1799 static int riscv013_authdata_write(struct target *target, uint32_t value, unsigned int index)
1800 {
1801 if (index > 0) {
1802 LOG_ERROR("Spec 0.13 only has a single authdata register.");
1803 return ERROR_FAIL;
1804 }
1805
1806 uint32_t before, after;
1807 if (wait_for_authbusy(target, &before) != ERROR_OK)
1808 return ERROR_FAIL;
1809
1810 dmi_write(target, DM_AUTHDATA, value);
1811
1812 if (wait_for_authbusy(target, &after) != ERROR_OK)
1813 return ERROR_FAIL;
1814
1815 if (!get_field(before, DM_DMSTATUS_AUTHENTICATED) &&
1816 get_field(after, DM_DMSTATUS_AUTHENTICATED)) {
1817 LOG_INFO("authdata_write resulted in successful authentication");
1818 int result = ERROR_OK;
1819 dm013_info_t *dm = get_dm(target);
1820 if (!dm)
1821 return ERROR_FAIL;
1822 target_list_t *entry;
1823 list_for_each_entry(entry, &dm->target_list, list) {
1824 if (examine(entry->target) != ERROR_OK)
1825 result = ERROR_FAIL;
1826 }
1827 return result;
1828 }
1829
1830 return ERROR_OK;
1831 }
1832
1833 static int riscv013_hart_count(struct target *target)
1834 {
1835 dm013_info_t *dm = get_dm(target);
1836 assert(dm);
1837 return dm->hart_count;
1838 }
1839
1840 /* Try to find out the widest memory access size depending on the selected memory access methods. */
1841 static unsigned riscv013_data_bits(struct target *target)
1842 {
1843 RISCV013_INFO(info);
1844 RISCV_INFO(r);
1845
1846 for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
1847 int method = r->mem_access_methods[i];
1848
1849 if (method == RISCV_MEM_ACCESS_PROGBUF) {
1850 if (has_sufficient_progbuf(target, 3))
1851 return riscv_xlen(target);
1852 } else if (method == RISCV_MEM_ACCESS_SYSBUS) {
1853 if (get_field(info->sbcs, DM_SBCS_SBACCESS128))
1854 return 128;
1855 if (get_field(info->sbcs, DM_SBCS_SBACCESS64))
1856 return 64;
1857 if (get_field(info->sbcs, DM_SBCS_SBACCESS32))
1858 return 32;
1859 if (get_field(info->sbcs, DM_SBCS_SBACCESS16))
1860 return 16;
1861 if (get_field(info->sbcs, DM_SBCS_SBACCESS8))
1862 return 8;
1863 } else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
1864 /* TODO: Once there is a spec for discovering abstract commands, we can
1865 * take those into account as well. For now we assume abstract commands
1866 * support XLEN-wide accesses. */
1867 return riscv_xlen(target);
1868 } else if (method == RISCV_MEM_ACCESS_UNSPECIFIED)
1869 /* No further mem access method to try. */
1870 break;
1871 }
1872 LOG_ERROR("Unable to determine supported data bits on this target. Assuming 32 bits.");
1873 return 32;
1874 }
1875
1876 COMMAND_HELPER(riscv013_print_info, struct target *target)
1877 {
1878 RISCV013_INFO(info);
1879
1880 /* Abstract description. */
1881 riscv_print_info_line(CMD, "target", "memory.read_while_running8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
1882 riscv_print_info_line(CMD, "target", "memory.write_while_running8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
1883 riscv_print_info_line(CMD, "target", "memory.read_while_running16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
1884 riscv_print_info_line(CMD, "target", "memory.write_while_running16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
1885 riscv_print_info_line(CMD, "target", "memory.read_while_running32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
1886 riscv_print_info_line(CMD, "target", "memory.write_while_running32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
1887 riscv_print_info_line(CMD, "target", "memory.read_while_running64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
1888 riscv_print_info_line(CMD, "target", "memory.write_while_running64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
1889 riscv_print_info_line(CMD, "target", "memory.read_while_running128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
1890 riscv_print_info_line(CMD, "target", "memory.write_while_running128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
1891
1892 /* Lower level description. */
1893 riscv_print_info_line(CMD, "dm", "abits", info->abits);
1894 riscv_print_info_line(CMD, "dm", "progbufsize", info->progbufsize);
1895 riscv_print_info_line(CMD, "dm", "sbversion", get_field(info->sbcs, DM_SBCS_SBVERSION));
1896 riscv_print_info_line(CMD, "dm", "sbasize", get_field(info->sbcs, DM_SBCS_SBASIZE));
1897 riscv_print_info_line(CMD, "dm", "sbaccess128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
1898 riscv_print_info_line(CMD, "dm", "sbaccess64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
1899 riscv_print_info_line(CMD, "dm", "sbaccess32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
1900 riscv_print_info_line(CMD, "dm", "sbaccess16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
1901 riscv_print_info_line(CMD, "dm", "sbaccess8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
1902
1903 uint32_t dmstatus;
1904 if (dmstatus_read(target, &dmstatus, false) == ERROR_OK)
1905 riscv_print_info_line(CMD, "dm", "authenticated", get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED));
1906
1907 return 0;
1908 }
1909
1910 static int prep_for_vector_access(struct target *target, uint64_t *vtype,
1911 uint64_t *vl, unsigned *debug_vl)
1912 {
1913 RISCV_INFO(r);
1914 /* TODO: this continuous save/restore is terrible for performance. */
1915 /* Write vtype and vl. */
1916 unsigned encoded_vsew;
1917 switch (riscv_xlen(target)) {
1918 case 32:
1919 encoded_vsew = 2;
1920 break;
1921 case 64:
1922 encoded_vsew = 3;
1923 break;
1924 default:
1925 LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1926 return ERROR_FAIL;
1927 }
1928
1929 /* Save vtype and vl. */
1930 if (register_read(target, vtype, GDB_REGNO_VTYPE) != ERROR_OK)
1931 return ERROR_FAIL;
1932 if (register_read(target, vl, GDB_REGNO_VL) != ERROR_OK)
1933 return ERROR_FAIL;
1934
1935 if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 3) != ERROR_OK)
1936 return ERROR_FAIL;
1937 *debug_vl = DIV_ROUND_UP(r->vlenb * 8, riscv_xlen(target));
1938 if (register_write_direct(target, GDB_REGNO_VL, *debug_vl) != ERROR_OK)
1939 return ERROR_FAIL;
1940
1941 return ERROR_OK;
1942 }
1943
1944 static int cleanup_after_vector_access(struct target *target, uint64_t vtype,
1945 uint64_t vl)
1946 {
1947 /* Restore vtype and vl. */
1948 if (register_write_direct(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
1949 return ERROR_FAIL;
1950 if (register_write_direct(target, GDB_REGNO_VL, vl) != ERROR_OK)
1951 return ERROR_FAIL;
1952 return ERROR_OK;
1953 }
1954
1955 static int riscv013_get_register_buf(struct target *target,
1956 uint8_t *value, int regno)
1957 {
1958 assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
1959
1960 if (riscv_select_current_hart(target) != ERROR_OK)
1961 return ERROR_FAIL;
1962
1963 riscv_reg_t s0;
1964 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
1965 return ERROR_FAIL;
1966
1967 uint64_t mstatus;
1968 if (prep_for_register_access(target, &mstatus, regno) != ERROR_OK)
1969 return ERROR_FAIL;
1970
1971 uint64_t vtype, vl;
1972 unsigned debug_vl;
1973 if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK)
1974 return ERROR_FAIL;
1975
1976 unsigned vnum = regno - GDB_REGNO_V0;
1977 unsigned xlen = riscv_xlen(target);
1978
1979 struct riscv_program program;
1980 riscv_program_init(&program, target);
1981 riscv_program_insert(&program, vmv_x_s(S0, vnum));
1982 riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
1983
1984 int result = ERROR_OK;
1985 for (unsigned i = 0; i < debug_vl; i++) {
1986 /* Executing the program might result in an exception if there is some
1987 * issue with the vector implementation/instructions we're using. If that
1988 * happens, attempt to restore as usual. We may have clobbered the
1989 * vector register we tried to read already.
1990 * For other failures, we just return error because things are probably
1991 * so messed up that attempting to restore isn't going to help. */
1992 result = riscv_program_exec(&program, target);
1993 if (result == ERROR_OK) {
1994 uint64_t v;
1995 if (register_read_direct(target, &v, GDB_REGNO_S0) != ERROR_OK)
1996 return ERROR_FAIL;
1997 buf_set_u64(value, xlen * i, xlen, v);
1998 } else {
1999 break;
2000 }
2001 }
2002
2003 if (cleanup_after_vector_access(target, vtype, vl) != ERROR_OK)
2004 return ERROR_FAIL;
2005
2006 if (cleanup_after_register_access(target, mstatus, regno) != ERROR_OK)
2007 return ERROR_FAIL;
2008 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
2009 return ERROR_FAIL;
2010
2011 return result;
2012 }
2013
2014 static int riscv013_set_register_buf(struct target *target,
2015 int regno, const uint8_t *value)
2016 {
2017 assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
2018
2019 if (riscv_select_current_hart(target) != ERROR_OK)
2020 return ERROR_FAIL;
2021
2022 riscv_reg_t s0;
2023 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
2024 return ERROR_FAIL;
2025
2026 uint64_t mstatus;
2027 if (prep_for_register_access(target, &mstatus, regno) != ERROR_OK)
2028 return ERROR_FAIL;
2029
2030 uint64_t vtype, vl;
2031 unsigned debug_vl;
2032 if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK)
2033 return ERROR_FAIL;
2034
2035 unsigned vnum = regno - GDB_REGNO_V0;
2036 unsigned xlen = riscv_xlen(target);
2037
2038 struct riscv_program program;
2039 riscv_program_init(&program, target);
2040 riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
2041 int result = ERROR_OK;
2042 for (unsigned i = 0; i < debug_vl; i++) {
2043 if (register_write_direct(target, GDB_REGNO_S0,
2044 buf_get_u64(value, xlen * i, xlen)) != ERROR_OK)
2045 return ERROR_FAIL;
2046 result = riscv_program_exec(&program, target);
2047 if (result != ERROR_OK)
2048 break;
2049 }
2050
2051 if (cleanup_after_vector_access(target, vtype, vl) != ERROR_OK)
2052 return ERROR_FAIL;
2053
2054 if (cleanup_after_register_access(target, mstatus, regno) != ERROR_OK)
2055 return ERROR_FAIL;
2056 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
2057 return ERROR_FAIL;
2058
2059 return result;
2060 }
2061
2062 static uint32_t sb_sbaccess(unsigned int size_bytes)
2063 {
2064 switch (size_bytes) {
2065 case 1:
2066 return set_field(0, DM_SBCS_SBACCESS, 0);
2067 case 2:
2068 return set_field(0, DM_SBCS_SBACCESS, 1);
2069 case 4:
2070 return set_field(0, DM_SBCS_SBACCESS, 2);
2071 case 8:
2072 return set_field(0, DM_SBCS_SBACCESS, 3);
2073 case 16:
2074 return set_field(0, DM_SBCS_SBACCESS, 4);
2075 }
2076 assert(0);
2077 return 0;
2078 }
2079
2080 static int sb_write_address(struct target *target, target_addr_t address,
2081 bool ensure_success)
2082 {
2083 RISCV013_INFO(info);
2084 unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
2085 /* There currently is no support for >64-bit addresses in OpenOCD. */
2086 if (sbasize > 96)
2087 dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS3, 0, false, false);
2088 if (sbasize > 64)
2089 dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS2, 0, false, false);
2090 if (sbasize > 32)
2091 dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS1, address >> 32, false, false);
2092 return dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS0, address,
2093 false, ensure_success);
2094 }
2095
2096 static int batch_run(const struct target *target, struct riscv_batch *batch)
2097 {
2098 RISCV013_INFO(info);
2099 RISCV_INFO(r);
2100 if (r->reset_delays_wait >= 0) {
2101 r->reset_delays_wait -= batch->used_scans;
2102 if (r->reset_delays_wait <= 0) {
2103 batch->idle_count = 0;
2104 info->dmi_busy_delay = 0;
2105 info->ac_busy_delay = 0;
2106 }
2107 }
2108 return riscv_batch_run(batch);
2109 }
2110
2111 static int sba_supports_access(struct target *target, unsigned int size_bytes)
2112 {
2113 RISCV013_INFO(info);
2114 switch (size_bytes) {
2115 case 1:
2116 return get_field(info->sbcs, DM_SBCS_SBACCESS8);
2117 case 2:
2118 return get_field(info->sbcs, DM_SBCS_SBACCESS16);
2119 case 4:
2120 return get_field(info->sbcs, DM_SBCS_SBACCESS32);
2121 case 8:
2122 return get_field(info->sbcs, DM_SBCS_SBACCESS64);
2123 case 16:
2124 return get_field(info->sbcs, DM_SBCS_SBACCESS128);
2125 default:
2126 return 0;
2127 }
2128 }
2129
2130 static int sample_memory_bus_v1(struct target *target,
2131 struct riscv_sample_buf *buf,
2132 const riscv_sample_config_t *config,
2133 int64_t until_ms)
2134 {
2135 RISCV013_INFO(info);
2136 unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
2137 if (sbasize > 64) {
2138 LOG_ERROR("Memory sampling is only implemented for sbasize <= 64.");
2139 return ERROR_NOT_IMPLEMENTED;
2140 }
2141
2142 if (get_field(info->sbcs, DM_SBCS_SBVERSION) != 1) {
2143 LOG_ERROR("Memory sampling is only implemented for SBA version 1.");
2144 return ERROR_NOT_IMPLEMENTED;
2145 }
2146
2147 uint32_t sbcs = 0;
2148 uint32_t sbcs_valid = false;
2149
2150 uint32_t sbaddress0 = 0;
2151 bool sbaddress0_valid = false;
2152 uint32_t sbaddress1 = 0;
2153 bool sbaddress1_valid = false;
2154
2155 /* How often to read each value in a batch. */
2156 const unsigned int repeat = 5;
2157
2158 unsigned int enabled_count = 0;
2159 for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
2160 if (config->bucket[i].enabled)
2161 enabled_count++;
2162 }
2163
2164 while (timeval_ms() < until_ms) {
2165 /*
2166 * batch_run() adds to the batch, so we can't simply reuse the same
2167 * batch over and over. So we create a new one every time through the
2168 * loop.
2169 */
2170 struct riscv_batch *batch = riscv_batch_alloc(
2171 target, 1 + enabled_count * 5 * repeat,
2172 info->dmi_busy_delay + info->bus_master_read_delay);
2173 if (!batch)
2174 return ERROR_FAIL;
2175
2176 unsigned int result_bytes = 0;
2177 for (unsigned int n = 0; n < repeat; n++) {
2178 for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
2179 if (config->bucket[i].enabled) {
2180 if (!sba_supports_access(target, config->bucket[i].size_bytes)) {
2181 LOG_ERROR("Hardware does not support SBA access for %d-byte memory sampling.",
2182 config->bucket[i].size_bytes);
2183 return ERROR_NOT_IMPLEMENTED;
2184 }
2185
2186 uint32_t sbcs_write = DM_SBCS_SBREADONADDR;
2187 if (enabled_count == 1)
2188 sbcs_write |= DM_SBCS_SBREADONDATA;
2189 sbcs_write |= sb_sbaccess(config->bucket[i].size_bytes);
2190 if (!sbcs_valid || sbcs_write != sbcs) {
2191 riscv_batch_add_dmi_write(batch, DM_SBCS, sbcs_write);
2192 sbcs = sbcs_write;
2193 sbcs_valid = true;
2194 }
2195
2196 if (sbasize > 32 &&
2197 (!sbaddress1_valid ||
2198 sbaddress1 != config->bucket[i].address >> 32)) {
2199 sbaddress1 = config->bucket[i].address >> 32;
2200 riscv_batch_add_dmi_write(batch, DM_SBADDRESS1, sbaddress1);
2201 sbaddress1_valid = true;
2202 }
2203 if (!sbaddress0_valid ||
2204 sbaddress0 != (config->bucket[i].address & 0xffffffff)) {
2205 sbaddress0 = config->bucket[i].address;
2206 riscv_batch_add_dmi_write(batch, DM_SBADDRESS0, sbaddress0);
2207 sbaddress0_valid = true;
2208 }
2209 if (config->bucket[i].size_bytes > 4)
2210 riscv_batch_add_dmi_read(batch, DM_SBDATA1);
2211 riscv_batch_add_dmi_read(batch, DM_SBDATA0);
2212 result_bytes += 1 + config->bucket[i].size_bytes;
2213 }
2214 }
2215 }
2216
2217 if (buf->used + result_bytes >= buf->size) {
2218 riscv_batch_free(batch);
2219 break;
2220 }
2221
2222 size_t sbcs_key = riscv_batch_add_dmi_read(batch, DM_SBCS);
2223
2224 int result = batch_run(target, batch);
2225 if (result != ERROR_OK)
2226 return result;
2227
2228 uint32_t sbcs_read = riscv_batch_get_dmi_read_data(batch, sbcs_key);
2229 if (get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) {
2230 /* Discard this batch (too much hassle to try to recover partial
2231 * data) and try again with a larger delay. */
2232 info->bus_master_read_delay += info->bus_master_read_delay / 10 + 1;
2233 dmi_write(target, DM_SBCS, sbcs_read | DM_SBCS_SBBUSYERROR | DM_SBCS_SBERROR);
2234 riscv_batch_free(batch);
2235 continue;
2236 }
2237 if (get_field(sbcs_read, DM_SBCS_SBERROR)) {
2238 /* The memory we're sampling was unreadable, somehow. Give up. */
2239 dmi_write(target, DM_SBCS, DM_SBCS_SBBUSYERROR | DM_SBCS_SBERROR);
2240 riscv_batch_free(batch);
2241 return ERROR_FAIL;
2242 }
2243
2244 unsigned int read = 0;
2245 for (unsigned int n = 0; n < repeat; n++) {
2246 for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
2247 if (config->bucket[i].enabled) {
2248 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2249 uint64_t value = 0;
2250 if (config->bucket[i].size_bytes > 4)
2251 value = ((uint64_t)riscv_batch_get_dmi_read_data(batch, read++)) << 32;
2252 value |= riscv_batch_get_dmi_read_data(batch, read++);
2253
2254 buf->buf[buf->used] = i;
2255 buf_set_u64(buf->buf + buf->used + 1, 0, config->bucket[i].size_bytes * 8, value);
2256 buf->used += 1 + config->bucket[i].size_bytes;
2257 }
2258 }
2259 }
2260
2261 riscv_batch_free(batch);
2262 }
2263
2264 return ERROR_OK;
2265 }
2266
2267 static int sample_memory(struct target *target,
2268 struct riscv_sample_buf *buf,
2269 riscv_sample_config_t *config,
2270 int64_t until_ms)
2271 {
2272 if (!config->enabled)
2273 return ERROR_OK;
2274
2275 return sample_memory_bus_v1(target, buf, config, until_ms);
2276 }
2277
2278 static int init_target(struct command_context *cmd_ctx,
2279 struct target *target)
2280 {
2281 LOG_DEBUG("init");
2282 RISCV_INFO(generic_info);
2283
2284 generic_info->get_register = &riscv013_get_register;
2285 generic_info->set_register = &riscv013_set_register;
2286 generic_info->get_register_buf = &riscv013_get_register_buf;
2287 generic_info->set_register_buf = &riscv013_set_register_buf;
2288 generic_info->select_current_hart = &riscv013_select_current_hart;
2289 generic_info->is_halted = &riscv013_is_halted;
2290 generic_info->resume_go = &riscv013_resume_go;
2291 generic_info->step_current_hart = &riscv013_step_current_hart;
2292 generic_info->on_halt = &riscv013_on_halt;
2293 generic_info->resume_prep = &riscv013_resume_prep;
2294 generic_info->halt_prep = &riscv013_halt_prep;
2295 generic_info->halt_go = &riscv013_halt_go;
2296 generic_info->on_step = &riscv013_on_step;
2297 generic_info->halt_reason = &riscv013_halt_reason;
2298 generic_info->read_debug_buffer = &riscv013_read_debug_buffer;
2299 generic_info->write_debug_buffer = &riscv013_write_debug_buffer;
2300 generic_info->execute_debug_buffer = &riscv013_execute_debug_buffer;
2301 generic_info->fill_dmi_write_u64 = &riscv013_fill_dmi_write_u64;
2302 generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64;
2303 generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64;
2304 generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits;
2305 generic_info->authdata_read = &riscv013_authdata_read;
2306 generic_info->authdata_write = &riscv013_authdata_write;
2307 generic_info->dmi_read = &dmi_read;
2308 generic_info->dmi_write = &dmi_write;
2309 generic_info->read_memory = read_memory;
2310 generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg;
2311 generic_info->hart_count = &riscv013_hart_count;
2312 generic_info->data_bits = &riscv013_data_bits;
2313 generic_info->print_info = &riscv013_print_info;
2314 generic_info->version_specific = calloc(1, sizeof(riscv013_info_t));
2315 if (!generic_info->version_specific)
2316 return ERROR_FAIL;
2317 generic_info->sample_memory = sample_memory;
2318 riscv013_info_t *info = get_info(target);
2319
2320 info->progbufsize = -1;
2321
2322 info->dmi_busy_delay = 0;
2323 info->bus_master_read_delay = 0;
2324 info->bus_master_write_delay = 0;
2325 info->ac_busy_delay = 0;
2326
2327 /* Assume all these abstract commands are supported until we learn
2328 * otherwise.
2329 * TODO: The spec allows eg. one CSR to be able to be accessed abstractly
2330 * while another one isn't. We don't track that this closely here, but in
2331 * the future we probably should. */
2332 info->abstract_read_csr_supported = true;
2333 info->abstract_write_csr_supported = true;
2334 info->abstract_read_fpr_supported = true;
2335 info->abstract_write_fpr_supported = true;
2336
2337 info->has_aampostincrement = YNM_MAYBE;
2338
2339 return ERROR_OK;
2340 }
2341
2342 static int assert_reset(struct target *target)
2343 {
2344 RISCV_INFO(r);
2345
2346 select_dmi(target);
2347
2348 uint32_t control_base = set_field(0, DM_DMCONTROL_DMACTIVE, 1);
2349
2350 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
2351 /* Run the user-supplied script if there is one. */
2352 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
2353 } else if (target->rtos) {
2354 /* There's only one target, and OpenOCD thinks each hart is a thread.
2355 * We must reset them all. */
2356
2357 /* TODO: Try to use hasel in dmcontrol */
2358
2359 /* Set haltreq for each hart. */
2360 uint32_t control = control_base;
2361
2362 control = set_hartsel(control_base, target->coreid);
2363 control = set_field(control, DM_DMCONTROL_HALTREQ,
2364 target->reset_halt ? 1 : 0);
2365 dmi_write(target, DM_DMCONTROL, control);
2366
2367 /* Assert ndmreset */
2368 control = set_field(control, DM_DMCONTROL_NDMRESET, 1);
2369 dmi_write(target, DM_DMCONTROL, control);
2370
2371 } else {
2372 /* Reset just this hart. */
2373 uint32_t control = set_hartsel(control_base, r->current_hartid);
2374 control = set_field(control, DM_DMCONTROL_HALTREQ,
2375 target->reset_halt ? 1 : 0);
2376 control = set_field(control, DM_DMCONTROL_NDMRESET, 1);
2377 dmi_write(target, DM_DMCONTROL, control);
2378 }
2379
2380 target->state = TARGET_RESET;
2381
2382 dm013_info_t *dm = get_dm(target);
2383 if (!dm)
2384 return ERROR_FAIL;
2385
2386 /* The DM might have gotten reset if OpenOCD called us in some reset that
2387 * involves SRST being toggled. So clear our cache which may be out of
2388 * date. */
2389 memset(dm->progbuf_cache, 0, sizeof(dm->progbuf_cache));
2390
2391 return ERROR_OK;
2392 }
2393
2394 static int deassert_reset(struct target *target)
2395 {
2396 RISCV_INFO(r);
2397 RISCV013_INFO(info);
2398 select_dmi(target);
2399
2400 /* Clear the reset, but make sure haltreq is still set */
2401 uint32_t control = 0;
2402 control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
2403 control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
2404 dmi_write(target, DM_DMCONTROL,
2405 set_hartsel(control, r->current_hartid));
2406
2407 uint32_t dmstatus;
2408 int dmi_busy_delay = info->dmi_busy_delay;
2409 time_t start = time(NULL);
2410
2411 for (int i = 0; i < riscv_count_harts(target); ++i) {
2412 int index = i;
2413 if (target->rtos) {
2414 if (index != target->coreid)
2415 continue;
2416 dmi_write(target, DM_DMCONTROL,
2417 set_hartsel(control, index));
2418 } else {
2419 index = r->current_hartid;
2420 }
2421
2422 LOG_DEBUG("Waiting for hart %d to come out of reset.", index);
2423 while (1) {
2424 int result = dmstatus_read_timeout(target, &dmstatus, true,
2425 riscv_reset_timeout_sec);
2426 if (result == ERROR_TIMEOUT_REACHED)
2427 LOG_ERROR("Hart %d didn't complete a DMI read coming out of "
2428 "reset in %ds; Increase the timeout with riscv "
2429 "set_reset_timeout_sec.",
2430 index, riscv_reset_timeout_sec);
2431 if (result != ERROR_OK)
2432 return result;
2433 /* Certain debug modules, like the one in GD32VF103
2434 * MCUs, violate the specification's requirement that
2435 * each hart is in "exactly one of four states" and,
2436 * during reset, report harts as both unavailable and
2437 * halted/running. To work around this, we check for
2438 * the absence of the unavailable state rather than
2439 * the presence of any other state. */
2440 if (!get_field(dmstatus, DM_DMSTATUS_ALLUNAVAIL))
2441 break;
2442 if (time(NULL) - start > riscv_reset_timeout_sec) {
2443 LOG_ERROR("Hart %d didn't leave reset in %ds; "
2444 "dmstatus=0x%x; "
2445 "Increase the timeout with riscv set_reset_timeout_sec.",
2446 index, riscv_reset_timeout_sec, dmstatus);
2447 return ERROR_FAIL;
2448 }
2449 }
2450 target->state = TARGET_HALTED;
2451
2452 if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {
2453 /* Ack reset. */
2454 dmi_write(target, DM_DMCONTROL,
2455 set_hartsel(control, index) |
2456 DM_DMCONTROL_ACKHAVERESET);
2457 }
2458
2459 if (!target->rtos)
2460 break;
2461 }
2462 info->dmi_busy_delay = dmi_busy_delay;
2463 return ERROR_OK;
2464 }
2465
2466 static int execute_fence(struct target *target)
2467 {
2468 /* FIXME: For non-coherent systems we need to flush the caches right
2469 * here, but there's no ISA-defined way of doing that. */
2470 {
2471 struct riscv_program program;
2472 riscv_program_init(&program, target);
2473 riscv_program_fence_i(&program);
2474 riscv_program_fence(&program);
2475 int result = riscv_program_exec(&program, target);
2476 if (result != ERROR_OK)
2477 LOG_DEBUG("Unable to execute pre-fence");
2478 }
2479
2480 return ERROR_OK;
2481 }
2482
2483 static void log_memory_access(target_addr_t address, uint64_t value,
2484 unsigned size_bytes, bool read)
2485 {
2486 if (debug_level < LOG_LVL_DEBUG)
2487 return;
2488
2489 char fmt[80];
2490 sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
2491 address, read ? "read" : "write", size_bytes * 2);
2492 switch (size_bytes) {
2493 case 1:
2494 value &= 0xff;
2495 break;
2496 case 2:
2497 value &= 0xffff;
2498 break;
2499 case 4:
2500 value &= 0xffffffffUL;
2501 break;
2502 case 8:
2503 break;
2504 default:
2505 assert(false);
2506 }
2507 LOG_DEBUG(fmt, value);
2508 }
2509
2510 /* Read the relevant sbdata regs depending on size, and put the results into
2511 * buffer. */
2512 static int read_memory_bus_word(struct target *target, target_addr_t address,
2513 uint32_t size, uint8_t *buffer)
2514 {
2515 uint32_t value;
2516 int result;
2517 static int sbdata[4] = { DM_SBDATA0, DM_SBDATA1, DM_SBDATA2, DM_SBDATA3 };
2518 assert(size <= 16);
2519 for (int i = (size - 1) / 4; i >= 0; i--) {
2520 result = dmi_op(target, &value, NULL, DMI_OP_READ, sbdata[i], 0, false, true);
2521 if (result != ERROR_OK)
2522 return result;
2523 buf_set_u32(buffer + i * 4, 0, 8 * MIN(size, 4), value);
2524 log_memory_access(address + i * 4, value, MIN(size, 4), true);
2525 }
2526 return ERROR_OK;
2527 }
2528
2529 static target_addr_t sb_read_address(struct target *target)
2530 {
2531 RISCV013_INFO(info);
2532 unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
2533 target_addr_t address = 0;
2534 uint32_t v;
2535 if (sbasize > 32) {
2536 dmi_read(target, &v, DM_SBADDRESS1);
2537 address |= v;
2538 address <<= 32;
2539 }
2540 dmi_read(target, &v, DM_SBADDRESS0);
2541 address |= v;
2542 return address;
2543 }
2544
2545 static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs)
2546 {
2547 time_t start = time(NULL);
2548 while (1) {
2549 if (dmi_read(target, sbcs, DM_SBCS) != ERROR_OK)
2550 return ERROR_FAIL;
2551 if (!get_field(*sbcs, DM_SBCS_SBBUSY))
2552 return ERROR_OK;
2553 if (time(NULL) - start > riscv_command_timeout_sec) {
2554 LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
2555 "Increase the timeout with riscv set_command_timeout_sec.",
2556 riscv_command_timeout_sec, *sbcs);
2557 return ERROR_FAIL;
2558 }
2559 }
2560 }
2561
2562 static int modify_privilege(struct target *target, uint64_t *mstatus, uint64_t *mstatus_old)
2563 {
2564 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5)) {
2565 /* Read DCSR */
2566 uint64_t dcsr;
2567 if (register_read(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
2568 return ERROR_FAIL;
2569
2570 /* Read and save MSTATUS */
2571 if (register_read(target, mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
2572 return ERROR_FAIL;
2573 *mstatus_old = *mstatus;
2574
2575 /* If we come from m-mode with mprv set, we want to keep mpp */
2576 if (get_field(dcsr, DCSR_PRV) < 3) {
2577 /* MPP = PRIV */
2578 *mstatus = set_field(*mstatus, MSTATUS_MPP, get_field(dcsr, DCSR_PRV));
2579
2580 /* MPRV = 1 */
2581 *mstatus = set_field(*mstatus, MSTATUS_MPRV, 1);
2582
2583 /* Write MSTATUS */
2584 if (*mstatus != *mstatus_old)
2585 if (register_write_direct(target, GDB_REGNO_MSTATUS, *mstatus) != ERROR_OK)
2586 return ERROR_FAIL;
2587 }
2588 }
2589
2590 return ERROR_OK;
2591 }
2592
2593 static int read_memory_bus_v0(struct target *target, target_addr_t address,
2594 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
2595 {
2596 if (size != increment) {
2597 LOG_ERROR("sba v0 reads only support size==increment");
2598 return ERROR_NOT_IMPLEMENTED;
2599 }
2600
2601 LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
2602 TARGET_PRIxADDR, size, count, address);
2603 uint8_t *t_buffer = buffer;
2604 riscv_addr_t cur_addr = address;
2605 riscv_addr_t fin_addr = address + (count * size);
2606 uint32_t access = 0;
2607
2608 const int DM_SBCS_SBSINGLEREAD_OFFSET = 20;
2609 const uint32_t DM_SBCS_SBSINGLEREAD = (0x1U << DM_SBCS_SBSINGLEREAD_OFFSET);
2610
2611 const int DM_SBCS_SBAUTOREAD_OFFSET = 15;
2612 const uint32_t DM_SBCS_SBAUTOREAD = (0x1U << DM_SBCS_SBAUTOREAD_OFFSET);
2613
2614 /* ww favorise one off reading if there is an issue */
2615 if (count == 1) {
2616 for (uint32_t i = 0; i < count; i++) {
2617 if (dmi_read(target, &access, DM_SBCS) != ERROR_OK)
2618 return ERROR_FAIL;
2619 dmi_write(target, DM_SBADDRESS0, cur_addr);
2620 /* size/2 matching the bit access of the spec 0.13 */
2621 access = set_field(access, DM_SBCS_SBACCESS, size/2);
2622 access = set_field(access, DM_SBCS_SBSINGLEREAD, 1);
2623 LOG_DEBUG("\r\nread_memory: sab: access: 0x%08x", access);
2624 dmi_write(target, DM_SBCS, access);
2625 /* 3) read */
2626 uint32_t value;
2627 if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK)
2628 return ERROR_FAIL;
2629 LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value);
2630 buf_set_u32(t_buffer, 0, 8 * size, value);
2631 t_buffer += size;
2632 cur_addr += size;
2633 }
2634 return ERROR_OK;
2635 }
2636
2637 /* has to be the same size if we want to read a block */
2638 LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr);
2639 if (dmi_read(target, &access, DM_SBCS) != ERROR_OK)
2640 return ERROR_FAIL;
2641 /* set current address */
2642 dmi_write(target, DM_SBADDRESS0, cur_addr);
2643 /* 2) write sbaccess=2, sbsingleread,sbautoread,sbautoincrement
2644 * size/2 matching the bit access of the spec 0.13 */
2645 access = set_field(access, DM_SBCS_SBACCESS, size/2);
2646 access = set_field(access, DM_SBCS_SBAUTOREAD, 1);
2647 access = set_field(access, DM_SBCS_SBSINGLEREAD, 1);
2648 access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1);
2649 LOG_DEBUG("\r\naccess: 0x%08x", access);
2650 dmi_write(target, DM_SBCS, access);
2651
2652 while (cur_addr < fin_addr) {
2653 LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
2654 PRIx64, size, count, cur_addr);
2655 /* read */
2656 uint32_t value;
2657 if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK)
2658 return ERROR_FAIL;
2659 buf_set_u32(t_buffer, 0, 8 * size, value);
2660 cur_addr += size;
2661 t_buffer += size;
2662
2663 /* if we are reaching last address, we must clear autoread */
2664 if (cur_addr == fin_addr && count != 1) {
2665 dmi_write(target, DM_SBCS, 0);
2666 if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK)
2667 return ERROR_FAIL;
2668 buf_set_u32(t_buffer, 0, 8 * size, value);
2669 }
2670 }
2671
2672 uint32_t sbcs;
2673 if (dmi_read(target, &sbcs, DM_SBCS) != ERROR_OK)
2674 return ERROR_FAIL;
2675
2676 return ERROR_OK;
2677 }
2678
2679 /**
2680 * Read the requested memory using the system bus interface.
2681 */
2682 static int read_memory_bus_v1(struct target *target, target_addr_t address,
2683 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
2684 {
2685 if (increment != size && increment != 0) {
2686 LOG_ERROR("sba v1 reads only support increment of size or 0");
2687 return ERROR_NOT_IMPLEMENTED;
2688 }
2689
2690 RISCV013_INFO(info);
2691 target_addr_t next_address = address;
2692 target_addr_t end_address = address + count * size;
2693
2694 while (next_address < end_address) {
2695 uint32_t sbcs_write = set_field(0, DM_SBCS_SBREADONADDR, 1);
2696 sbcs_write |= sb_sbaccess(size);
2697 if (increment == size)
2698 sbcs_write = set_field(sbcs_write, DM_SBCS_SBAUTOINCREMENT, 1);
2699 if (count > 1)
2700 sbcs_write = set_field(sbcs_write, DM_SBCS_SBREADONDATA, count > 1);
2701 if (dmi_write(target, DM_SBCS, sbcs_write) != ERROR_OK)
2702 return ERROR_FAIL;
2703
2704 /* This address write will trigger the first read. */
2705 if (sb_write_address(target, next_address, true) != ERROR_OK)
2706 return ERROR_FAIL;
2707
2708 if (info->bus_master_read_delay) {
2709 jtag_add_runtest(info->bus_master_read_delay, TAP_IDLE);
2710 if (jtag_execute_queue() != ERROR_OK) {
2711 LOG_ERROR("Failed to scan idle sequence");
2712 return ERROR_FAIL;
2713 }
2714 }
2715
2716 /* First value has been read, and is waiting for us to issue a DMI read
2717 * to get it. */
2718
2719 static int sbdata[4] = {DM_SBDATA0, DM_SBDATA1, DM_SBDATA2, DM_SBDATA3};
2720 assert(size <= 16);
2721 target_addr_t next_read = address - 1;
2722 for (uint32_t i = (next_address - address) / size; i < count - 1; i++) {
2723 for (int j = (size - 1) / 4; j >= 0; j--) {
2724 uint32_t value;
2725 unsigned attempt = 0;
2726 while (1) {
2727 if (attempt++ > 100) {
2728 LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
2729 next_read);
2730 return ERROR_FAIL;
2731 }
2732 keep_alive();
2733 dmi_status_t status = dmi_scan(target, NULL, &value,
2734 DMI_OP_READ, sbdata[j], 0, false);
2735 if (status == DMI_STATUS_BUSY)
2736 increase_dmi_busy_delay(target);
2737 else if (status == DMI_STATUS_SUCCESS)
2738 break;
2739 else
2740 return ERROR_FAIL;
2741 }
2742 if (next_read != address - 1) {
2743 buf_set_u32(buffer + next_read - address, 0, 8 * MIN(size, 4), value);
2744 log_memory_access(next_read, value, MIN(size, 4), true);
2745 }
2746 next_read = address + i * size + j * 4;
2747 }
2748 }
2749
2750 uint32_t sbcs_read = 0;
2751 if (count > 1) {
2752 uint32_t value;
2753 unsigned attempt = 0;
2754 while (1) {
2755 if (attempt++ > 100) {
2756 LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
2757 next_read);
2758 return ERROR_FAIL;
2759 }
2760 dmi_status_t status = dmi_scan(target, NULL, &value, DMI_OP_NOP, 0, 0, false);
2761 if (status == DMI_STATUS_BUSY)
2762 increase_dmi_busy_delay(target);
2763 else if (status == DMI_STATUS_SUCCESS)
2764 break;
2765 else
2766 return ERROR_FAIL;
2767 }
2768 buf_set_u32(buffer + next_read - address, 0, 8 * MIN(size, 4), value);
2769 log_memory_access(next_read, value, MIN(size, 4), true);
2770
2771 /* "Writes to sbcs while sbbusy is high result in undefined behavior.
2772 * A debugger must not write to sbcs until it reads sbbusy as 0." */
2773 if (read_sbcs_nonbusy(target, &sbcs_read) != ERROR_OK)
2774 return ERROR_FAIL;
2775
2776 sbcs_write = set_field(sbcs_write, DM_SBCS_SBREADONDATA, 0);
2777 if (dmi_write(target, DM_SBCS, sbcs_write) != ERROR_OK)
2778 return ERROR_FAIL;
2779 }
2780
2781 /* Read the last word, after we disabled sbreadondata if necessary. */
2782 if (!get_field(sbcs_read, DM_SBCS_SBERROR) &&
2783 !get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) {
2784 if (read_memory_bus_word(target, address + (count - 1) * size, size,
2785 buffer + (count - 1) * size) != ERROR_OK)
2786 return ERROR_FAIL;
2787
2788 if (read_sbcs_nonbusy(target, &sbcs_read) != ERROR_OK)
2789 return ERROR_FAIL;
2790 }
2791
2792 if (get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) {
2793 /* We read while the target was busy. Slow down and try again. */
2794 if (dmi_write(target, DM_SBCS, sbcs_read | DM_SBCS_SBBUSYERROR) != ERROR_OK)
2795 return ERROR_FAIL;
2796 next_address = sb_read_address(target);
2797 info->bus_master_read_delay += info->bus_master_read_delay / 10 + 1;
2798 continue;
2799 }
2800
2801 unsigned error = get_field(sbcs_read, DM_SBCS_SBERROR);
2802 if (error == 0) {
2803 next_address = end_address;
2804 } else {
2805 /* Some error indicating the bus access failed, but not because of
2806 * something we did wrong. */
2807 if (dmi_write(target, DM_SBCS, DM_SBCS_SBERROR) != ERROR_OK)
2808 return ERROR_FAIL;
2809 return ERROR_FAIL;
2810 }
2811 }
2812
2813 return ERROR_OK;
2814 }
2815
2816 static void log_mem_access_result(struct target *target, bool success, int method, bool read)
2817 {
2818 RISCV_INFO(r);
2819 bool warn = false;
2820 char msg[60];
2821
2822 /* Compose the message */
2823 snprintf(msg, 60, "%s to %s memory via %s.",
2824 success ? "Succeeded" : "Failed",
2825 read ? "read" : "write",
2826 (method == RISCV_MEM_ACCESS_PROGBUF) ? "program buffer" :
2827 (method == RISCV_MEM_ACCESS_SYSBUS) ? "system bus" : "abstract access");
2828
2829 /* Determine the log message severity. Show warnings only once. */
2830 if (!success) {
2831 if (method == RISCV_MEM_ACCESS_PROGBUF) {
2832 warn = r->mem_access_progbuf_warn;
2833 r->mem_access_progbuf_warn = false;
2834 }
2835 if (method == RISCV_MEM_ACCESS_SYSBUS) {
2836 warn = r->mem_access_sysbus_warn;
2837 r->mem_access_sysbus_warn = false;
2838 }
2839 if (method == RISCV_MEM_ACCESS_ABSTRACT) {
2840 warn = r->mem_access_abstract_warn;
2841 r->mem_access_abstract_warn = false;
2842 }
2843 }
2844
2845 if (warn)
2846 LOG_WARNING("%s", msg);
2847 else
2848 LOG_DEBUG("%s", msg);
2849 }
2850
2851 static bool mem_should_skip_progbuf(struct target *target, target_addr_t address,
2852 uint32_t size, bool read, char **skip_reason)
2853 {
2854 assert(skip_reason);
2855
2856 if (!has_sufficient_progbuf(target, 3)) {
2857 LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.",
2858 read ? "read" : "write");
2859 *skip_reason = "skipped (insufficient progbuf)";
2860 return true;
2861 }
2862 if (target->state != TARGET_HALTED) {
2863 LOG_DEBUG("Skipping mem %s via progbuf - target not halted.",
2864 read ? "read" : "write");
2865 *skip_reason = "skipped (target not halted)";
2866 return true;
2867 }
2868 if (riscv_xlen(target) < size * 8) {
2869 LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
2870 read ? "read" : "write", riscv_xlen(target), size * 8);
2871 *skip_reason = "skipped (XLEN too short)";
2872 return true;
2873 }
2874 if (size > 8) {
2875 LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.",
2876 read ? "read" : "write");
2877 *skip_reason = "skipped (unsupported size)";
2878 return true;
2879 }
2880 if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
2881 LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
2882 read ? "read" : "write", riscv_xlen(target));
2883 *skip_reason = "skipped (too large address)";
2884 return true;
2885 }
2886
2887 return false;
2888 }
2889
2890 static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
2891 uint32_t size, uint32_t increment, bool read, char **skip_reason)
2892 {
2893 assert(skip_reason);
2894
2895 RISCV013_INFO(info);
2896 if (!sba_supports_access(target, size)) {
2897 LOG_DEBUG("Skipping mem %s via system bus - unsupported size.",
2898 read ? "read" : "write");
2899 *skip_reason = "skipped (unsupported size)";
2900 return true;
2901 }
2902 unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
2903 if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) {
2904 LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
2905 read ? "read" : "write", sbasize);
2906 *skip_reason = "skipped (too large address)";
2907 return true;
2908 }
2909 if (read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
2910 LOG_DEBUG("Skipping mem read via system bus - "
2911 "sba reads only support size==increment or also size==0 for sba v1.");
2912 *skip_reason = "skipped (unsupported increment)";
2913 return true;
2914 }
2915
2916 return false;
2917 }
2918
2919 static bool mem_should_skip_abstract(struct target *target, target_addr_t address,
2920 uint32_t size, uint32_t increment, bool read, char **skip_reason)
2921 {
2922 assert(skip_reason);
2923
2924 if (size > 8) {
2925 /* TODO: Add 128b support if it's ever used. Involves modifying
2926 read/write_abstract_arg() to work on two 64b values. */
2927 LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits",
2928 read ? "read" : "write", size * 8);
2929 *skip_reason = "skipped (unsupported size)";
2930 return true;
2931 }
2932 if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
2933 LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
2934 read ? "read" : "write", riscv_xlen(target));
2935 *skip_reason = "skipped (too large address)";
2936 return true;
2937 }
2938 if (read && size != increment) {
2939 LOG_ERROR("Skipping mem read via abstract access - "
2940 "abstract command reads only support size==increment.");
2941 *skip_reason = "skipped (unsupported increment)";
2942 return true;
2943 }
2944
2945 return false;
2946 }
2947
2948 /*
2949 * Performs a memory read using memory access abstract commands. The read sizes
2950 * supported are 1, 2, and 4 bytes despite the spec's support of 8 and 16 byte
2951 * aamsize fields in the memory access abstract command.
2952 */
2953 static int read_memory_abstract(struct target *target, target_addr_t address,
2954 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
2955 {
2956 RISCV013_INFO(info);
2957
2958 int result = ERROR_OK;
2959 bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
2960
2961 LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
2962 size, address);
2963
2964 memset(buffer, 0, count * size);
2965
2966 /* Convert the size (bytes) to width (bits) */
2967 unsigned width = size << 3;
2968
2969 /* Create the command (physical address, postincrement, read) */
2970 uint32_t command = access_memory_command(target, false, width, use_aampostincrement, false);
2971
2972 /* Execute the reads */
2973 uint8_t *p = buffer;
2974 bool updateaddr = true;
2975 unsigned int width32 = (width < 32) ? 32 : width;
2976 for (uint32_t c = 0; c < count; c++) {
2977 /* Update the address if it is the first time or aampostincrement is not supported by the target. */
2978 if (updateaddr) {
2979 /* Set arg1 to the address: address + c * size */
2980 result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
2981 if (result != ERROR_OK) {
2982 LOG_ERROR("Failed to write arg1 during read_memory_abstract().");
2983 return result;
2984 }
2985 }
2986
2987 /* Execute the command */
2988 result = execute_abstract_command(target, command);
2989
2990 if (info->has_aampostincrement == YNM_MAYBE) {
2991 if (result == ERROR_OK) {
2992 /* Safety: double-check that the address was really auto-incremented */
2993 riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
2994 if (new_address == address + size) {
2995 LOG_DEBUG("aampostincrement is supported on this target.");
2996 info->has_aampostincrement = YNM_YES;
2997 } else {
2998 LOG_WARNING("Buggy aampostincrement! Address not incremented correctly.");
2999 info->has_aampostincrement = YNM_NO;
3000 }
3001 } else {
3002 /* Try the same access but with postincrement disabled. */
3003 command = access_memory_command(target, false, width, false, false);
3004 result = execute_abstract_command(target, command);
3005 if (result == ERROR_OK) {
3006 LOG_DEBUG("aampostincrement is not supported on this target.");
3007 info->has_aampostincrement = YNM_NO;
3008 }
3009 }
3010 }
3011
3012 if (result != ERROR_OK)
3013 return result;
3014
3015 /* Copy arg0 to buffer (rounded width up to nearest 32) */
3016 riscv_reg_t value = read_abstract_arg(target, 0, width32);
3017 buf_set_u64(p, 0, 8 * size, value);
3018
3019 if (info->has_aampostincrement == YNM_YES)
3020 updateaddr = false;
3021 p += size;
3022 }
3023
3024 return result;
3025 }
3026
3027 /*
3028 * Performs a memory write using memory access abstract commands. The write
3029 * sizes supported are 1, 2, and 4 bytes despite the spec's support of 8 and 16
3030 * byte aamsize fields in the memory access abstract command.
3031 */
3032 static int write_memory_abstract(struct target *target, target_addr_t address,
3033 uint32_t size, uint32_t count, const uint8_t *buffer)
3034 {
3035 RISCV013_INFO(info);
3036 int result = ERROR_OK;
3037 bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
3038
3039 LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
3040 size, address);
3041
3042 /* Convert the size (bytes) to width (bits) */
3043 unsigned width = size << 3;
3044
3045 /* Create the command (physical address, postincrement, write) */
3046 uint32_t command = access_memory_command(target, false, width, use_aampostincrement, true);
3047
3048 /* Execute the writes */
3049 const uint8_t *p = buffer;
3050 bool updateaddr = true;
3051 for (uint32_t c = 0; c < count; c++) {
3052 /* Move data to arg0 */
3053 riscv_reg_t value = buf_get_u64(p, 0, 8 * size);
3054 result = write_abstract_arg(target, 0, value, riscv_xlen(target));
3055 if (result != ERROR_OK) {
3056 LOG_ERROR("Failed to write arg0 during write_memory_abstract().");
3057 return result;
3058 }
3059
3060 /* Update the address if it is the first time or aampostincrement is not supported by the target. */
3061 if (updateaddr) {
3062 /* Set arg1 to the address: address + c * size */
3063 result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
3064 if (result != ERROR_OK) {
3065 LOG_ERROR("Failed to write arg1 during write_memory_abstract().");
3066 return result;
3067 }
3068 }
3069
3070 /* Execute the command */
3071 result = execute_abstract_command(target, command);
3072
3073 if (info->has_aampostincrement == YNM_MAYBE) {
3074 if (result == ERROR_OK) {
3075 /* Safety: double-check that the address was really auto-incremented */
3076 riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
3077 if (new_address == address + size) {
3078 LOG_DEBUG("aampostincrement is supported on this target.");
3079 info->has_aampostincrement = YNM_YES;
3080 } else {
3081 LOG_WARNING("Buggy aampostincrement! Address not incremented correctly.");
3082 info->has_aampostincrement = YNM_NO;
3083 }
3084 } else {
3085 /* Try the same access but with postincrement disabled. */
3086 command = access_memory_command(target, false, width, false, true);
3087 result = execute_abstract_command(target, command);
3088 if (result == ERROR_OK) {
3089 LOG_DEBUG("aampostincrement is not supported on this target.");
3090 info->has_aampostincrement = YNM_NO;
3091 }
3092 }
3093 }
3094
3095 if (result != ERROR_OK)
3096 return result;
3097
3098 if (info->has_aampostincrement == YNM_YES)
3099 updateaddr = false;
3100 p += size;
3101 }
3102
3103 return result;
3104 }
3105
3106 /**
3107 * Read the requested memory, taking care to execute every read exactly once,
3108 * even if cmderr=busy is encountered.
3109 */
3110 static int read_memory_progbuf_inner(struct target *target, target_addr_t address,
3111 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
3112 {
3113 RISCV013_INFO(info);
3114
3115 int result = ERROR_OK;
3116
3117 /* Write address to S0. */
3118 result = register_write_direct(target, GDB_REGNO_S0, address);
3119 if (result != ERROR_OK)
3120 return result;
3121
3122 if (increment == 0 &&
3123 register_write_direct(target, GDB_REGNO_S2, 0) != ERROR_OK)
3124 return ERROR_FAIL;
3125
3126 uint32_t command = access_register_command(target, GDB_REGNO_S1,
3127 riscv_xlen(target),
3128 AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_POSTEXEC);
3129 if (execute_abstract_command(target, command) != ERROR_OK)
3130 return ERROR_FAIL;
3131
3132 /* First read has just triggered. Result is in s1. */
3133 if (count == 1) {
3134 uint64_t value;
3135 if (register_read_direct(target, &value, GDB_REGNO_S1) != ERROR_OK)
3136 return ERROR_FAIL;
3137 buf_set_u64(buffer, 0, 8 * size, value);
3138 log_memory_access(address, value, size, true);
3139 return ERROR_OK;
3140 }
3141
3142 if (dmi_write(target, DM_ABSTRACTAUTO,
3143 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) != ERROR_OK)
3144 goto error;
3145 /* Read garbage from dmi_data0, which triggers another execution of the
3146 * program. Now dmi_data0 contains the first good result, and s1 the next
3147 * memory value. */
3148 if (dmi_read_exec(target, NULL, DM_DATA0) != ERROR_OK)
3149 goto error;
3150
3151 /* read_addr is the next address that the hart will read from, which is the
3152 * value in s0. */
3153 unsigned index = 2;
3154 while (index < count) {
3155 riscv_addr_t read_addr = address + index * increment;
3156 LOG_DEBUG("i=%d, count=%d, read_addr=0x%" PRIx64, index, count, read_addr);
3157 /* The pipeline looks like this:
3158 * memory -> s1 -> dm_data0 -> debugger
3159 * Right now:
3160 * s0 contains read_addr
3161 * s1 contains mem[read_addr-size]
3162 * dm_data0 contains[read_addr-size*2]
3163 */
3164
3165 struct riscv_batch *batch = riscv_batch_alloc(target, 32,
3166 info->dmi_busy_delay + info->ac_busy_delay);
3167 if (!batch)
3168 return ERROR_FAIL;
3169
3170 unsigned reads = 0;
3171 for (unsigned j = index; j < count; j++) {
3172 if (size > 4)
3173 riscv_batch_add_dmi_read(batch, DM_DATA1);
3174 riscv_batch_add_dmi_read(batch, DM_DATA0);
3175
3176 reads++;
3177 if (riscv_batch_full(batch))
3178 break;
3179 }
3180
3181 batch_run(target, batch);
3182
3183 /* Wait for the target to finish performing the last abstract command,
3184 * and update our copy of cmderr. If we see that DMI is busy here,
3185 * dmi_busy_delay will be incremented. */
3186 uint32_t abstractcs;
3187 if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK)
3188 return ERROR_FAIL;
3189 while (get_field(abstractcs, DM_ABSTRACTCS_BUSY))
3190 if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK)
3191 return ERROR_FAIL;
3192 info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
3193
3194 unsigned next_index;
3195 unsigned ignore_last = 0;
3196 switch (info->cmderr) {
3197 case CMDERR_NONE:
3198 LOG_DEBUG("successful (partial?) memory read");
3199 next_index = index + reads;
3200 break;
3201 case CMDERR_BUSY:
3202 LOG_DEBUG("memory read resulted in busy response");
3203
3204 increase_ac_busy_delay(target);
3205 riscv013_clear_abstract_error(target);
3206
3207 dmi_write(target, DM_ABSTRACTAUTO, 0);
3208
3209 uint32_t dmi_data0, dmi_data1 = 0;
3210 /* This is definitely a good version of the value that we
3211 * attempted to read when we discovered that the target was
3212 * busy. */
3213 if (dmi_read(target, &dmi_data0, DM_DATA0) != ERROR_OK) {
3214 riscv_batch_free(batch);
3215 goto error;
3216 }
3217 if (size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK) {
3218 riscv_batch_free(batch);
3219 goto error;
3220 }
3221
3222 /* See how far we got, clobbering dmi_data0. */
3223 if (increment == 0) {
3224 uint64_t counter;
3225 result = register_read_direct(target, &counter, GDB_REGNO_S2);
3226 next_index = counter;
3227 } else {
3228 uint64_t next_read_addr;
3229 result = register_read_direct(target, &next_read_addr,
3230 GDB_REGNO_S0);
3231 next_index = (next_read_addr - address) / increment;
3232 }
3233 if (result != ERROR_OK) {
3234 riscv_batch_free(batch);
3235 goto error;
3236 }
3237
3238 uint64_t value64 = (((uint64_t)dmi_data1) << 32) | dmi_data0;
3239 buf_set_u64(buffer + (next_index - 2) * size, 0, 8 * size, value64);
3240 log_memory_access(address + (next_index - 2) * size, value64, size, true);
3241
3242 /* Restore the command, and execute it.
3243 * Now DM_DATA0 contains the next value just as it would if no
3244 * error had occurred. */
3245 dmi_write_exec(target, DM_COMMAND, command, true);
3246 next_index++;
3247
3248 dmi_write(target, DM_ABSTRACTAUTO,
3249 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
3250
3251 ignore_last = 1;
3252
3253 break;
3254 default:
3255 LOG_DEBUG("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
3256 riscv013_clear_abstract_error(target);
3257 riscv_batch_free(batch);
3258 result = ERROR_FAIL;
3259 goto error;
3260 }
3261
3262 /* Now read whatever we got out of the batch. */
3263 dmi_status_t status = DMI_STATUS_SUCCESS;
3264 unsigned read = 0;
3265 assert(index >= 2);
3266 for (unsigned j = index - 2; j < index + reads; j++) {
3267 assert(j < count);
3268 LOG_DEBUG("index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d",
3269 index, reads, next_index, ignore_last, j);
3270 if (j + 3 + ignore_last > next_index)
3271 break;
3272
3273 status = riscv_batch_get_dmi_read_op(batch, read);
3274 uint64_t value = riscv_batch_get_dmi_read_data(batch, read);
3275 read++;
3276 if (status != DMI_STATUS_SUCCESS) {
3277 /* If we're here because of busy count, dmi_busy_delay will
3278 * already have been increased and busy state will have been
3279 * cleared in dmi_read(). */
3280 /* In at least some implementations, we issue a read, and then
3281 * can get busy back when we try to scan out the read result,
3282 * and the actual read value is lost forever. Since this is
3283 * rare in any case, we return error here and rely on our
3284 * caller to reread the entire block. */
3285 LOG_WARNING("Batch memory read encountered DMI error %d. "
3286 "Falling back on slower reads.", status);
3287 riscv_batch_free(batch);
3288 result = ERROR_FAIL;
3289 goto error;
3290 }
3291 if (size > 4) {
3292 status = riscv_batch_get_dmi_read_op(batch, read);
3293 if (status != DMI_STATUS_SUCCESS) {
3294 LOG_WARNING("Batch memory read encountered DMI error %d. "
3295 "Falling back on slower reads.", status);
3296 riscv_batch_free(batch);
3297 result = ERROR_FAIL;
3298 goto error;
3299 }
3300 value <<= 32;
3301 value |= riscv_batch_get_dmi_read_data(batch, read);
3302 read++;
3303 }
3304 riscv_addr_t offset = j * size;
3305 buf_set_u64(buffer + offset, 0, 8 * size, value);
3306 log_memory_access(address + j * increment, value, size, true);
3307 }
3308
3309 index = next_index;
3310
3311 riscv_batch_free(batch);
3312 }
3313
3314 dmi_write(target, DM_ABSTRACTAUTO, 0);
3315
3316 if (count > 1) {
3317 /* Read the penultimate word. */
3318 uint32_t dmi_data0, dmi_data1 = 0;
3319 if (dmi_read(target, &dmi_data0, DM_DATA0) != ERROR_OK)
3320 return ERROR_FAIL;
3321 if (size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK)
3322 return ERROR_FAIL;
3323 uint64_t value64 = (((uint64_t)dmi_data1) << 32) | dmi_data0;
3324 buf_set_u64(buffer + size * (count - 2), 0, 8 * size, value64);
3325 log_memory_access(address + size * (count - 2), value64, size, true);
3326 }
3327
3328 /* Read the last word. */
3329 uint64_t value;
3330 result = register_read_direct(target, &value, GDB_REGNO_S1);
3331 if (result != ERROR_OK)
3332 goto error;
3333 buf_set_u64(buffer + size * (count-1), 0, 8 * size, value);
3334 log_memory_access(address + size * (count-1), value, size, true);
3335
3336 return ERROR_OK;
3337
3338 error:
3339 dmi_write(target, DM_ABSTRACTAUTO, 0);
3340
3341 return result;
3342 }
3343
3344 /* Only need to save/restore one GPR to read a single word, and the progbuf
3345 * program doesn't need to increment. */
3346 static int read_memory_progbuf_one(struct target *target, target_addr_t address,
3347 uint32_t size, uint8_t *buffer)
3348 {
3349 uint64_t mstatus = 0;
3350 uint64_t mstatus_old = 0;
3351 if (modify_privilege(target, &mstatus, &mstatus_old) != ERROR_OK)
3352 return ERROR_FAIL;
3353
3354 uint64_t s0;
3355 int result = ERROR_FAIL;
3356
3357 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
3358 goto restore_mstatus;
3359
3360 /* Write the program (load, increment) */
3361 struct riscv_program program;
3362 riscv_program_init(&program, target);
3363 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3364 riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3365 switch (size) {
3366 case 1:
3367 riscv_program_lbr(&program, GDB_REGNO_S0, GDB_REGNO_S0, 0);
3368 break;
3369 case 2:
3370 riscv_program_lhr(&program, GDB_REGNO_S0, GDB_REGNO_S0, 0);
3371 break;
3372 case 4:
3373 riscv_program_lwr(&program, GDB_REGNO_S0, GDB_REGNO_S0, 0);
3374 break;
3375 case 8:
3376 riscv_program_ldr(&program, GDB_REGNO_S0, GDB_REGNO_S0, 0);
3377 break;
3378 default:
3379 LOG_ERROR("Unsupported size: %d", size);
3380 goto restore_mstatus;
3381 }
3382 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3383 riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3384
3385 if (riscv_program_ebreak(&program) != ERROR_OK)
3386 goto restore_mstatus;
3387 if (riscv_program_write(&program) != ERROR_OK)
3388 goto restore_mstatus;
3389
3390 /* Write address to S0, and execute buffer. */
3391 if (write_abstract_arg(target, 0, address, riscv_xlen(target)) != ERROR_OK)
3392 goto restore_mstatus;
3393 uint32_t command = access_register_command(target, GDB_REGNO_S0,
3394 riscv_xlen(target), AC_ACCESS_REGISTER_WRITE |
3395 AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_POSTEXEC);
3396 if (execute_abstract_command(target, command) != ERROR_OK)
3397 goto restore_s0;
3398
3399 uint64_t value;
3400 if (register_read(target, &value, GDB_REGNO_S0) != ERROR_OK)
3401 goto restore_s0;
3402 buf_set_u64(buffer, 0, 8 * size, value);
3403 log_memory_access(address, value, size, true);
3404 result = ERROR_OK;
3405
3406 restore_s0:
3407 if (riscv_set_register(target, GDB_REGNO_S0, s0) != ERROR_OK)
3408 result = ERROR_FAIL;
3409
3410 restore_mstatus:
3411 if (mstatus != mstatus_old)
3412 if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus_old))
3413 result = ERROR_FAIL;
3414
3415 return result;
3416 }
3417
3418 /**
3419 * Read the requested memory, silently handling memory access errors.
3420 */
3421 static int read_memory_progbuf(struct target *target, target_addr_t address,
3422 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
3423 {
3424 if (riscv_xlen(target) < size * 8) {
3425 LOG_ERROR("XLEN (%d) is too short for %d-bit memory read.",
3426 riscv_xlen(target), size * 8);
3427 return ERROR_FAIL;
3428 }
3429
3430 int result = ERROR_OK;
3431
3432 LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
3433 size, address);
3434
3435 select_dmi(target);
3436
3437 memset(buffer, 0, count*size);
3438
3439 if (execute_fence(target) != ERROR_OK)
3440 return ERROR_FAIL;
3441
3442 if (count == 1)
3443 return read_memory_progbuf_one(target, address, size, buffer);
3444
3445 uint64_t mstatus = 0;
3446 uint64_t mstatus_old = 0;
3447 if (modify_privilege(target, &mstatus, &mstatus_old) != ERROR_OK)
3448 return ERROR_FAIL;
3449
3450 /* s0 holds the next address to read from
3451 * s1 holds the next data value read
3452 * s2 is a counter in case increment is 0
3453 */
3454 uint64_t s0, s1, s2;
3455 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
3456 return ERROR_FAIL;
3457 if (register_read(target, &s1, GDB_REGNO_S1) != ERROR_OK)
3458 return ERROR_FAIL;
3459 if (increment == 0 && register_read(target, &s2, GDB_REGNO_S2) != ERROR_OK)
3460 return ERROR_FAIL;
3461
3462 /* Write the program (load, increment) */
3463 struct riscv_program program;
3464 riscv_program_init(&program, target);
3465 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3466 riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3467
3468 switch (size) {
3469 case 1:
3470 riscv_program_lbr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3471 break;
3472 case 2:
3473 riscv_program_lhr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3474 break;
3475 case 4:
3476 riscv_program_lwr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3477 break;
3478 case 8:
3479 riscv_program_ldr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3480 break;
3481 default:
3482 LOG_ERROR("Unsupported size: %d", size);
3483 return ERROR_FAIL;
3484 }
3485
3486 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3487 riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3488 if (increment == 0)
3489 riscv_program_addi(&program, GDB_REGNO_S2, GDB_REGNO_S2, 1);
3490 else
3491 riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, increment);
3492
3493 if (riscv_program_ebreak(&program) != ERROR_OK)
3494 return ERROR_FAIL;
3495 if (riscv_program_write(&program) != ERROR_OK)
3496 return ERROR_FAIL;
3497
3498 result = read_memory_progbuf_inner(target, address, size, count, buffer, increment);
3499
3500 if (result != ERROR_OK) {
3501 /* The full read did not succeed, so we will try to read each word individually. */
3502 /* This will not be fast, but reading outside actual memory is a special case anyway. */
3503 /* It will make the toolchain happier, especially Eclipse Memory View as it reads ahead. */
3504 target_addr_t address_i = address;
3505 uint32_t count_i = 1;
3506 uint8_t *buffer_i = buffer;
3507
3508 for (uint32_t i = 0; i < count; i++, address_i += increment, buffer_i += size) {
3509 /* TODO: This is much slower than it needs to be because we end up
3510 * writing the address to read for every word we read. */
3511 result = read_memory_progbuf_inner(target, address_i, size, count_i, buffer_i, increment);
3512
3513 /* The read of a single word failed, so we will just return 0 for that instead */
3514 if (result != ERROR_OK) {
3515 LOG_DEBUG("error reading single word of %d bytes from 0x%" TARGET_PRIxADDR,
3516 size, address_i);
3517
3518 buf_set_u64(buffer_i, 0, 8 * size, 0);
3519 }
3520 }
3521 result = ERROR_OK;
3522 }
3523
3524 riscv_set_register(target, GDB_REGNO_S0, s0);
3525 riscv_set_register(target, GDB_REGNO_S1, s1);
3526 if (increment == 0)
3527 riscv_set_register(target, GDB_REGNO_S2, s2);
3528
3529 /* Restore MSTATUS */
3530 if (mstatus != mstatus_old)
3531 if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus_old))
3532 return ERROR_FAIL;
3533
3534 return result;
3535 }
3536
3537 static int read_memory(struct target *target, target_addr_t address,
3538 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
3539 {
3540 if (count == 0)
3541 return ERROR_OK;
3542
3543 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) {
3544 LOG_ERROR("BUG: Unsupported size for memory read: %d", size);
3545 return ERROR_FAIL;
3546 }
3547
3548 int ret = ERROR_FAIL;
3549 RISCV_INFO(r);
3550 RISCV013_INFO(info);
3551
3552 char *progbuf_result = "disabled";
3553 char *sysbus_result = "disabled";
3554 char *abstract_result = "disabled";
3555
3556 for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
3557 int method = r->mem_access_methods[i];
3558
3559 if (method == RISCV_MEM_ACCESS_PROGBUF) {
3560 if (mem_should_skip_progbuf(target, address, size, true, &progbuf_result))
3561 continue;
3562
3563 ret = read_memory_progbuf(target, address, size, count, buffer, increment);
3564
3565 if (ret != ERROR_OK)
3566 progbuf_result = "failed";
3567 } else if (method == RISCV_MEM_ACCESS_SYSBUS) {
3568 if (mem_should_skip_sysbus(target, address, size, increment, true, &sysbus_result))
3569 continue;
3570
3571 if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0)
3572 ret = read_memory_bus_v0(target, address, size, count, buffer, increment);
3573 else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1)
3574 ret = read_memory_bus_v1(target, address, size, count, buffer, increment);
3575
3576 if (ret != ERROR_OK)
3577 sysbus_result = "failed";
3578 } else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
3579 if (mem_should_skip_abstract(target, address, size, increment, true, &abstract_result))
3580 continue;
3581
3582 ret = read_memory_abstract(target, address, size, count, buffer, increment);
3583
3584 if (ret != ERROR_OK)
3585 abstract_result = "failed";
3586 } else if (method == RISCV_MEM_ACCESS_UNSPECIFIED)
3587 /* No further mem access method to try. */
3588 break;
3589
3590 log_mem_access_result(target, ret == ERROR_OK, method, true);
3591
3592 if (ret == ERROR_OK)
3593 return ret;
3594 }
3595
3596 LOG_ERROR("Target %s: Failed to read memory (addr=0x%" PRIx64 ")", target_name(target), address);
3597 LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
3598 return ret;
3599 }
3600
3601 static int write_memory_bus_v0(struct target *target, target_addr_t address,
3602 uint32_t size, uint32_t count, const uint8_t *buffer)
3603 {
3604 /*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/
3605 LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
3606 TARGET_PRIxADDR, size, count, address);
3607 dmi_write(target, DM_SBADDRESS0, address);
3608 int64_t value = 0;
3609 int64_t access = 0;
3610 riscv_addr_t offset = 0;
3611 riscv_addr_t t_addr = 0;
3612 const uint8_t *t_buffer = buffer + offset;
3613
3614 /* B.8 Writing Memory, single write check if we write in one go */
3615 if (count == 1) { /* count is in bytes here */
3616 value = buf_get_u64(t_buffer, 0, 8 * size);
3617
3618 access = 0;
3619 access = set_field(access, DM_SBCS_SBACCESS, size/2);
3620 dmi_write(target, DM_SBCS, access);
3621 LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
3622 LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value);
3623 dmi_write(target, DM_SBDATA0, value);
3624 return ERROR_OK;
3625 }
3626
3627 /*B.8 Writing Memory, using autoincrement*/
3628
3629 access = 0;
3630 access = set_field(access, DM_SBCS_SBACCESS, size/2);
3631 access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1);
3632 LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
3633 dmi_write(target, DM_SBCS, access);
3634
3635 /*2)set the value according to the size required and write*/
3636 for (riscv_addr_t i = 0; i < count; ++i) {
3637 offset = size*i;
3638 /* for monitoring only */
3639 t_addr = address + offset;
3640 t_buffer = buffer + offset;
3641
3642 value = buf_get_u64(t_buffer, 0, 8 * size);
3643 LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
3644 PRIx64, (uint32_t)t_addr, (uint32_t)value);
3645 dmi_write(target, DM_SBDATA0, value);
3646 }
3647 /*reset the autoincrement when finished (something weird is happening if this is not done at the end*/
3648 access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 0);
3649 dmi_write(target, DM_SBCS, access);
3650
3651 return ERROR_OK;
3652 }
3653
3654 static int write_memory_bus_v1(struct target *target, target_addr_t address,
3655 uint32_t size, uint32_t count, const uint8_t *buffer)
3656 {
3657 RISCV013_INFO(info);
3658 uint32_t sbcs = sb_sbaccess(size);
3659 sbcs = set_field(sbcs, DM_SBCS_SBAUTOINCREMENT, 1);
3660 dmi_write(target, DM_SBCS, sbcs);
3661
3662 target_addr_t next_address = address;
3663 target_addr_t end_address = address + count * size;
3664
3665 int result;
3666
3667 sb_write_address(target, next_address, true);
3668 while (next_address < end_address) {
3669 LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR,
3670 next_address);
3671
3672 struct riscv_batch *batch = riscv_batch_alloc(
3673 target,
3674 32,
3675 info->dmi_busy_delay + info->bus_master_write_delay);
3676 if (!batch)
3677 return ERROR_FAIL;
3678
3679 for (uint32_t i = (next_address - address) / size; i < count; i++) {
3680 const uint8_t *p = buffer + i * size;
3681
3682 if (riscv_batch_available_scans(batch) < (size + 3) / 4)
3683 break;
3684
3685 if (size > 12)
3686 riscv_batch_add_dmi_write(batch, DM_SBDATA3,
3687 ((uint32_t) p[12]) |
3688 (((uint32_t) p[13]) << 8) |
3689 (((uint32_t) p[14]) << 16) |
3690 (((uint32_t) p[15]) << 24));
3691
3692 if (size > 8)
3693 riscv_batch_add_dmi_write(batch, DM_SBDATA2,
3694 ((uint32_t) p[8]) |
3695 (((uint32_t) p[9]) << 8) |
3696 (((uint32_t) p[10]) << 16) |
3697 (((uint32_t) p[11]) << 24));
3698 if (size > 4)
3699 riscv_batch_add_dmi_write(batch, DM_SBDATA1,
3700 ((uint32_t) p[4]) |
3701 (((uint32_t) p[5]) << 8) |
3702 (((uint32_t) p[6]) << 16) |
3703 (((uint32_t) p[7]) << 24));
3704 uint32_t value = p[0];
3705 if (size > 2) {
3706 value |= ((uint32_t) p[2]) << 16;
3707 value |= ((uint32_t) p[3]) << 24;
3708 }
3709 if (size > 1)
3710 value |= ((uint32_t) p[1]) << 8;
3711 riscv_batch_add_dmi_write(batch, DM_SBDATA0, value);
3712
3713 log_memory_access(address + i * size, value, size, false);
3714 next_address += size;
3715 }
3716
3717 /* Execute the batch of writes */
3718 result = batch_run(target, batch);
3719 riscv_batch_free(batch);
3720 if (result != ERROR_OK)
3721 return result;
3722
3723 /* Read sbcs value.
3724 * At the same time, detect if DMI busy has occurred during the batch write. */
3725 bool dmi_busy_encountered;
3726 if (dmi_op(target, &sbcs, &dmi_busy_encountered, DMI_OP_READ,
3727 DM_SBCS, 0, false, true) != ERROR_OK)
3728 return ERROR_FAIL;
3729 if (dmi_busy_encountered)
3730 LOG_DEBUG("DMI busy encountered during system bus write.");
3731
3732 /* Wait until sbbusy goes low */
3733 time_t start = time(NULL);
3734 while (get_field(sbcs, DM_SBCS_SBBUSY)) {
3735 if (time(NULL) - start > riscv_command_timeout_sec) {
3736 LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
3737 "Increase the timeout with riscv set_command_timeout_sec.",
3738 riscv_command_timeout_sec, sbcs);
3739 return ERROR_FAIL;
3740 }
3741 if (dmi_read(target, &sbcs, DM_SBCS) != ERROR_OK)
3742 return ERROR_FAIL;
3743 }
3744
3745 if (get_field(sbcs, DM_SBCS_SBBUSYERROR)) {
3746 /* We wrote while the target was busy. */
3747 LOG_DEBUG("Sbbusyerror encountered during system bus write.");
3748 /* Clear the sticky error flag. */
3749 dmi_write(target, DM_SBCS, sbcs | DM_SBCS_SBBUSYERROR);
3750 /* Slow down before trying again. */
3751 info->bus_master_write_delay += info->bus_master_write_delay / 10 + 1;
3752 }
3753
3754 if (get_field(sbcs, DM_SBCS_SBBUSYERROR) || dmi_busy_encountered) {
3755 /* Recover from the case when the write commands were issued too fast.
3756 * Determine the address from which to resume writing. */
3757 next_address = sb_read_address(target);
3758 if (next_address < address) {
3759 /* This should never happen, probably buggy hardware. */
3760 LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
3761 " - buggy sbautoincrement in hw?", next_address);
3762 /* Fail the whole operation. */
3763 return ERROR_FAIL;
3764 }
3765 /* Try again - resume writing. */
3766 continue;
3767 }
3768
3769 unsigned int sberror = get_field(sbcs, DM_SBCS_SBERROR);
3770 if (sberror != 0) {
3771 /* Sberror indicates the bus access failed, but not because we issued the writes
3772 * too fast. Cannot recover. Sbaddress holds the address where the error occurred
3773 * (unless sbautoincrement in the HW is buggy).
3774 */
3775 target_addr_t sbaddress = sb_read_address(target);
3776 LOG_DEBUG("System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
3777 sberror, sbaddress);
3778 if (sbaddress < address) {
3779 /* This should never happen, probably buggy hardware.
3780 * Make a note to the user not to trust the sbaddress value. */
3781 LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
3782 " - buggy sbautoincrement in hw?", next_address);
3783 }
3784 /* Clear the sticky error flag */
3785 dmi_write(target, DM_SBCS, DM_SBCS_SBERROR);
3786 /* Fail the whole operation */
3787 return ERROR_FAIL;
3788 }
3789 }
3790
3791 return ERROR_OK;
3792 }
3793
3794 static int write_memory_progbuf(struct target *target, target_addr_t address,
3795 uint32_t size, uint32_t count, const uint8_t *buffer)
3796 {
3797 RISCV013_INFO(info);
3798
3799 if (riscv_xlen(target) < size * 8) {
3800 LOG_ERROR("XLEN (%d) is too short for %d-bit memory write.",
3801 riscv_xlen(target), size * 8);
3802 return ERROR_FAIL;
3803 }
3804
3805 LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
3806
3807 select_dmi(target);
3808
3809 uint64_t mstatus = 0;
3810 uint64_t mstatus_old = 0;
3811 if (modify_privilege(target, &mstatus, &mstatus_old) != ERROR_OK)
3812 return ERROR_FAIL;
3813
3814 /* s0 holds the next address to write to
3815 * s1 holds the next data value to write
3816 */
3817
3818 int result = ERROR_OK;
3819 uint64_t s0, s1;
3820 if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
3821 return ERROR_FAIL;
3822 if (register_read(target, &s1, GDB_REGNO_S1) != ERROR_OK)
3823 return ERROR_FAIL;
3824
3825 /* Write the program (store, increment) */
3826 struct riscv_program program;
3827 riscv_program_init(&program, target);
3828 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3829 riscv_program_csrrsi(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3830
3831 switch (size) {
3832 case 1:
3833 riscv_program_sbr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3834 break;
3835 case 2:
3836 riscv_program_shr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3837 break;
3838 case 4:
3839 riscv_program_swr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3840 break;
3841 case 8:
3842 riscv_program_sdr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
3843 break;
3844 default:
3845 LOG_ERROR("write_memory_progbuf(): Unsupported size: %d", size);
3846 result = ERROR_FAIL;
3847 goto error;
3848 }
3849
3850 if (riscv_enable_virtual && has_sufficient_progbuf(target, 5) && get_field(mstatus, MSTATUS_MPRV))
3851 riscv_program_csrrci(&program, GDB_REGNO_ZERO, CSR_DCSR_MPRVEN, GDB_REGNO_DCSR);
3852 riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, size);
3853
3854 result = riscv_program_ebreak(&program);
3855 if (result != ERROR_OK)
3856 goto error;
3857 riscv_program_write(&program);
3858
3859 riscv_addr_t cur_addr = address;
3860 riscv_addr_t fin_addr = address + (count * size);
3861 bool setup_needed = true;
3862 LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr);
3863 while (cur_addr < fin_addr) {
3864 LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64,
3865 cur_addr);
3866
3867 struct riscv_batch *batch = riscv_batch_alloc(
3868 target,
3869 32,
3870 info->dmi_busy_delay + info->ac_busy_delay);
3871 if (!batch)
3872 goto error;
3873
3874 /* To write another word, we put it in S1 and execute the program. */
3875 unsigned start = (cur_addr - address) / size;
3876 for (unsigned i = start; i < count; ++i) {
3877 unsigned offset = size*i;
3878 const uint8_t *t_buffer = buffer + offset;
3879
3880 uint64_t value = buf_get_u64(t_buffer, 0, 8 * size);
3881
3882 log_memory_access(address + offset, value, size, false);
3883 cur_addr += size;
3884
3885 if (setup_needed) {
3886 result = register_write_direct(target, GDB_REGNO_S0,
3887 address + offset);
3888 if (result != ERROR_OK) {
3889 riscv_batch_free(batch);
3890 goto error;
3891 }
3892
3893 /* Write value. */
3894 if (size > 4)
3895 dmi_write(target, DM_DATA1, value >> 32);
3896 dmi_write(target, DM_DATA0, value);
3897
3898 /* Write and execute command that moves value into S1 and
3899 * executes program buffer. */
3900 uint32_t command = access_register_command(target,
3901 GDB_REGNO_S1, riscv_xlen(target),
3902 AC_ACCESS_REGISTER_POSTEXEC |
3903 AC_ACCESS_REGISTER_TRANSFER |
3904 AC_ACCESS_REGISTER_WRITE);
3905 result = execute_abstract_command(target, command);
3906 if (result != ERROR_OK) {
3907 riscv_batch_free(batch);
3908 goto error;
3909 }
3910
3911 /* Turn on autoexec */
3912 dmi_write(target, DM_ABSTRACTAUTO,
3913 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET);
3914
3915 setup_needed = false;
3916 } else {
3917 if (size > 4)
3918 riscv_batch_add_dmi_write(batch, DM_DATA1, value >> 32);
3919 riscv_batch_add_dmi_write(batch, DM_DATA0, value);
3920 if (riscv_batch_full(batch))
3921 break;
3922 }
3923 }
3924
3925 result = batch_run(target, batch);
3926 riscv_batch_free(batch);
3927 if (result != ERROR_OK)
3928 goto error;
3929
3930 /* Note that if the scan resulted in a Busy DMI response, it
3931 * is this read to abstractcs that will cause the dmi_busy_delay
3932 * to be incremented if necessary. */
3933
3934 uint32_t abstractcs;
3935 bool dmi_busy_encountered;
3936 result = dmi_op(target, &abstractcs, &dmi_busy_encountered,
3937 DMI_OP_READ, DM_ABSTRACTCS, 0, false, true);
3938 if (result != ERROR_OK)
3939 goto error;
3940 while (get_field(abstractcs, DM_ABSTRACTCS_BUSY))
3941 if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK)
3942 return ERROR_FAIL;
3943 info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
3944 if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered) {
3945 LOG_DEBUG("successful (partial?) memory write");
3946 } else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) {
3947 if (info->cmderr == CMDERR_BUSY)
3948 LOG_DEBUG("Memory write resulted in abstract command busy response.");
3949 else if (dmi_busy_encountered)
3950 LOG_DEBUG("Memory write resulted in DMI busy response.");
3951 riscv013_clear_abstract_error(target);
3952 increase_ac_busy_delay(target);
3953
3954 dmi_write(target, DM_ABSTRACTAUTO, 0);
3955 result = register_read_direct(target, &cur_addr, GDB_REGNO_S0);
3956 if (result != ERROR_OK)
3957 goto error;
3958 setup_needed = true;
3959 } else {
3960 LOG_ERROR("error when writing memory, abstractcs=0x%08lx", (long)abstractcs);
3961 riscv013_clear_abstract_error(target);
3962 result = ERROR_FAIL;
3963 goto error;
3964 }
3965 }
3966
3967 error:
3968 dmi_write(target, DM_ABSTRACTAUTO, 0);
3969
3970 if (register_write_direct(target, GDB_REGNO_S1, s1) != ERROR_OK)
3971 return ERROR_FAIL;
3972 if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
3973 return ERROR_FAIL;
3974
3975 /* Restore MSTATUS */
3976 if (mstatus != mstatus_old)
3977 if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus_old))
3978 return ERROR_FAIL;
3979
3980 if (execute_fence(target) != ERROR_OK)
3981 return ERROR_FAIL;
3982
3983 return result;
3984 }
3985
3986 static int write_memory(struct target *target, target_addr_t address,
3987 uint32_t size, uint32_t count, const uint8_t *buffer)
3988 {
3989 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) {
3990 LOG_ERROR("BUG: Unsupported size for memory write: %d", size);
3991 return ERROR_FAIL;
3992 }
3993
3994 int ret = ERROR_FAIL;
3995 RISCV_INFO(r);
3996 RISCV013_INFO(info);
3997
3998 char *progbuf_result = "disabled";
3999 char *sysbus_result = "disabled";
4000 char *abstract_result = "disabled";
4001
4002 for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
4003 int method = r->mem_access_methods[i];
4004
4005 if (method == RISCV_MEM_ACCESS_PROGBUF) {
4006 if (mem_should_skip_progbuf(target, address, size, false, &progbuf_result))
4007 continue;
4008
4009 ret = write_memory_progbuf(target, address, size, count, buffer);
4010
4011 if (ret != ERROR_OK)
4012 progbuf_result = "failed";
4013 } else if (method == RISCV_MEM_ACCESS_SYSBUS) {
4014 if (mem_should_skip_sysbus(target, address, size, 0, false, &sysbus_result))
4015 continue;
4016
4017 if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0)
4018 ret = write_memory_bus_v0(target, address, size, count, buffer);
4019 else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1)
4020 ret = write_memory_bus_v1(target, address, size, count, buffer);
4021
4022 if (ret != ERROR_OK)
4023 sysbus_result = "failed";
4024 } else if (method == RISCV_MEM_ACCESS_ABSTRACT) {
4025 if (mem_should_skip_abstract(target, address, size, 0, false, &abstract_result))
4026 continue;
4027
4028 ret = write_memory_abstract(target, address, size, count, buffer);
4029
4030 if (ret != ERROR_OK)
4031 abstract_result = "failed";
4032 } else if (method == RISCV_MEM_ACCESS_UNSPECIFIED)
4033 /* No further mem access method to try. */
4034 break;
4035
4036 log_mem_access_result(target, ret == ERROR_OK, method, false);
4037
4038 if (ret == ERROR_OK)
4039 return ret;
4040 }
4041
4042 LOG_ERROR("Target %s: Failed to write memory (addr=0x%" PRIx64 ")", target_name(target), address);
4043 LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
4044 return ret;
4045 }
4046
4047 static int arch_state(struct target *target)
4048 {
4049 return ERROR_OK;
4050 }
4051
4052 struct target_type riscv013_target = {
4053 .name = "riscv",
4054
4055 .init_target = init_target,
4056 .deinit_target = deinit_target,
4057 .examine = examine,
4058
4059 .poll = &riscv_openocd_poll,
4060 .halt = &riscv_halt,
4061 .step = &riscv_openocd_step,
4062
4063 .assert_reset = assert_reset,
4064 .deassert_reset = deassert_reset,
4065
4066 .write_memory = write_memory,
4067
4068 .arch_state = arch_state
4069 };
4070
4071 /*** 0.13-specific implementations of various RISC-V helper functions. ***/
4072 static int riscv013_get_register(struct target *target,
4073 riscv_reg_t *value, int rid)
4074 {
4075 LOG_DEBUG("[%s] reading register %s", target_name(target),
4076 gdb_regno_name(rid));
4077
4078 if (riscv_select_current_hart(target) != ERROR_OK)
4079 return ERROR_FAIL;
4080
4081 int result = ERROR_OK;
4082 if (rid == GDB_REGNO_PC) {
4083 /* TODO: move this into riscv.c. */
4084 result = register_read(target, value, GDB_REGNO_DPC);
4085 LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
4086 } else if (rid == GDB_REGNO_PRIV) {
4087 uint64_t dcsr;
4088 /* TODO: move this into riscv.c. */
4089 result = register_read(target, &dcsr, GDB_REGNO_DCSR);
4090 *value = set_field(0, VIRT_PRIV_V, get_field(dcsr, CSR_DCSR_V));
4091 *value = set_field(*value, VIRT_PRIV_PRV, get_field(dcsr, CSR_DCSR_PRV));
4092 } else {
4093 result = register_read(target, value, rid);
4094 if (result != ERROR_OK)
4095 *value = -1;
4096 }
4097
4098 return result;
4099 }
4100
4101 static int riscv013_set_register(struct target *target, int rid, uint64_t value)
4102 {
4103 riscv013_select_current_hart(target);
4104 LOG_DEBUG("[%d] writing 0x%" PRIx64 " to register %s",
4105 target->coreid, value, gdb_regno_name(rid));
4106
4107 if (rid <= GDB_REGNO_XPR31) {
4108 return register_write_direct(target, rid, value);
4109 } else if (rid == GDB_REGNO_PC) {
4110 LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
4111 register_write_direct(target, GDB_REGNO_DPC, value);
4112 uint64_t actual_value;
4113 register_read_direct(target, &actual_value, GDB_REGNO_DPC);
4114 LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
4115 if (value != actual_value) {
4116 LOG_ERROR("Written PC (0x%" PRIx64 ") does not match read back "
4117 "value (0x%" PRIx64 ")", value, actual_value);
4118 return ERROR_FAIL;
4119 }
4120 } else if (rid == GDB_REGNO_PRIV) {
4121 uint64_t dcsr;
4122 register_read(target, &dcsr, GDB_REGNO_DCSR);
4123 dcsr = set_field(dcsr, CSR_DCSR_PRV, get_field(value, VIRT_PRIV_PRV));
4124 dcsr = set_field(dcsr, CSR_DCSR_V, get_field(value, VIRT_PRIV_V));
4125 return register_write_direct(target, GDB_REGNO_DCSR, dcsr);
4126 } else {
4127 return register_write_direct(target, rid, value);
4128 }
4129
4130 return ERROR_OK;
4131 }
4132
4133 static int riscv013_select_current_hart(struct target *target)
4134 {
4135 RISCV_INFO(r);
4136
4137 dm013_info_t *dm = get_dm(target);
4138 if (!dm)
4139 return ERROR_FAIL;
4140 if (r->current_hartid == dm->current_hartid)
4141 return ERROR_OK;
4142
4143 uint32_t dmcontrol;
4144 /* TODO: can't we just "dmcontrol = DMI_DMACTIVE"? */
4145 if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK)
4146 return ERROR_FAIL;
4147 dmcontrol = set_hartsel(dmcontrol, r->current_hartid);
4148 int result = dmi_write(target, DM_DMCONTROL, dmcontrol);
4149 dm->current_hartid = r->current_hartid;
4150 return result;
4151 }
4152
4153 /* Select all harts that were prepped and that are selectable, clearing the
4154 * prepped flag on the harts that actually were selected. */
4155 static int select_prepped_harts(struct target *target, bool *use_hasel)
4156 {
4157 dm013_info_t *dm = get_dm(target);
4158 if (!dm)
4159 return ERROR_FAIL;
4160 if (!dm->hasel_supported) {
4161 RISCV_INFO(r);
4162 r->prepped = false;
4163 *use_hasel = false;
4164 return ERROR_OK;
4165 }
4166
4167 assert(dm->hart_count);
4168 unsigned hawindow_count = (dm->hart_count + 31) / 32;
4169 uint32_t hawindow[hawindow_count];
4170
4171 memset(hawindow, 0, sizeof(uint32_t) * hawindow_count);
4172
4173 target_list_t *entry;
4174 unsigned total_selected = 0;
4175 list_for_each_entry(entry, &dm->target_list, list) {
4176 struct target *t = entry->target;
4177 riscv_info_t *r = riscv_info(t);
4178 riscv013_info_t *info = get_info(t);
4179 unsigned index = info->index;
4180 LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
4181 r->selected = r->prepped;
4182 if (r->prepped) {
4183 hawindow[index / 32] |= 1 << (index % 32);
4184 r->prepped = false;
4185 total_selected++;
4186 }
4187 index++;
4188 }
4189
4190 /* Don't use hasel if we only need to talk to one hart. */
4191 if (total_selected <= 1) {
4192 *use_hasel = false;
4193 return ERROR_OK;
4194 }
4195
4196 for (unsigned i = 0; i < hawindow_count; i++) {
4197 if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK)
4198 return ERROR_FAIL;
4199 if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK)
4200 return ERROR_FAIL;
4201 }
4202
4203 *use_hasel = true;
4204 return ERROR_OK;
4205 }
4206
4207 static int riscv013_halt_prep(struct target *target)
4208 {
4209 return ERROR_OK;
4210 }
4211
4212 static int riscv013_halt_go(struct target *target)
4213 {
4214 bool use_hasel = false;
4215 if (select_prepped_harts(target, &use_hasel) != ERROR_OK)
4216 return ERROR_FAIL;
4217
4218 RISCV_INFO(r);
4219 LOG_DEBUG("halting hart %d", r->current_hartid);
4220
4221 /* Issue the halt command, and then wait for the current hart to halt. */
4222 uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_HALTREQ;
4223 if (use_hasel)
4224 dmcontrol |= DM_DMCONTROL_HASEL;
4225 dmcontrol = set_hartsel(dmcontrol, r->current_hartid);
4226 dmi_write(target, DM_DMCONTROL, dmcontrol);
4227 for (size_t i = 0; i < 256; ++i)
4228 if (riscv_is_halted(target))
4229 break;
4230
4231 if (!riscv_is_halted(target)) {
4232 uint32_t dmstatus;
4233 if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
4234 return ERROR_FAIL;
4235 if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK)
4236 return ERROR_FAIL;
4237
4238 LOG_ERROR("unable to halt hart %d", r->current_hartid);
4239 LOG_ERROR(" dmcontrol=0x%08x", dmcontrol);
4240 LOG_ERROR(" dmstatus =0x%08x", dmstatus);
4241 return ERROR_FAIL;
4242 }
4243
4244 dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HALTREQ, 0);
4245 dmi_write(target, DM_DMCONTROL, dmcontrol);
4246
4247 if (use_hasel) {
4248 target_list_t *entry;
4249 dm013_info_t *dm = get_dm(target);
4250 if (!dm)
4251 return ERROR_FAIL;
4252 list_for_each_entry(entry, &dm->target_list, list) {
4253 struct target *t = entry->target;
4254 t->state = TARGET_HALTED;
4255 if (t->debug_reason == DBG_REASON_NOTHALTED)
4256 t->debug_reason = DBG_REASON_DBGRQ;
4257 }
4258 }
4259 /* The "else" case is handled in halt_go(). */
4260
4261 return ERROR_OK;
4262 }
4263
4264 static int riscv013_resume_go(struct target *target)
4265 {
4266 bool use_hasel = false;
4267 if (select_prepped_harts(target, &use_hasel) != ERROR_OK)
4268 return ERROR_FAIL;
4269
4270 return riscv013_step_or_resume_current_hart(target, false, use_hasel);
4271 }
4272
4273 static int riscv013_step_current_hart(struct target *target)
4274 {
4275 return riscv013_step_or_resume_current_hart(target, true, false);
4276 }
4277
4278 static int riscv013_resume_prep(struct target *target)
4279 {
4280 return riscv013_on_step_or_resume(target, false);
4281 }
4282
4283 static int riscv013_on_step(struct target *target)
4284 {
4285 return riscv013_on_step_or_resume(target, true);
4286 }
4287
4288 static int riscv013_on_halt(struct target *target)
4289 {
4290 return ERROR_OK;
4291 }
4292
4293 static bool riscv013_is_halted(struct target *target)
4294 {
4295 uint32_t dmstatus;
4296 if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
4297 return false;
4298 if (get_field(dmstatus, DM_DMSTATUS_ANYUNAVAIL))
4299 LOG_ERROR("Hart %d is unavailable.", riscv_current_hartid(target));
4300 if (get_field(dmstatus, DM_DMSTATUS_ANYNONEXISTENT))
4301 LOG_ERROR("Hart %d doesn't exist.", riscv_current_hartid(target));
4302 if (get_field(dmstatus, DM_DMSTATUS_ANYHAVERESET)) {
4303 int hartid = riscv_current_hartid(target);
4304 LOG_INFO("Hart %d unexpectedly reset!", hartid);
4305 /* TODO: Can we make this more obvious to eg. a gdb user? */
4306 uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE |
4307 DM_DMCONTROL_ACKHAVERESET;
4308 dmcontrol = set_hartsel(dmcontrol, hartid);
4309 /* If we had been halted when we reset, request another halt. If we
4310 * ended up running out of reset, then the user will (hopefully) get a
4311 * message that a reset happened, that the target is running, and then
4312 * that it is halted again once the request goes through.
4313 */
4314 if (target->state == TARGET_HALTED)
4315 dmcontrol |= DM_DMCONTROL_HALTREQ;
4316 dmi_write(target, DM_DMCONTROL, dmcontrol);
4317 }
4318 return get_field(dmstatus, DM_DMSTATUS_ALLHALTED);
4319 }
4320
4321 static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
4322 {
4323 riscv_reg_t dcsr;
4324 int result = register_read(target, &dcsr, GDB_REGNO_DCSR);
4325 if (result != ERROR_OK)
4326 return RISCV_HALT_UNKNOWN;
4327
4328 LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
4329
4330 switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
4331 case CSR_DCSR_CAUSE_SWBP:
4332 return RISCV_HALT_BREAKPOINT;
4333 case CSR_DCSR_CAUSE_TRIGGER:
4334 /* We could get here before triggers are enumerated if a trigger was
4335 * already set when we connected. Force enumeration now, which has the
4336 * side effect of clearing any triggers we did not set. */
4337 riscv_enumerate_triggers(target);
4338 LOG_DEBUG("{%d} halted because of trigger", target->coreid);
4339 return RISCV_HALT_TRIGGER;
4340 case CSR_DCSR_CAUSE_STEP:
4341 return RISCV_HALT_SINGLESTEP;
4342 case CSR_DCSR_CAUSE_DEBUGINT:
4343 case CSR_DCSR_CAUSE_HALT:
4344 return RISCV_HALT_INTERRUPT;
4345 case CSR_DCSR_CAUSE_GROUP:
4346 return RISCV_HALT_GROUP;
4347 }
4348
4349 LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
4350 LOG_ERROR(" dcsr=0x%016lx", (long)dcsr);
4351 return RISCV_HALT_UNKNOWN;
4352 }
4353
4354 int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
4355 {
4356 dm013_info_t *dm = get_dm(target);
4357 if (!dm)
4358 return ERROR_FAIL;
4359 if (dm->progbuf_cache[index] != data) {
4360 if (dmi_write(target, DM_PROGBUF0 + index, data) != ERROR_OK)
4361 return ERROR_FAIL;
4362 dm->progbuf_cache[index] = data;
4363 } else {
4364 LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index);
4365 }
4366 return ERROR_OK;
4367 }
4368
4369 riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index)
4370 {
4371 uint32_t value;
4372 dmi_read(target, &value, DM_PROGBUF0 + index);
4373 return value;
4374 }
4375
4376 int riscv013_execute_debug_buffer(struct target *target)
4377 {
4378 uint32_t run_program = 0;
4379 run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2);
4380 run_program = set_field(run_program, AC_ACCESS_REGISTER_POSTEXEC, 1);
4381 run_program = set_field(run_program, AC_ACCESS_REGISTER_TRANSFER, 0);
4382 run_program = set_field(run_program, AC_ACCESS_REGISTER_REGNO, 0x1000);
4383
4384 return execute_abstract_command(target, run_program);
4385 }
4386
4387 void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
4388 {
4389 RISCV013_INFO(info);
4390 buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
4391 buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
4392 buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
4393 }
4394
4395 void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
4396 {
4397 RISCV013_INFO(info);
4398 buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
4399 buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
4400 buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
4401 }
4402
4403 void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
4404 {
4405 RISCV013_INFO(info);
4406 buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
4407 buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
4408 buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
4409 }
4410
4411 /* Helper function for riscv013_test_sba_config_reg */
4412 static int get_max_sbaccess(struct target *target)
4413 {
4414 RISCV013_INFO(info);
4415
4416 uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128);
4417 uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64);
4418 uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32);
4419 uint32_t sbaccess16 = get_field(info->sbcs, DM_SBCS_SBACCESS16);
4420 uint32_t sbaccess8 = get_field(info->sbcs, DM_SBCS_SBACCESS8);
4421
4422 if (sbaccess128)
4423 return 4;
4424 else if (sbaccess64)
4425 return 3;
4426 else if (sbaccess32)
4427 return 2;
4428 else if (sbaccess16)
4429 return 1;
4430 else if (sbaccess8)
4431 return 0;
4432 else
4433 return -1;
4434 }
4435
4436 static uint32_t get_num_sbdata_regs(struct target *target)
4437 {
4438 RISCV013_INFO(info);
4439
4440 uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128);
4441 uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64);
4442 uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32);
4443
4444 if (sbaccess128)
4445 return 4;
4446 else if (sbaccess64)
4447 return 2;
4448 else if (sbaccess32)
4449 return 1;
4450 else
4451 return 0;
4452 }
4453
4454 static int riscv013_test_sba_config_reg(struct target *target,
4455 target_addr_t legal_address, uint32_t num_words,
4456 target_addr_t illegal_address, bool run_sbbusyerror_test)
4457 {
4458 LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13");
4459
4460 uint32_t tests_failed = 0;
4461
4462 uint32_t rd_val;
4463 uint32_t sbcs_orig;
4464 dmi_read(target, &sbcs_orig, DM_SBCS);
4465
4466 uint32_t sbcs = sbcs_orig;
4467 bool test_passed;
4468
4469 int max_sbaccess = get_max_sbaccess(target);
4470
4471 if (max_sbaccess == -1) {
4472 LOG_ERROR("System Bus Access not supported in this config.");
4473 return ERROR_FAIL;
4474 }
4475
4476 if (get_field(sbcs, DM_SBCS_SBVERSION) != 1) {
4477 LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.",
4478 get_field(sbcs, DM_SBCS_SBVERSION));
4479 return ERROR_FAIL;
4480 }
4481
4482 uint32_t num_sbdata_regs = get_num_sbdata_regs(target);
4483 assert(num_sbdata_regs);
4484
4485 uint32_t rd_buf[num_sbdata_regs];
4486
4487 /* Test 1: Simple write/read test */
4488 test_passed = true;
4489 sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 0);
4490 dmi_write(target, DM_SBCS, sbcs);
4491
4492 uint32_t test_patterns[4] = {0xdeadbeef, 0xfeedbabe, 0x12345678, 0x08675309};
4493 for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) {
4494 sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess);
4495 dmi_write(target, DM_SBCS, sbcs);
4496
4497 uint32_t compare_mask = (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff;
4498
4499 for (uint32_t i = 0; i < num_words; i++) {
4500 uint32_t addr = legal_address + (i << sbaccess);
4501 uint32_t wr_data[num_sbdata_regs];
4502 for (uint32_t j = 0; j < num_sbdata_regs; j++)
4503 wr_data[j] = test_patterns[j] + i;
4504 write_memory_sba_simple(target, addr, wr_data, num_sbdata_regs, sbcs);
4505 }
4506
4507 for (uint32_t i = 0; i < num_words; i++) {
4508 uint32_t addr = legal_address + (i << sbaccess);
4509 read_memory_sba_simple(target, addr, rd_buf, num_sbdata_regs, sbcs);
4510 for (uint32_t j = 0; j < num_sbdata_regs; j++) {
4511 if (((test_patterns[j]+i)&compare_mask) != (rd_buf[j]&compare_mask)) {
4512 LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x,"
4513 "expected val = %x, read val = %x", addr, test_patterns[j]+i, rd_buf[j]);
4514 test_passed = false;
4515 tests_failed++;
4516 }
4517 }
4518 }
4519 }
4520 if (test_passed)
4521 LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED.");
4522
4523 /* Test 2: Address autoincrement test */
4524 target_addr_t curr_addr;
4525 target_addr_t prev_addr;
4526 test_passed = true;
4527 sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 1);
4528 dmi_write(target, DM_SBCS, sbcs);
4529
4530 for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) {
4531 sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess);
4532 dmi_write(target, DM_SBCS, sbcs);
4533
4534 dmi_write(target, DM_SBADDRESS0, legal_address);
4535 read_sbcs_nonbusy(target, &sbcs);
4536 curr_addr = legal_address;
4537 for (uint32_t i = 0; i < num_words; i++) {
4538 prev_addr = curr_addr;
4539 read_sbcs_nonbusy(target, &sbcs);
4540 curr_addr = sb_read_address(target);
4541 if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
4542 LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess);
4543 test_passed = false;
4544 tests_failed++;
4545 }
4546 dmi_write(target, DM_SBDATA0, i);
4547 }
4548
4549 read_sbcs_nonbusy(target, &sbcs);
4550
4551 dmi_write(target, DM_SBADDRESS0, legal_address);
4552
4553 uint32_t val;
4554 sbcs = set_field(sbcs, DM_SBCS_SBREADONDATA, 1);
4555 dmi_write(target, DM_SBCS, sbcs);
4556 dmi_read(target, &val, DM_SBDATA0); /* Dummy read to trigger first system bus read */
4557 curr_addr = legal_address;
4558 for (uint32_t i = 0; i < num_words; i++) {
4559 prev_addr = curr_addr;
4560 read_sbcs_nonbusy(target, &sbcs);
4561 curr_addr = sb_read_address(target);
4562 if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
4563 LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
4564 test_passed = false;
4565 tests_failed++;
4566 }
4567 dmi_read(target, &val, DM_SBDATA0);
4568 read_sbcs_nonbusy(target, &sbcs);
4569 if (i != val) {
4570 LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address,"
4571 "expected val = %x, read val = %x.", i, val);
4572 test_passed = false;
4573 tests_failed++;
4574 }
4575 }
4576 }
4577 if (test_passed)
4578 LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED.");
4579
4580 /* Test 3: Read from illegal address */
4581 read_memory_sba_simple(target, illegal_address, rd_buf, 1, sbcs_orig);
4582
4583 dmi_read(target, &rd_val, DM_SBCS);
4584 if (get_field(rd_val, DM_SBCS_SBERROR) == 2) {
4585 sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2);
4586 dmi_write(target, DM_SBCS, sbcs);
4587 dmi_read(target, &rd_val, DM_SBCS);
4588 if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
4589 LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED.");
4590 else
4591 LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to clear to 0.");
4592 } else {
4593 LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to set error code.");
4594 }
4595
4596 /* Test 4: Write to illegal address */
4597 write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig);
4598
4599 dmi_read(target, &rd_val, DM_SBCS);
4600 if (get_field(rd_val, DM_SBCS_SBERROR) == 2) {
4601 sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2);
4602 dmi_write(target, DM_SBCS, sbcs);
4603 dmi_read(target, &rd_val, DM_SBCS);
4604 if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
4605 LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED.");
4606 else {
4607 LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0.");
4608 tests_failed++;
4609 }
4610 } else {
4611 LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to set error code.");
4612 tests_failed++;
4613 }
4614
4615 /* Test 5: Write with unsupported sbaccess size */
4616 uint32_t sbaccess128 = get_field(sbcs_orig, DM_SBCS_SBACCESS128);
4617
4618 if (sbaccess128) {
4619 LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported.");
4620 } else {
4621 sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 4);
4622
4623 write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs);
4624
4625 dmi_read(target, &rd_val, DM_SBCS);
4626 if (get_field(rd_val, DM_SBCS_SBERROR) == 4) {
4627 sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 4);
4628 dmi_write(target, DM_SBCS, sbcs);
4629 dmi_read(target, &rd_val, DM_SBCS);
4630 if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
4631 LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED.");
4632 else {
4633 LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0.");
4634 tests_failed++;
4635 }
4636 } else {
4637 LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code.");
4638 tests_failed++;
4639 }
4640 }
4641
4642 /* Test 6: Write to misaligned address */
4643 sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 1);
4644
4645 write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs);
4646
4647 dmi_read(target, &rd_val, DM_SBCS);
4648 if (get_field(rd_val, DM_SBCS_SBERROR) == 3) {
4649 sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 3);
4650 dmi_write(target, DM_SBCS, sbcs);
4651 dmi_read(target, &rd_val, DM_SBCS);
4652 if (get_field(rd_val, DM_SBCS_SBERROR) == 0)
4653 LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED");
4654 else {
4655 LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0.");
4656 tests_failed++;
4657 }
4658 } else {
4659 LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code.");
4660 tests_failed++;
4661 }
4662
4663 /* Test 7: Set sbbusyerror, only run this case in simulation as it is likely
4664 * impossible to hit otherwise */
4665 if (run_sbbusyerror_test) {
4666 sbcs = set_field(sbcs_orig, DM_SBCS_SBREADONADDR, 1);
4667 dmi_write(target, DM_SBCS, sbcs);
4668
4669 for (int i = 0; i < 16; i++)
4670 dmi_write(target, DM_SBDATA0, 0xdeadbeef);
4671
4672 for (int i = 0; i < 16; i++)
4673 dmi_write(target, DM_SBADDRESS0, legal_address);
4674
4675 dmi_read(target, &rd_val, DM_SBCS);
4676 if (get_field(rd_val, DM_SBCS_SBBUSYERROR)) {
4677 sbcs = set_field(sbcs_orig, DM_SBCS_SBBUSYERROR, 1);
4678 dmi_write(target, DM_SBCS, sbcs);
4679 dmi_read(target, &rd_val, DM_SBCS);
4680 if (get_field(rd_val, DM_SBCS_SBBUSYERROR) == 0)
4681 LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED.");
4682 else {
4683 LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0.");
4684 tests_failed++;
4685 }
4686 } else {
4687 LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code.");
4688 tests_failed++;
4689 }
4690 }
4691
4692 if (tests_failed == 0) {
4693 LOG_INFO("ALL TESTS PASSED");
4694 return ERROR_OK;
4695 } else {
4696 LOG_ERROR("%d TESTS FAILED", tests_failed);
4697 return ERROR_FAIL;
4698 }
4699
4700 }
4701
4702 void write_memory_sba_simple(struct target *target, target_addr_t addr,
4703 uint32_t *write_data, uint32_t write_size, uint32_t sbcs)
4704 {
4705 RISCV013_INFO(info);
4706
4707 uint32_t rd_sbcs;
4708 uint32_t masked_addr;
4709
4710 uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE);
4711
4712 read_sbcs_nonbusy(target, &rd_sbcs);
4713
4714 uint32_t sbcs_no_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 0);
4715 dmi_write(target, DM_SBCS, sbcs_no_readonaddr);
4716
4717 for (uint32_t i = 0; i < sba_size/32; i++) {
4718 masked_addr = (addr >> 32*i) & 0xffffffff;
4719
4720 if (i != 3)
4721 dmi_write(target, DM_SBADDRESS0+i, masked_addr);
4722 else
4723 dmi_write(target, DM_SBADDRESS3, masked_addr);
4724 }
4725
4726 /* Write SBDATA registers starting with highest address, since write to
4727 * SBDATA0 triggers write */
4728 for (int i = write_size-1; i >= 0; i--)
4729 dmi_write(target, DM_SBDATA0+i, write_data[i]);
4730 }
4731
4732 void read_memory_sba_simple(struct target *target, target_addr_t addr,
4733 uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs)
4734 {
4735 RISCV013_INFO(info);
4736
4737 uint32_t rd_sbcs;
4738 uint32_t masked_addr;
4739
4740 uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE);
4741
4742 read_sbcs_nonbusy(target, &rd_sbcs);
4743
4744 uint32_t sbcs_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 1);
4745 dmi_write(target, DM_SBCS, sbcs_readonaddr);
4746
4747 /* Write addresses starting with highest address register */
4748 for (int i = sba_size/32-1; i >= 0; i--) {
4749 masked_addr = (addr >> 32*i) & 0xffffffff;
4750
4751 if (i != 3)
4752 dmi_write(target, DM_SBADDRESS0+i, masked_addr);
4753 else
4754 dmi_write(target, DM_SBADDRESS3, masked_addr);
4755 }
4756
4757 read_sbcs_nonbusy(target, &rd_sbcs);
4758
4759 for (uint32_t i = 0; i < read_size; i++)
4760 dmi_read(target, &(rd_buf[i]), DM_SBDATA0+i);
4761 }
4762
4763 int riscv013_dmi_write_u64_bits(struct target *target)
4764 {
4765 RISCV013_INFO(info);
4766 return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH;
4767 }
4768
4769 static int maybe_execute_fence_i(struct target *target)
4770 {
4771 if (has_sufficient_progbuf(target, 3))
4772 return execute_fence(target);
4773 return ERROR_OK;
4774 }
4775
4776 /* Helper Functions. */
4777 static int riscv013_on_step_or_resume(struct target *target, bool step)
4778 {
4779 if (maybe_execute_fence_i(target) != ERROR_OK)
4780 return ERROR_FAIL;
4781
4782 /* We want to twiddle some bits in the debug CSR so debugging works. */
4783 riscv_reg_t dcsr;
4784 int result = register_read(target, &dcsr, GDB_REGNO_DCSR);
4785 if (result != ERROR_OK)
4786 return result;
4787 dcsr = set_field(dcsr, CSR_DCSR_STEP, step);
4788 dcsr = set_field(dcsr, CSR_DCSR_EBREAKM, riscv_ebreakm);
4789 dcsr = set_field(dcsr, CSR_DCSR_EBREAKS, riscv_ebreaks);
4790 dcsr = set_field(dcsr, CSR_DCSR_EBREAKU, riscv_ebreaku);
4791 return riscv_set_register(target, GDB_REGNO_DCSR, dcsr);
4792 }
4793
4794 static int riscv013_step_or_resume_current_hart(struct target *target,
4795 bool step, bool use_hasel)
4796 {
4797 RISCV_INFO(r);
4798 LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
4799 if (!riscv_is_halted(target)) {
4800 LOG_ERROR("Hart %d is not halted!", r->current_hartid);
4801 return ERROR_FAIL;
4802 }
4803
4804 /* Issue the resume command, and then wait for the current hart to resume. */
4805 uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_RESUMEREQ;
4806 if (use_hasel)
4807 dmcontrol |= DM_DMCONTROL_HASEL;
4808 dmcontrol = set_hartsel(dmcontrol, r->current_hartid);
4809 dmi_write(target, DM_DMCONTROL, dmcontrol);
4810
4811 dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HASEL, 0);
4812 dmcontrol = set_field(dmcontrol, DM_DMCONTROL_RESUMEREQ, 0);
4813
4814 uint32_t dmstatus;
4815 for (size_t i = 0; i < 256; ++i) {
4816 usleep(10);
4817 if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
4818 return ERROR_FAIL;
4819 if (get_field(dmstatus, DM_DMSTATUS_ALLRESUMEACK) == 0)
4820 continue;
4821 if (step && get_field(dmstatus, DM_DMSTATUS_ALLHALTED) == 0)
4822 continue;
4823
4824 dmi_write(target, DM_DMCONTROL, dmcontrol);
4825 return ERROR_OK;
4826 }
4827
4828 dmi_write(target, DM_DMCONTROL, dmcontrol);
4829
4830 LOG_ERROR("unable to resume hart %d", r->current_hartid);
4831 if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
4832 return ERROR_FAIL;
4833 LOG_ERROR(" dmstatus =0x%08x", dmstatus);
4834
4835 if (step) {
4836 LOG_ERROR(" was stepping, halting");
4837 riscv_halt(target);
4838 return ERROR_OK;
4839 }
4840
4841 return ERROR_FAIL;
4842 }
4843
4844 void riscv013_clear_abstract_error(struct target *target)
4845 {
4846 /* Wait for busy to go away. */
4847 time_t start = time(NULL);
4848 uint32_t abstractcs;
4849 dmi_read(target, &abstractcs, DM_ABSTRACTCS);
4850 while (get_field(abstractcs, DM_ABSTRACTCS_BUSY)) {
4851 dmi_read(target, &abstractcs, DM_ABSTRACTCS);
4852
4853 if (time(NULL) - start > riscv_command_timeout_sec) {
4854 LOG_ERROR("abstractcs.busy is not going low after %d seconds "
4855 "(abstractcs=0x%x). The target is either really slow or "
4856 "broken. You could increase the timeout with riscv "
4857 "set_command_timeout_sec.",
4858 riscv_command_timeout_sec, abstractcs);
4859 break;
4860 }
4861 }
4862 /* Clear the error status. */
4863 dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR);
4864 }
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