1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <helper/log.h>
12 #include <helper/time_support.h>
13 #include "target/target.h"
14 #include "target/algorithm.h"
15 #include "target/target_type.h"
16 #include "jtag/jtag.h"
17 #include "target/register.h"
18 #include "target/breakpoints.h"
21 #include "rtos/rtos.h"
22 #include "debug_defines.h"
23 #include <helper/bits.h>
25 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
26 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
28 /* Constants for legacy SiFive hardware breakpoints. */
29 #define CSR_BPCONTROL_X (1<<0)
30 #define CSR_BPCONTROL_W (1<<1)
31 #define CSR_BPCONTROL_R (1<<2)
32 #define CSR_BPCONTROL_U (1<<3)
33 #define CSR_BPCONTROL_S (1<<4)
34 #define CSR_BPCONTROL_H (1<<5)
35 #define CSR_BPCONTROL_M (1<<6)
36 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
37 #define CSR_BPCONTROL_BPACTION (0xff<<11)
39 #define DEBUG_ROM_START 0x800
40 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
41 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
42 #define DEBUG_RAM_START 0x400
44 #define SETHALTNOT 0x10c
46 /*** JTAG registers. ***/
48 #define DTMCONTROL 0x10
49 #define DTMCONTROL_DBUS_RESET (1<<16)
50 #define DTMCONTROL_IDLE (7<<10)
51 #define DTMCONTROL_ADDRBITS (0xf<<4)
52 #define DTMCONTROL_VERSION (0xf)
55 #define DBUS_OP_START 0
56 #define DBUS_OP_SIZE 2
63 DBUS_STATUS_SUCCESS
= 0,
64 DBUS_STATUS_FAILED
= 2,
67 #define DBUS_DATA_START 2
68 #define DBUS_DATA_SIZE 34
69 #define DBUS_ADDRESS_START 36
77 /*** Debug Bus registers. ***/
79 #define DMCONTROL 0x10
80 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
81 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
82 #define DMCONTROL_BUSERROR (7<<19)
83 #define DMCONTROL_SERIAL (3<<16)
84 #define DMCONTROL_AUTOINCREMENT (1<<15)
85 #define DMCONTROL_ACCESS (7<<12)
86 #define DMCONTROL_HARTID (0x3ff<<2)
87 #define DMCONTROL_NDRESET (1<<1)
88 #define DMCONTROL_FULLRESET 1
91 #define DMINFO_ABUSSIZE (0x7fU<<25)
92 #define DMINFO_SERIALCOUNT (0xf<<21)
93 #define DMINFO_ACCESS128 (1<<20)
94 #define DMINFO_ACCESS64 (1<<19)
95 #define DMINFO_ACCESS32 (1<<18)
96 #define DMINFO_ACCESS16 (1<<17)
97 #define DMINFO_ACCESS8 (1<<16)
98 #define DMINFO_DRAMSIZE (0x3f<<10)
99 #define DMINFO_AUTHENTICATED (1<<5)
100 #define DMINFO_AUTHBUSY (1<<4)
101 #define DMINFO_AUTHTYPE (3<<2)
102 #define DMINFO_VERSION 3
104 /*** Info about the core being debugged. ***/
106 #define DBUS_ADDRESS_UNKNOWN 0xffff
109 #define DRAM_CACHE_SIZE 16
111 uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
112 struct scan_field select_dtmcontrol
= {
114 .out_value
= ir_dtmcontrol
116 uint8_t ir_dbus
[4] = {DBUS
};
117 struct scan_field select_dbus
= {
121 uint8_t ir_idcode
[4] = {0x1};
122 struct scan_field select_idcode
= {
124 .out_value
= ir_idcode
127 bscan_tunnel_type_t bscan_tunnel_type
;
128 int bscan_tunnel_ir_width
; /* if zero, then tunneling is not present/active */
130 static const uint8_t bscan_zero
[4] = {0};
131 static const uint8_t bscan_one
[4] = {1};
134 struct scan_field select_user4
= {
136 .out_value
= ir_user4
140 uint8_t bscan_tunneled_ir_width
[4] = {5}; /* overridden by assignment in riscv_init_target */
141 struct scan_field _bscan_tunnel_data_register_select_dmi
[] = {
144 .out_value
= bscan_zero
,
148 .num_bits
= 5, /* initialized in riscv_init_target to ir width of DM */
149 .out_value
= ir_dbus
,
154 .out_value
= bscan_tunneled_ir_width
,
159 .out_value
= bscan_zero
,
164 struct scan_field _bscan_tunnel_nested_tap_select_dmi
[] = {
167 .out_value
= bscan_zero
,
172 .out_value
= bscan_tunneled_ir_width
,
176 .num_bits
= 0, /* initialized in riscv_init_target to ir width of DM */
177 .out_value
= ir_dbus
,
182 .out_value
= bscan_zero
,
186 struct scan_field
*bscan_tunnel_nested_tap_select_dmi
= _bscan_tunnel_nested_tap_select_dmi
;
187 uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi
);
189 struct scan_field
*bscan_tunnel_data_register_select_dmi
= _bscan_tunnel_data_register_select_dmi
;
190 uint32_t bscan_tunnel_data_register_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi
);
197 bool read
, write
, execute
;
201 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
202 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
204 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
205 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
207 bool riscv_enable_virt2phys
= true;
208 bool riscv_ebreakm
= true;
209 bool riscv_ebreaks
= true;
210 bool riscv_ebreaku
= true;
212 bool riscv_enable_virtual
;
219 const virt2phys_info_t sv32
= {
224 .vpn_shift
= {12, 22},
225 .vpn_mask
= {0x3ff, 0x3ff},
226 .pte_ppn_shift
= {10, 20},
227 .pte_ppn_mask
= {0x3ff, 0xfff},
228 .pa_ppn_shift
= {12, 22},
229 .pa_ppn_mask
= {0x3ff, 0xfff},
232 const virt2phys_info_t sv39
= {
237 .vpn_shift
= {12, 21, 30},
238 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff},
239 .pte_ppn_shift
= {10, 19, 28},
240 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
241 .pa_ppn_shift
= {12, 21, 30},
242 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
245 const virt2phys_info_t sv48
= {
250 .vpn_shift
= {12, 21, 30, 39},
251 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ff},
252 .pte_ppn_shift
= {10, 19, 28, 37},
253 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
254 .pa_ppn_shift
= {12, 21, 30, 39},
255 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
258 void riscv_sample_buf_maybe_add_timestamp(struct target
*target
, bool before
)
261 uint32_t now
= timeval_ms() & 0xffffffff;
262 if (r
->sample_buf
.used
+ 5 < r
->sample_buf
.size
) {
264 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE
;
266 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER
;
267 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = now
& 0xff;
268 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 8) & 0xff;
269 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 16) & 0xff;
270 r
->sample_buf
.buf
[r
->sample_buf
.used
++] = (now
>> 24) & 0xff;
274 static int riscv_resume_go_all_harts(struct target
*target
);
276 void select_dmi_via_bscan(struct target
*target
)
278 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
279 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
280 jtag_add_dr_scan(target
->tap
, bscan_tunnel_data_register_select_dmi_num_fields
,
281 bscan_tunnel_data_register_select_dmi
, TAP_IDLE
);
282 else /* BSCAN_TUNNEL_NESTED_TAP */
283 jtag_add_dr_scan(target
->tap
, bscan_tunnel_nested_tap_select_dmi_num_fields
,
284 bscan_tunnel_nested_tap_select_dmi
, TAP_IDLE
);
287 uint32_t dtmcontrol_scan_via_bscan(struct target
*target
, uint32_t out
)
289 /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
290 uint8_t tunneled_ir_width
[4] = {bscan_tunnel_ir_width
};
291 uint8_t tunneled_dr_width
[4] = {32};
292 uint8_t out_value
[5] = {0};
293 uint8_t in_value
[5] = {0};
295 buf_set_u32(out_value
, 0, 32, out
);
296 struct scan_field tunneled_ir
[4] = {};
297 struct scan_field tunneled_dr
[4] = {};
299 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
300 tunneled_ir
[0].num_bits
= 3;
301 tunneled_ir
[0].out_value
= bscan_zero
;
302 tunneled_ir
[0].in_value
= NULL
;
303 tunneled_ir
[1].num_bits
= bscan_tunnel_ir_width
;
304 tunneled_ir
[1].out_value
= ir_dtmcontrol
;
305 tunneled_ir
[1].in_value
= NULL
;
306 tunneled_ir
[2].num_bits
= 7;
307 tunneled_ir
[2].out_value
= tunneled_ir_width
;
308 tunneled_ir
[2].in_value
= NULL
;
309 tunneled_ir
[3].num_bits
= 1;
310 tunneled_ir
[3].out_value
= bscan_zero
;
311 tunneled_ir
[3].in_value
= NULL
;
313 tunneled_dr
[0].num_bits
= 3;
314 tunneled_dr
[0].out_value
= bscan_zero
;
315 tunneled_dr
[0].in_value
= NULL
;
316 tunneled_dr
[1].num_bits
= 32 + 1;
317 tunneled_dr
[1].out_value
= out_value
;
318 tunneled_dr
[1].in_value
= in_value
;
319 tunneled_dr
[2].num_bits
= 7;
320 tunneled_dr
[2].out_value
= tunneled_dr_width
;
321 tunneled_dr
[2].in_value
= NULL
;
322 tunneled_dr
[3].num_bits
= 1;
323 tunneled_dr
[3].out_value
= bscan_one
;
324 tunneled_dr
[3].in_value
= NULL
;
326 /* BSCAN_TUNNEL_NESTED_TAP */
327 tunneled_ir
[3].num_bits
= 3;
328 tunneled_ir
[3].out_value
= bscan_zero
;
329 tunneled_ir
[3].in_value
= NULL
;
330 tunneled_ir
[2].num_bits
= bscan_tunnel_ir_width
;
331 tunneled_ir
[2].out_value
= ir_dtmcontrol
;
332 tunneled_ir
[1].in_value
= NULL
;
333 tunneled_ir
[1].num_bits
= 7;
334 tunneled_ir
[1].out_value
= tunneled_ir_width
;
335 tunneled_ir
[2].in_value
= NULL
;
336 tunneled_ir
[0].num_bits
= 1;
337 tunneled_ir
[0].out_value
= bscan_zero
;
338 tunneled_ir
[0].in_value
= NULL
;
340 tunneled_dr
[3].num_bits
= 3;
341 tunneled_dr
[3].out_value
= bscan_zero
;
342 tunneled_dr
[3].in_value
= NULL
;
343 tunneled_dr
[2].num_bits
= 32 + 1;
344 tunneled_dr
[2].out_value
= out_value
;
345 tunneled_dr
[2].in_value
= in_value
;
346 tunneled_dr
[1].num_bits
= 7;
347 tunneled_dr
[1].out_value
= tunneled_dr_width
;
348 tunneled_dr
[1].in_value
= NULL
;
349 tunneled_dr
[0].num_bits
= 1;
350 tunneled_dr
[0].out_value
= bscan_one
;
351 tunneled_dr
[0].in_value
= NULL
;
353 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
354 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_ir
), tunneled_ir
, TAP_IDLE
);
355 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_dr
), tunneled_dr
, TAP_IDLE
);
356 select_dmi_via_bscan(target
);
358 int retval
= jtag_execute_queue();
359 if (retval
!= ERROR_OK
) {
360 LOG_ERROR("failed jtag scan: %d", retval
);
363 /* Note the starting offset is bit 1, not bit 0. In BSCAN tunnel, there is a one-bit TCK skew between
365 uint32_t in
= buf_get_u32(in_value
, 1, 32);
366 LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out
, in
);
371 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
373 struct scan_field field
;
375 uint8_t out_value
[4] = { 0 };
377 if (bscan_tunnel_ir_width
!= 0)
378 return dtmcontrol_scan_via_bscan(target
, out
);
381 buf_set_u32(out_value
, 0, 32, out
);
383 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
386 field
.out_value
= out_value
;
387 field
.in_value
= in_value
;
388 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
390 /* Always return to dbus. */
391 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
393 int retval
= jtag_execute_queue();
394 if (retval
!= ERROR_OK
) {
395 LOG_ERROR("failed jtag scan: %d", retval
);
399 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
400 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
405 static struct target_type
*get_target_type(struct target
*target
)
407 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
410 LOG_ERROR("Target has not been initialized");
414 switch (info
->dtm_version
) {
416 return &riscv011_target
;
418 return &riscv013_target
;
420 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
425 static int riscv_create_target(struct target
*target
, Jim_Interp
*interp
)
427 LOG_DEBUG("riscv_create_target()");
428 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
429 if (!target
->arch_info
) {
430 LOG_ERROR("Failed to allocate RISC-V target structure.");
433 riscv_info_init(target
, target
->arch_info
);
437 static int riscv_init_target(struct command_context
*cmd_ctx
,
438 struct target
*target
)
440 LOG_DEBUG("riscv_init_target()");
442 info
->cmd_ctx
= cmd_ctx
;
444 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
445 select_dbus
.num_bits
= target
->tap
->ir_length
;
446 select_idcode
.num_bits
= target
->tap
->ir_length
;
448 if (bscan_tunnel_ir_width
!= 0) {
449 assert(target
->tap
->ir_length
>= 6);
450 uint32_t ir_user4_raw
= 0x23 << (target
->tap
->ir_length
- 6);
451 ir_user4
[0] = (uint8_t)ir_user4_raw
;
452 ir_user4
[1] = (uint8_t)(ir_user4_raw
>>= 8);
453 ir_user4
[2] = (uint8_t)(ir_user4_raw
>>= 8);
454 ir_user4
[3] = (uint8_t)(ir_user4_raw
>>= 8);
455 select_user4
.num_bits
= target
->tap
->ir_length
;
456 bscan_tunneled_ir_width
[0] = bscan_tunnel_ir_width
;
457 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
458 bscan_tunnel_data_register_select_dmi
[1].num_bits
= bscan_tunnel_ir_width
;
459 else /* BSCAN_TUNNEL_NESTED_TAP */
460 bscan_tunnel_nested_tap_select_dmi
[2].num_bits
= bscan_tunnel_ir_width
;
463 riscv_semihosting_init(target
);
465 target
->debug_reason
= DBG_REASON_DBGRQ
;
470 static void riscv_free_registers(struct target
*target
)
472 /* Free the shared structure use for most registers. */
473 if (target
->reg_cache
) {
474 if (target
->reg_cache
->reg_list
) {
475 free(target
->reg_cache
->reg_list
[0].arch_info
);
476 /* Free the ones we allocated separately. */
477 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
478 free(target
->reg_cache
->reg_list
[i
].arch_info
);
479 for (unsigned int i
= 0; i
< target
->reg_cache
->num_regs
; i
++)
480 free(target
->reg_cache
->reg_list
[i
].value
);
481 free(target
->reg_cache
->reg_list
);
483 free(target
->reg_cache
);
487 static void riscv_deinit_target(struct target
*target
)
489 LOG_DEBUG("riscv_deinit_target()");
491 riscv_info_t
*info
= target
->arch_info
;
492 struct target_type
*tt
= get_target_type(target
);
494 if (tt
&& info
->version_specific
)
495 tt
->deinit_target(target
);
497 riscv_free_registers(target
);
499 range_list_t
*entry
, *tmp
;
500 list_for_each_entry_safe(entry
, tmp
, &info
->expose_csr
, list
) {
505 list_for_each_entry_safe(entry
, tmp
, &info
->expose_custom
, list
) {
510 free(info
->reg_names
);
511 free(target
->arch_info
);
513 target
->arch_info
= NULL
;
516 static void trigger_from_breakpoint(struct trigger
*trigger
,
517 const struct breakpoint
*breakpoint
)
519 trigger
->address
= breakpoint
->address
;
520 trigger
->length
= breakpoint
->length
;
521 trigger
->mask
= ~0LL;
522 trigger
->read
= false;
523 trigger
->write
= false;
524 trigger
->execute
= true;
525 /* unique_id is unique across both breakpoints and watchpoints. */
526 trigger
->unique_id
= breakpoint
->unique_id
;
529 static int maybe_add_trigger_t1(struct target
*target
,
530 struct trigger
*trigger
, uint64_t tdata1
)
534 const uint32_t bpcontrol_x
= 1<<0;
535 const uint32_t bpcontrol_w
= 1<<1;
536 const uint32_t bpcontrol_r
= 1<<2;
537 const uint32_t bpcontrol_u
= 1<<3;
538 const uint32_t bpcontrol_s
= 1<<4;
539 const uint32_t bpcontrol_h
= 1<<5;
540 const uint32_t bpcontrol_m
= 1<<6;
541 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
542 const uint32_t bpcontrol_bpaction
= 0xff << 11;
544 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
545 /* Trigger is already in use, presumably by user code. */
546 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
549 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
550 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
551 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
552 tdata1
= set_field(tdata1
, bpcontrol_u
,
553 !!(r
->misa
& BIT('U' - 'A')));
554 tdata1
= set_field(tdata1
, bpcontrol_s
,
555 !!(r
->misa
& BIT('S' - 'A')));
556 tdata1
= set_field(tdata1
, bpcontrol_h
,
557 !!(r
->misa
& BIT('H' - 'A')));
558 tdata1
|= bpcontrol_m
;
559 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
560 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
562 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
564 riscv_reg_t tdata1_rb
;
565 if (riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
) != ERROR_OK
)
567 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
569 if (tdata1
!= tdata1_rb
) {
570 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
571 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
573 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
574 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
577 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
582 static int maybe_add_trigger_t2(struct target
*target
,
583 struct trigger
*trigger
, uint64_t tdata1
)
587 /* tselect is already set */
588 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
589 /* Trigger is already in use, presumably by user code. */
590 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
593 /* address/data match trigger */
594 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
595 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
596 MCONTROL_ACTION_DEBUG_MODE
);
597 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
598 tdata1
|= MCONTROL_M
;
599 if (r
->misa
& (1 << ('S' - 'A')))
600 tdata1
|= MCONTROL_S
;
601 if (r
->misa
& (1 << ('U' - 'A')))
602 tdata1
|= MCONTROL_U
;
604 if (trigger
->execute
)
605 tdata1
|= MCONTROL_EXECUTE
;
607 tdata1
|= MCONTROL_LOAD
;
609 tdata1
|= MCONTROL_STORE
;
611 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
614 int result
= riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
);
615 if (result
!= ERROR_OK
)
617 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
619 if (tdata1
!= tdata1_rb
) {
620 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
621 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
623 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
624 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
627 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
632 static int maybe_add_trigger_t6(struct target
*target
,
633 struct trigger
*trigger
, uint64_t tdata1
)
637 /* tselect is already set */
638 if (tdata1
& (CSR_MCONTROL6_EXECUTE
| CSR_MCONTROL6_STORE
| CSR_MCONTROL6_LOAD
)) {
639 /* Trigger is already in use, presumably by user code. */
640 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
643 /* address/data match trigger */
644 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
645 tdata1
= set_field(tdata1
, CSR_MCONTROL6_ACTION
,
646 MCONTROL_ACTION_DEBUG_MODE
);
647 tdata1
= set_field(tdata1
, CSR_MCONTROL6_MATCH
, MCONTROL_MATCH_EQUAL
);
648 tdata1
|= CSR_MCONTROL6_M
;
649 if (r
->misa
& (1 << ('H' - 'A')))
650 tdata1
|= CSR_MCONTROL6_VS
| CSR_MCONTROL6_VU
;
651 if (r
->misa
& (1 << ('S' - 'A')))
652 tdata1
|= CSR_MCONTROL6_S
;
653 if (r
->misa
& (1 << ('U' - 'A')))
654 tdata1
|= CSR_MCONTROL6_U
;
656 if (trigger
->execute
)
657 tdata1
|= CSR_MCONTROL6_EXECUTE
;
659 tdata1
|= CSR_MCONTROL6_LOAD
;
661 tdata1
|= CSR_MCONTROL6_STORE
;
663 riscv_set_register(target
, GDB_REGNO_TDATA1
, tdata1
);
666 int result
= riscv_get_register(target
, &tdata1_rb
, GDB_REGNO_TDATA1
);
667 if (result
!= ERROR_OK
)
669 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
671 if (tdata1
!= tdata1_rb
) {
672 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
673 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
675 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
676 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
679 riscv_set_register(target
, GDB_REGNO_TDATA2
, trigger
->address
);
684 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
688 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
692 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
696 for (i
= 0; i
< r
->trigger_count
; i
++) {
697 if (r
->trigger_unique_id
[i
] != -1)
700 riscv_set_register(target
, GDB_REGNO_TSELECT
, i
);
703 int result
= riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
);
704 if (result
!= ERROR_OK
)
706 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
711 result
= maybe_add_trigger_t1(target
, trigger
, tdata1
);
714 result
= maybe_add_trigger_t2(target
, trigger
, tdata1
);
717 result
= maybe_add_trigger_t6(target
, trigger
, tdata1
);
720 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
724 if (result
!= ERROR_OK
)
727 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
728 i
, type
, trigger
->unique_id
);
729 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
733 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
735 if (i
>= r
->trigger_count
) {
736 LOG_ERROR("Couldn't find an available hardware trigger.");
737 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
744 * Write one memory item of given "size". Use memory access of given "access_size".
745 * Utilize read-modify-write, if needed.
747 static int write_by_given_size(struct target
*target
, target_addr_t address
,
748 uint32_t size
, uint8_t *buffer
, uint32_t access_size
)
750 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
751 assert(access_size
== 1 || access_size
== 2 || access_size
== 4 || access_size
== 8);
753 if (access_size
<= size
&& address
% access_size
== 0)
754 /* Can do the memory access directly without a helper buffer. */
755 return target_write_memory(target
, address
, access_size
, size
/ access_size
, buffer
);
757 unsigned int offset_head
= address
% access_size
;
758 unsigned int n_blocks
= ((size
+ offset_head
) <= access_size
) ? 1 : 2;
759 uint8_t helper_buf
[n_blocks
* access_size
];
761 /* Read from memory */
762 if (target_read_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
) != ERROR_OK
)
765 /* Modify and write back */
766 memcpy(helper_buf
+ offset_head
, buffer
, size
);
767 return target_write_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
);
771 * Read one memory item of given "size". Use memory access of given "access_size".
772 * Read larger section of memory and pick out the required portion, if needed.
774 static int read_by_given_size(struct target
*target
, target_addr_t address
,
775 uint32_t size
, uint8_t *buffer
, uint32_t access_size
)
777 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
778 assert(access_size
== 1 || access_size
== 2 || access_size
== 4 || access_size
== 8);
780 if (access_size
<= size
&& address
% access_size
== 0)
781 /* Can do the memory access directly without a helper buffer. */
782 return target_read_memory(target
, address
, access_size
, size
/ access_size
, buffer
);
784 unsigned int offset_head
= address
% access_size
;
785 unsigned int n_blocks
= ((size
+ offset_head
) <= access_size
) ? 1 : 2;
786 uint8_t helper_buf
[n_blocks
* access_size
];
788 /* Read from memory */
789 if (target_read_memory(target
, address
- offset_head
, access_size
, n_blocks
, helper_buf
) != ERROR_OK
)
792 /* Pick the requested portion from the buffer */
793 memcpy(buffer
, helper_buf
+ offset_head
, size
);
798 * Write one memory item using any memory access size that will work.
799 * Utilize read-modify-write, if needed.
801 int riscv_write_by_any_size(struct target
*target
, target_addr_t address
, uint32_t size
, uint8_t *buffer
)
803 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
805 /* Find access size that correspond to data size and the alignment. */
806 unsigned int preferred_size
= size
;
807 while (address
% preferred_size
!= 0)
810 /* First try the preferred (most natural) access size. */
811 if (write_by_given_size(target
, address
, size
, buffer
, preferred_size
) == ERROR_OK
)
814 /* On failure, try other access sizes.
815 Minimize the number of accesses by trying first the largest size. */
816 for (unsigned int access_size
= 8; access_size
> 0; access_size
/= 2) {
817 if (access_size
== preferred_size
)
818 /* Already tried this size. */
821 if (write_by_given_size(target
, address
, size
, buffer
, access_size
) == ERROR_OK
)
825 /* No access attempt succeeded. */
830 * Read one memory item using any memory access size that will work.
831 * Read larger section of memory and pick out the required portion, if needed.
833 int riscv_read_by_any_size(struct target
*target
, target_addr_t address
, uint32_t size
, uint8_t *buffer
)
835 assert(size
== 1 || size
== 2 || size
== 4 || size
== 8);
837 /* Find access size that correspond to data size and the alignment. */
838 unsigned int preferred_size
= size
;
839 while (address
% preferred_size
!= 0)
842 /* First try the preferred (most natural) access size. */
843 if (read_by_given_size(target
, address
, size
, buffer
, preferred_size
) == ERROR_OK
)
846 /* On failure, try other access sizes.
847 Minimize the number of accesses by trying first the largest size. */
848 for (unsigned int access_size
= 8; access_size
> 0; access_size
/= 2) {
849 if (access_size
== preferred_size
)
850 /* Already tried this size. */
853 if (read_by_given_size(target
, address
, size
, buffer
, access_size
) == ERROR_OK
)
857 /* No access attempt succeeded. */
861 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
863 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
865 if (breakpoint
->type
== BKPT_SOFT
) {
866 /** @todo check RVC for size/alignment */
867 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
868 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
872 if (0 != (breakpoint
->address
% 2)) {
873 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
877 /* Read the original instruction. */
878 if (riscv_read_by_any_size(
879 target
, breakpoint
->address
, breakpoint
->length
, breakpoint
->orig_instr
) != ERROR_OK
) {
880 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
881 breakpoint
->address
);
885 uint8_t buff
[4] = { 0 };
886 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
887 /* Write the ebreak instruction. */
888 if (riscv_write_by_any_size(target
, breakpoint
->address
, breakpoint
->length
, buff
) != ERROR_OK
) {
889 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
890 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
894 } else if (breakpoint
->type
== BKPT_HARD
) {
895 struct trigger trigger
;
896 trigger_from_breakpoint(&trigger
, breakpoint
);
897 int const result
= add_trigger(target
, &trigger
);
898 if (result
!= ERROR_OK
)
901 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
902 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
905 breakpoint
->set
= true;
909 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
913 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
917 for (i
= 0; i
< r
->trigger_count
; i
++) {
918 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
921 if (i
>= r
->trigger_count
) {
922 LOG_ERROR("Couldn't find the hardware resources used by hardware "
926 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
930 int result
= riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
);
931 if (result
!= ERROR_OK
)
933 riscv_set_register(target
, GDB_REGNO_TSELECT
, i
);
934 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
935 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
936 r
->trigger_unique_id
[i
] = -1;
941 int riscv_remove_breakpoint(struct target
*target
,
942 struct breakpoint
*breakpoint
)
944 if (breakpoint
->type
== BKPT_SOFT
) {
945 /* Write the original instruction. */
946 if (riscv_write_by_any_size(
947 target
, breakpoint
->address
, breakpoint
->length
, breakpoint
->orig_instr
) != ERROR_OK
) {
948 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
949 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
953 } else if (breakpoint
->type
== BKPT_HARD
) {
954 struct trigger trigger
;
955 trigger_from_breakpoint(&trigger
, breakpoint
);
956 int result
= remove_trigger(target
, &trigger
);
957 if (result
!= ERROR_OK
)
961 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
962 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
965 breakpoint
->set
= false;
970 static void trigger_from_watchpoint(struct trigger
*trigger
,
971 const struct watchpoint
*watchpoint
)
973 trigger
->address
= watchpoint
->address
;
974 trigger
->length
= watchpoint
->length
;
975 trigger
->mask
= watchpoint
->mask
;
976 trigger
->value
= watchpoint
->value
;
977 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
978 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
979 trigger
->execute
= false;
980 /* unique_id is unique across both breakpoints and watchpoints. */
981 trigger
->unique_id
= watchpoint
->unique_id
;
984 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
986 struct trigger trigger
;
987 trigger_from_watchpoint(&trigger
, watchpoint
);
989 int result
= add_trigger(target
, &trigger
);
990 if (result
!= ERROR_OK
)
992 watchpoint
->set
= true;
997 int riscv_remove_watchpoint(struct target
*target
,
998 struct watchpoint
*watchpoint
)
1000 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
1002 struct trigger trigger
;
1003 trigger_from_watchpoint(&trigger
, watchpoint
);
1005 int result
= remove_trigger(target
, &trigger
);
1006 if (result
!= ERROR_OK
)
1008 watchpoint
->set
= false;
1013 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1016 * The GDB server uses this information to tell GDB what data address has
1017 * been hit, which enables GDB to print the hit variable along with its old
1019 int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
1021 struct watchpoint
*wp
= target
->watchpoints
;
1023 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
1025 /*TODO instead of disassembling the instruction that we think caused the
1026 * trigger, check the hit bit of each watchpoint first. The hit bit is
1027 * simpler and more reliable to check but as it is optional and relatively
1028 * new, not all hardware will implement it */
1030 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
1031 const uint8_t length
= 4;
1032 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
1034 /* fetch the instruction at dpc */
1035 uint8_t buffer
[length
];
1036 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
1037 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
1041 uint32_t instruction
= 0;
1043 for (int i
= 0; i
< length
; i
++) {
1044 LOG_DEBUG("Next byte is %x", buffer
[i
]);
1045 instruction
+= (buffer
[i
] << 8 * i
);
1047 LOG_DEBUG("Full instruction is %x", instruction
);
1049 /* find out which memory address is accessed by the instruction at dpc */
1050 /* opcode is first 7 bits of the instruction */
1051 uint8_t opcode
= instruction
& 0x7F;
1054 riscv_reg_t mem_addr
;
1056 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
1057 rs1
= (instruction
& 0xf8000) >> 15;
1058 riscv_get_register(target
, &mem_addr
, rs1
);
1060 if (opcode
== MATCH_SB
) {
1061 LOG_DEBUG("%x is store instruction", instruction
);
1062 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
1064 LOG_DEBUG("%x is load instruction", instruction
);
1065 imm
= (instruction
& 0xfff00000) >> 20;
1067 /* sign extend 12-bit imm to 16-bits */
1068 if (imm
& (1 << 11))
1071 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
1073 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
1078 /*TODO support length/mask */
1079 if (wp
->address
== mem_addr
) {
1080 *hit_watchpoint
= wp
;
1081 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
1087 /* No match found - either we hit a watchpoint caused by an instruction that
1088 * this function does not yet disassemble, or we hit a breakpoint.
1090 * OpenOCD will behave as if this function had never been implemented i.e.
1091 * report the halt to GDB with no address information. */
1096 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
1097 int handle_breakpoints
)
1099 struct target_type
*tt
= get_target_type(target
);
1100 return tt
->step(target
, current
, address
, handle_breakpoints
);
1103 static int old_or_new_riscv_step(struct target
*target
, int current
,
1104 target_addr_t address
, int handle_breakpoints
)
1107 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
1109 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
1111 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
1115 static int riscv_examine(struct target
*target
)
1117 LOG_DEBUG("riscv_examine()");
1118 if (target_was_examined(target
)) {
1119 LOG_DEBUG("Target was already examined.");
1123 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1126 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
1127 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
1128 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
1129 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
1131 struct target_type
*tt
= get_target_type(target
);
1135 int result
= tt
->init_target(info
->cmd_ctx
, target
);
1136 if (result
!= ERROR_OK
)
1139 return tt
->examine(target
);
1142 static int oldriscv_poll(struct target
*target
)
1144 struct target_type
*tt
= get_target_type(target
);
1145 return tt
->poll(target
);
1148 static int old_or_new_riscv_poll(struct target
*target
)
1152 return oldriscv_poll(target
);
1154 return riscv_openocd_poll(target
);
1157 int riscv_select_current_hart(struct target
*target
)
1159 return riscv_set_current_hartid(target
, target
->coreid
);
1162 int halt_prep(struct target
*target
)
1166 LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target
),
1167 target
->debug_reason
);
1168 if (riscv_select_current_hart(target
) != ERROR_OK
)
1170 if (riscv_is_halted(target
)) {
1171 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1172 target_name(target
), target
->debug_reason
);
1174 if (r
->halt_prep(target
) != ERROR_OK
)
1182 int riscv_halt_go_all_harts(struct target
*target
)
1186 if (riscv_select_current_hart(target
) != ERROR_OK
)
1188 if (riscv_is_halted(target
)) {
1189 LOG_DEBUG("[%s] Hart is already halted.", target_name(target
));
1191 if (r
->halt_go(target
) != ERROR_OK
)
1195 riscv_invalidate_register_cache(target
);
1200 int halt_go(struct target
*target
)
1202 riscv_info_t
*r
= riscv_info(target
);
1204 if (!r
->is_halted
) {
1205 struct target_type
*tt
= get_target_type(target
);
1206 result
= tt
->halt(target
);
1208 result
= riscv_halt_go_all_harts(target
);
1210 target
->state
= TARGET_HALTED
;
1211 if (target
->debug_reason
== DBG_REASON_NOTHALTED
)
1212 target
->debug_reason
= DBG_REASON_DBGRQ
;
1217 static int halt_finish(struct target
*target
)
1219 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1222 int riscv_halt(struct target
*target
)
1226 if (!r
->is_halted
) {
1227 struct target_type
*tt
= get_target_type(target
);
1228 return tt
->halt(target
);
1231 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1233 int result
= ERROR_OK
;
1235 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1236 struct target
*t
= tlist
->target
;
1237 if (halt_prep(t
) != ERROR_OK
)
1238 result
= ERROR_FAIL
;
1241 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1242 struct target
*t
= tlist
->target
;
1243 riscv_info_t
*i
= riscv_info(t
);
1245 if (halt_go(t
) != ERROR_OK
)
1246 result
= ERROR_FAIL
;
1250 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1251 struct target
*t
= tlist
->target
;
1252 if (halt_finish(t
) != ERROR_OK
)
1257 if (halt_prep(target
) != ERROR_OK
)
1258 result
= ERROR_FAIL
;
1259 if (halt_go(target
) != ERROR_OK
)
1260 result
= ERROR_FAIL
;
1261 if (halt_finish(target
) != ERROR_OK
)
1268 static int riscv_assert_reset(struct target
*target
)
1270 LOG_DEBUG("[%d]", target
->coreid
);
1271 struct target_type
*tt
= get_target_type(target
);
1272 riscv_invalidate_register_cache(target
);
1273 return tt
->assert_reset(target
);
1276 static int riscv_deassert_reset(struct target
*target
)
1278 LOG_DEBUG("[%d]", target
->coreid
);
1279 struct target_type
*tt
= get_target_type(target
);
1280 return tt
->deassert_reset(target
);
1283 int riscv_resume_prep_all_harts(struct target
*target
)
1287 LOG_DEBUG("[%s] prep hart", target_name(target
));
1288 if (riscv_select_current_hart(target
) != ERROR_OK
)
1290 if (riscv_is_halted(target
)) {
1291 if (r
->resume_prep(target
) != ERROR_OK
)
1294 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1295 target_name(target
));
1298 LOG_DEBUG("[%s] mark as prepped", target_name(target
));
1304 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1305 static int disable_triggers(struct target
*target
, riscv_reg_t
*state
)
1309 LOG_DEBUG("deal with triggers");
1311 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
1314 if (r
->manual_hwbp_set
) {
1315 /* Look at every trigger that may have been set. */
1316 riscv_reg_t tselect
;
1317 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1319 for (unsigned int t
= 0; t
< r
->trigger_count
; t
++) {
1320 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1323 if (riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
) != ERROR_OK
)
1325 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
))) {
1327 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, 0) != ERROR_OK
)
1331 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1335 /* Just go through the triggers we manage. */
1336 struct watchpoint
*watchpoint
= target
->watchpoints
;
1338 while (watchpoint
) {
1339 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1340 state
[i
] = watchpoint
->set
;
1341 if (watchpoint
->set
) {
1342 if (riscv_remove_watchpoint(target
, watchpoint
) != ERROR_OK
)
1345 watchpoint
= watchpoint
->next
;
1353 static int enable_triggers(struct target
*target
, riscv_reg_t
*state
)
1357 if (r
->manual_hwbp_set
) {
1358 /* Look at every trigger that may have been set. */
1359 riscv_reg_t tselect
;
1360 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1362 for (unsigned int t
= 0; t
< r
->trigger_count
; t
++) {
1363 if (state
[t
] != 0) {
1364 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1366 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, state
[t
]) != ERROR_OK
)
1370 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1374 struct watchpoint
*watchpoint
= target
->watchpoints
;
1376 while (watchpoint
) {
1377 LOG_DEBUG("watchpoint %d: cleared=%" PRId64
, i
, state
[i
]);
1379 if (riscv_add_watchpoint(target
, watchpoint
) != ERROR_OK
)
1382 watchpoint
= watchpoint
->next
;
1391 * Get everything ready to resume.
1393 static int resume_prep(struct target
*target
, int current
,
1394 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1397 LOG_DEBUG("[%d]", target
->coreid
);
1400 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1402 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1403 /* To be able to run off a trigger, disable all the triggers, step, and
1404 * then resume as usual. */
1405 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
1407 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
1410 if (old_or_new_riscv_step(target
, true, 0, false) != ERROR_OK
)
1413 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
1418 if (riscv_resume_prep_all_harts(target
) != ERROR_OK
)
1422 LOG_DEBUG("[%d] mark as prepped", target
->coreid
);
1429 * Resume all the harts that have been prepped, as close to instantaneous as
1432 static int resume_go(struct target
*target
, int current
,
1433 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1435 riscv_info_t
*r
= riscv_info(target
);
1437 if (!r
->is_halted
) {
1438 struct target_type
*tt
= get_target_type(target
);
1439 result
= tt
->resume(target
, current
, address
, handle_breakpoints
,
1442 result
= riscv_resume_go_all_harts(target
);
1448 static int resume_finish(struct target
*target
)
1450 register_cache_invalidate(target
->reg_cache
);
1452 target
->state
= TARGET_RUNNING
;
1453 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1454 return target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1458 * @par single_hart When true, only resume a single hart even if SMP is
1459 * configured. This is used to run algorithms on just one hart.
1462 struct target
*target
,
1464 target_addr_t address
,
1465 int handle_breakpoints
,
1466 int debug_execution
,
1469 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
1470 int result
= ERROR_OK
;
1471 if (target
->smp
&& !single_hart
) {
1472 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1473 struct target
*t
= tlist
->target
;
1474 if (resume_prep(t
, current
, address
, handle_breakpoints
,
1475 debug_execution
) != ERROR_OK
)
1476 result
= ERROR_FAIL
;
1479 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1480 struct target
*t
= tlist
->target
;
1481 riscv_info_t
*i
= riscv_info(t
);
1483 if (resume_go(t
, current
, address
, handle_breakpoints
,
1484 debug_execution
) != ERROR_OK
)
1485 result
= ERROR_FAIL
;
1489 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1490 struct target
*t
= tlist
->target
;
1491 if (resume_finish(t
) != ERROR_OK
)
1496 if (resume_prep(target
, current
, address
, handle_breakpoints
,
1497 debug_execution
) != ERROR_OK
)
1498 result
= ERROR_FAIL
;
1499 if (resume_go(target
, current
, address
, handle_breakpoints
,
1500 debug_execution
) != ERROR_OK
)
1501 result
= ERROR_FAIL
;
1502 if (resume_finish(target
) != ERROR_OK
)
1509 static int riscv_target_resume(struct target
*target
, int current
, target_addr_t address
,
1510 int handle_breakpoints
, int debug_execution
)
1512 return riscv_resume(target
, current
, address
, handle_breakpoints
,
1513 debug_execution
, false);
1516 static int riscv_mmu(struct target
*target
, int *enabled
)
1518 if (!riscv_enable_virt2phys
) {
1523 /* Don't use MMU in explicit or effective M (machine) mode */
1525 if (riscv_get_register(target
, &priv
, GDB_REGNO_PRIV
) != ERROR_OK
) {
1526 LOG_ERROR("Failed to read priv register.");
1530 riscv_reg_t mstatus
;
1531 if (riscv_get_register(target
, &mstatus
, GDB_REGNO_MSTATUS
) != ERROR_OK
) {
1532 LOG_ERROR("Failed to read mstatus register.");
1536 if ((get_field(mstatus
, MSTATUS_MPRV
) ? get_field(mstatus
, MSTATUS_MPP
) : priv
) == PRV_M
) {
1537 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64
").", mstatus
);
1543 if (riscv_get_register(target
, &satp
, GDB_REGNO_SATP
) != ERROR_OK
) {
1544 LOG_DEBUG("Couldn't read SATP.");
1545 /* If we can't read SATP, then there must not be an MMU. */
1550 if (get_field(satp
, RISCV_SATP_MODE(riscv_xlen(target
))) == SATP_MODE_OFF
) {
1551 LOG_DEBUG("MMU is disabled.");
1554 LOG_DEBUG("MMU is enabled.");
1561 static int riscv_address_translate(struct target
*target
,
1562 target_addr_t
virtual, target_addr_t
*physical
)
1565 riscv_reg_t satp_value
;
1568 target_addr_t table_address
;
1569 const virt2phys_info_t
*info
;
1573 int result
= riscv_get_register(target
, &satp_value
, GDB_REGNO_SATP
);
1574 if (result
!= ERROR_OK
)
1577 unsigned xlen
= riscv_xlen(target
);
1578 mode
= get_field(satp_value
, RISCV_SATP_MODE(xlen
));
1580 case SATP_MODE_SV32
:
1583 case SATP_MODE_SV39
:
1586 case SATP_MODE_SV48
:
1590 LOG_ERROR("No translation or protection." \
1591 " (satp: 0x%" PRIx64
")", satp_value
);
1594 LOG_ERROR("The translation mode is not supported." \
1595 " (satp: 0x%" PRIx64
")", satp_value
);
1598 LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR
"; mode=%s", virtual, info
->name
);
1600 /* verify bits xlen-1:va_bits-1 are all equal */
1601 target_addr_t mask
= ((target_addr_t
)1 << (xlen
- (info
->va_bits
- 1))) - 1;
1602 target_addr_t masked_msbs
= (virtual >> (info
->va_bits
- 1)) & mask
;
1603 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
1604 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR
" is not sign-extended "
1605 "for %s mode.", virtual, info
->name
);
1609 ppn_value
= get_field(satp_value
, RISCV_SATP_PPN(xlen
));
1610 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1611 i
= info
->level
- 1;
1613 uint64_t vpn
= virtual >> info
->vpn_shift
[i
];
1614 vpn
&= info
->vpn_mask
[i
];
1615 target_addr_t pte_address
= table_address
+
1616 (vpn
<< info
->pte_shift
);
1618 assert(info
->pte_shift
<= 3);
1619 int retval
= r
->read_memory(target
, pte_address
,
1620 4, (1 << info
->pte_shift
) / 4, buffer
, 4);
1621 if (retval
!= ERROR_OK
)
1624 if (info
->pte_shift
== 2)
1625 pte
= buf_get_u32(buffer
, 0, 32);
1627 pte
= buf_get_u64(buffer
, 0, 64);
1629 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR
" = 0x%" PRIx64
, i
,
1632 if (!(pte
& PTE_V
) || (!(pte
& PTE_R
) && (pte
& PTE_W
)))
1635 if ((pte
& PTE_R
) || (pte
& PTE_X
)) /* Found leaf PTE. */
1641 ppn_value
= pte
>> PTE_PPN_SHIFT
;
1642 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1646 LOG_ERROR("Couldn't find the PTE.");
1650 /* Make sure to clear out the high bits that may be set. */
1651 *physical
= virtual & (((target_addr_t
)1 << info
->va_bits
) - 1);
1653 while (i
< info
->level
) {
1654 ppn_value
= pte
>> info
->pte_ppn_shift
[i
];
1655 ppn_value
&= info
->pte_ppn_mask
[i
];
1656 *physical
&= ~(((target_addr_t
)info
->pa_ppn_mask
[i
]) <<
1657 info
->pa_ppn_shift
[i
]);
1658 *physical
|= (ppn_value
<< info
->pa_ppn_shift
[i
]);
1661 LOG_DEBUG("0x%" TARGET_PRIxADDR
" -> 0x%" TARGET_PRIxADDR
, virtual,
1667 static int riscv_virt2phys(struct target
*target
, target_addr_t
virtual, target_addr_t
*physical
)
1670 if (riscv_mmu(target
, &enabled
) == ERROR_OK
) {
1674 if (riscv_address_translate(target
, virtual, physical
) == ERROR_OK
)
1681 static int riscv_read_phys_memory(struct target
*target
, target_addr_t phys_address
,
1682 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1685 if (riscv_select_current_hart(target
) != ERROR_OK
)
1687 return r
->read_memory(target
, phys_address
, size
, count
, buffer
, size
);
1690 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
1691 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1694 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR
, address
);
1698 if (riscv_select_current_hart(target
) != ERROR_OK
)
1701 target_addr_t physical_addr
;
1702 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1703 address
= physical_addr
;
1706 return r
->read_memory(target
, address
, size
, count
, buffer
, size
);
1709 static int riscv_write_phys_memory(struct target
*target
, target_addr_t phys_address
,
1710 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1712 if (riscv_select_current_hart(target
) != ERROR_OK
)
1714 struct target_type
*tt
= get_target_type(target
);
1715 return tt
->write_memory(target
, phys_address
, size
, count
, buffer
);
1718 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
1719 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1722 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR
, address
);
1726 if (riscv_select_current_hart(target
) != ERROR_OK
)
1729 target_addr_t physical_addr
;
1730 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1731 address
= physical_addr
;
1733 struct target_type
*tt
= get_target_type(target
);
1734 return tt
->write_memory(target
, address
, size
, count
, buffer
);
1737 const char *riscv_get_gdb_arch(struct target
*target
)
1739 switch (riscv_xlen(target
)) {
1741 return "riscv:rv32";
1743 return "riscv:rv64";
1745 LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target
));
1749 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
1750 struct reg
**reg_list
[], int *reg_list_size
,
1751 enum target_register_class reg_class
, bool read
)
1754 LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1755 target_name(target
), r
->current_hartid
, reg_class
, read
);
1757 if (!target
->reg_cache
) {
1758 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1762 if (riscv_select_current_hart(target
) != ERROR_OK
)
1765 switch (reg_class
) {
1766 case REG_CLASS_GENERAL
:
1767 *reg_list_size
= 33;
1770 *reg_list_size
= target
->reg_cache
->num_regs
;
1773 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
1777 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
1781 for (int i
= 0; i
< *reg_list_size
; i
++) {
1782 assert(!target
->reg_cache
->reg_list
[i
].valid
||
1783 target
->reg_cache
->reg_list
[i
].size
> 0);
1784 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
1786 target
->reg_cache
->reg_list
[i
].exist
&&
1787 !target
->reg_cache
->reg_list
[i
].valid
) {
1788 if (target
->reg_cache
->reg_list
[i
].type
->get(
1789 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
1797 static int riscv_get_gdb_reg_list_noread(struct target
*target
,
1798 struct reg
**reg_list
[], int *reg_list_size
,
1799 enum target_register_class reg_class
)
1801 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1805 static int riscv_get_gdb_reg_list(struct target
*target
,
1806 struct reg
**reg_list
[], int *reg_list_size
,
1807 enum target_register_class reg_class
)
1809 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1813 static int riscv_arch_state(struct target
*target
)
1815 struct target_type
*tt
= get_target_type(target
);
1816 return tt
->arch_state(target
);
1819 /* Algorithm must end with a software breakpoint instruction. */
1820 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
1821 struct mem_param
*mem_params
, int num_reg_params
,
1822 struct reg_param
*reg_params
, target_addr_t entry_point
,
1823 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
1827 if (num_mem_params
> 0) {
1828 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1832 if (target
->state
!= TARGET_HALTED
) {
1833 LOG_WARNING("target not halted");
1834 return ERROR_TARGET_NOT_HALTED
;
1837 /* Save registers */
1838 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", true);
1839 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1841 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1842 LOG_DEBUG("saved_pc=0x%" PRIx64
, saved_pc
);
1844 uint64_t saved_regs
[32];
1845 for (int i
= 0; i
< num_reg_params
; i
++) {
1846 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1847 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1849 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1853 if (r
->size
!= reg_params
[i
].size
) {
1854 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1855 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1859 if (r
->number
> GDB_REGNO_XPR31
) {
1860 LOG_ERROR("Only GPRs can be use as argument registers.");
1864 if (r
->type
->get(r
) != ERROR_OK
)
1866 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1868 if (reg_params
[i
].direction
== PARAM_OUT
|| reg_params
[i
].direction
== PARAM_IN_OUT
) {
1869 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1875 /* Disable Interrupts before attempting to run the algorithm. */
1876 uint64_t current_mstatus
;
1877 uint8_t mstatus_bytes
[8] = { 0 };
1879 LOG_DEBUG("Disabling Interrupts");
1880 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1883 LOG_ERROR("Couldn't find mstatus!");
1887 reg_mstatus
->type
->get(reg_mstatus
);
1888 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1889 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1890 buf_set_u64(mstatus_bytes
, 0, info
->xlen
, set_field(current_mstatus
,
1893 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1896 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1897 if (riscv_resume(target
, 0, entry_point
, 0, 0, true) != ERROR_OK
)
1900 int64_t start
= timeval_ms();
1901 while (target
->state
!= TARGET_HALTED
) {
1902 LOG_DEBUG("poll()");
1903 int64_t now
= timeval_ms();
1904 if (now
- start
> timeout_ms
) {
1905 LOG_ERROR("Algorithm timed out after %" PRId64
" ms.", now
- start
);
1907 old_or_new_riscv_poll(target
);
1908 enum gdb_regno regnums
[] = {
1909 GDB_REGNO_RA
, GDB_REGNO_SP
, GDB_REGNO_GP
, GDB_REGNO_TP
,
1910 GDB_REGNO_T0
, GDB_REGNO_T1
, GDB_REGNO_T2
, GDB_REGNO_FP
,
1911 GDB_REGNO_S1
, GDB_REGNO_A0
, GDB_REGNO_A1
, GDB_REGNO_A2
,
1912 GDB_REGNO_A3
, GDB_REGNO_A4
, GDB_REGNO_A5
, GDB_REGNO_A6
,
1913 GDB_REGNO_A7
, GDB_REGNO_S2
, GDB_REGNO_S3
, GDB_REGNO_S4
,
1914 GDB_REGNO_S5
, GDB_REGNO_S6
, GDB_REGNO_S7
, GDB_REGNO_S8
,
1915 GDB_REGNO_S9
, GDB_REGNO_S10
, GDB_REGNO_S11
, GDB_REGNO_T3
,
1916 GDB_REGNO_T4
, GDB_REGNO_T5
, GDB_REGNO_T6
,
1918 GDB_REGNO_MSTATUS
, GDB_REGNO_MEPC
, GDB_REGNO_MCAUSE
,
1920 for (unsigned i
= 0; i
< ARRAY_SIZE(regnums
); i
++) {
1921 enum gdb_regno regno
= regnums
[i
];
1922 riscv_reg_t reg_value
;
1923 if (riscv_get_register(target
, ®_value
, regno
) != ERROR_OK
)
1925 LOG_ERROR("%s = 0x%" PRIx64
, gdb_regno_name(regno
), reg_value
);
1927 return ERROR_TARGET_TIMEOUT
;
1930 int result
= old_or_new_riscv_poll(target
);
1931 if (result
!= ERROR_OK
)
1935 /* The current hart id might have been changed in poll(). */
1936 if (riscv_select_current_hart(target
) != ERROR_OK
)
1939 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1941 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1942 if (exit_point
&& final_pc
!= exit_point
) {
1943 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1944 TARGET_PRIxADDR
, final_pc
, exit_point
);
1948 /* Restore Interrupts */
1949 LOG_DEBUG("Restoring Interrupts");
1950 buf_set_u64(mstatus_bytes
, 0, info
->xlen
, current_mstatus
);
1951 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1953 /* Restore registers */
1954 uint8_t buf
[8] = { 0 };
1955 buf_set_u64(buf
, 0, info
->xlen
, saved_pc
);
1956 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1959 for (int i
= 0; i
< num_reg_params
; i
++) {
1960 if (reg_params
[i
].direction
== PARAM_IN
||
1961 reg_params
[i
].direction
== PARAM_IN_OUT
) {
1962 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1963 if (r
->type
->get(r
) != ERROR_OK
) {
1964 LOG_ERROR("get(%s) failed", r
->name
);
1967 buf_cpy(r
->value
, reg_params
[i
].value
, reg_params
[i
].size
);
1969 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1970 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, false);
1971 buf_set_u64(buf
, 0, info
->xlen
, saved_regs
[r
->number
]);
1972 if (r
->type
->set(r
, buf
) != ERROR_OK
) {
1973 LOG_ERROR("set(%s) failed", r
->name
);
1981 static int riscv_checksum_memory(struct target
*target
,
1982 target_addr_t address
, uint32_t count
,
1985 struct working_area
*crc_algorithm
;
1986 struct reg_param reg_params
[2];
1989 LOG_DEBUG("address=0x%" TARGET_PRIxADDR
"; count=0x%" PRIx32
, address
, count
);
1991 static const uint8_t riscv32_crc_code
[] = {
1992 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
1994 static const uint8_t riscv64_crc_code
[] = {
1995 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
1998 static const uint8_t *crc_code
;
2000 unsigned xlen
= riscv_xlen(target
);
2001 unsigned crc_code_size
;
2003 crc_code
= riscv32_crc_code
;
2004 crc_code_size
= sizeof(riscv32_crc_code
);
2006 crc_code
= riscv64_crc_code
;
2007 crc_code_size
= sizeof(riscv64_crc_code
);
2010 if (count
< crc_code_size
* 4) {
2011 /* Don't use the algorithm for relatively small buffers. It's faster
2012 * just to read the memory. target_checksum_memory() will take care of
2013 * that if we fail. */
2017 retval
= target_alloc_working_area(target
, crc_code_size
, &crc_algorithm
);
2018 if (retval
!= ERROR_OK
)
2021 if (crc_algorithm
->address
+ crc_algorithm
->size
> address
&&
2022 crc_algorithm
->address
< address
+ count
) {
2023 /* Region to checksum overlaps with the work area we've been assigned.
2024 * Bail. (Would be better to manually checksum what we read there, and
2025 * use the algorithm for the rest.) */
2026 target_free_working_area(target
, crc_algorithm
);
2030 retval
= target_write_buffer(target
, crc_algorithm
->address
, crc_code_size
,
2032 if (retval
!= ERROR_OK
) {
2033 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT
": %d",
2034 crc_algorithm
->address
, retval
);
2035 target_free_working_area(target
, crc_algorithm
);
2039 init_reg_param(®_params
[0], "a0", xlen
, PARAM_IN_OUT
);
2040 init_reg_param(®_params
[1], "a1", xlen
, PARAM_OUT
);
2041 buf_set_u64(reg_params
[0].value
, 0, xlen
, address
);
2042 buf_set_u64(reg_params
[1].value
, 0, xlen
, count
);
2044 /* 20 second timeout/megabyte */
2045 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
2047 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
2048 crc_algorithm
->address
,
2049 0, /* Leave exit point unspecified because we don't know. */
2052 if (retval
== ERROR_OK
)
2053 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2055 LOG_ERROR("error executing RISC-V CRC algorithm");
2057 destroy_reg_param(®_params
[0]);
2058 destroy_reg_param(®_params
[1]);
2060 target_free_working_area(target
, crc_algorithm
);
2062 LOG_DEBUG("checksum=0x%" PRIx32
", result=%d", *checksum
, retval
);
2067 /*** OpenOCD Helper Functions ***/
2069 enum riscv_poll_hart
{
2071 RPH_DISCOVERED_HALTED
,
2072 RPH_DISCOVERED_RUNNING
,
2075 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
2078 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2081 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
2083 /* If OpenOCD thinks we're running but this hart is halted then it's time
2084 * to raise an event. */
2085 bool halted
= riscv_is_halted(target
);
2086 if (target
->state
!= TARGET_HALTED
&& halted
) {
2087 LOG_DEBUG(" triggered a halt");
2089 return RPH_DISCOVERED_HALTED
;
2090 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
2091 LOG_DEBUG(" triggered running");
2092 target
->state
= TARGET_RUNNING
;
2093 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2094 return RPH_DISCOVERED_RUNNING
;
2097 return RPH_NO_CHANGE
;
2100 int set_debug_reason(struct target
*target
, enum riscv_halt_reason halt_reason
)
2102 switch (halt_reason
) {
2103 case RISCV_HALT_BREAKPOINT
:
2104 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
2106 case RISCV_HALT_TRIGGER
:
2107 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
2109 case RISCV_HALT_INTERRUPT
:
2110 case RISCV_HALT_GROUP
:
2111 target
->debug_reason
= DBG_REASON_DBGRQ
;
2113 case RISCV_HALT_SINGLESTEP
:
2114 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2116 case RISCV_HALT_UNKNOWN
:
2117 target
->debug_reason
= DBG_REASON_UNDEFINED
;
2119 case RISCV_HALT_ERROR
:
2122 LOG_DEBUG("[%s] debug_reason=%d", target_name(target
), target
->debug_reason
);
2126 int sample_memory(struct target
*target
)
2130 if (!r
->sample_buf
.buf
|| !r
->sample_config
.enabled
)
2133 LOG_DEBUG("buf used/size: %d/%d", r
->sample_buf
.used
, r
->sample_buf
.size
);
2135 uint64_t start
= timeval_ms();
2136 riscv_sample_buf_maybe_add_timestamp(target
, true);
2137 int result
= ERROR_OK
;
2138 if (r
->sample_memory
) {
2139 result
= r
->sample_memory(target
, &r
->sample_buf
, &r
->sample_config
,
2140 start
+ TARGET_DEFAULT_POLLING_INTERVAL
);
2141 if (result
!= ERROR_NOT_IMPLEMENTED
)
2145 /* Default slow path. */
2146 while (timeval_ms() - start
< TARGET_DEFAULT_POLLING_INTERVAL
) {
2147 for (unsigned int i
= 0; i
< ARRAY_SIZE(r
->sample_config
.bucket
); i
++) {
2148 if (r
->sample_config
.bucket
[i
].enabled
&&
2149 r
->sample_buf
.used
+ 1 + r
->sample_config
.bucket
[i
].size_bytes
< r
->sample_buf
.size
) {
2150 assert(i
< RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE
);
2151 r
->sample_buf
.buf
[r
->sample_buf
.used
] = i
;
2152 result
= riscv_read_phys_memory(
2153 target
, r
->sample_config
.bucket
[i
].address
,
2154 r
->sample_config
.bucket
[i
].size_bytes
, 1,
2155 r
->sample_buf
.buf
+ r
->sample_buf
.used
+ 1);
2156 if (result
== ERROR_OK
)
2157 r
->sample_buf
.used
+= 1 + r
->sample_config
.bucket
[i
].size_bytes
;
2165 riscv_sample_buf_maybe_add_timestamp(target
, false);
2166 if (result
!= ERROR_OK
) {
2167 LOG_INFO("Turning off memory sampling because it failed.");
2168 r
->sample_config
.enabled
= false;
2173 /*** OpenOCD Interface ***/
2174 int riscv_openocd_poll(struct target
*target
)
2176 LOG_DEBUG("polling all harts");
2177 int halted_hart
= -1;
2180 unsigned halts_discovered
= 0;
2181 unsigned should_remain_halted
= 0;
2182 unsigned should_resume
= 0;
2184 for (struct target_list
*list
= target
->head
; list
;
2185 list
= list
->next
, i
++) {
2186 struct target
*t
= list
->target
;
2187 riscv_info_t
*r
= riscv_info(t
);
2188 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
2192 case RPH_DISCOVERED_RUNNING
:
2193 t
->state
= TARGET_RUNNING
;
2194 t
->debug_reason
= DBG_REASON_NOTHALTED
;
2196 case RPH_DISCOVERED_HALTED
:
2198 t
->state
= TARGET_HALTED
;
2199 enum riscv_halt_reason halt_reason
=
2200 riscv_halt_reason(t
, r
->current_hartid
);
2201 if (set_debug_reason(t
, halt_reason
) != ERROR_OK
)
2204 if (halt_reason
== RISCV_HALT_BREAKPOINT
) {
2206 switch (riscv_semihosting(t
, &retval
)) {
2209 /* This hart should remain halted. */
2210 should_remain_halted
++;
2213 /* This hart should be resumed, along with any other
2214 * harts that halted due to haltgroups. */
2220 } else if (halt_reason
!= RISCV_HALT_GROUP
) {
2221 should_remain_halted
++;
2230 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2231 should_remain_halted
, should_resume
);
2232 if (should_remain_halted
&& should_resume
) {
2233 LOG_WARNING("%d harts should remain halted, and %d should resume.",
2234 should_remain_halted
, should_resume
);
2236 if (should_remain_halted
) {
2237 LOG_DEBUG("halt all");
2239 } else if (should_resume
) {
2240 LOG_DEBUG("resume all");
2241 riscv_resume(target
, true, 0, 0, 0, false);
2244 /* Sample memory if any target is running. */
2245 for (struct target_list
*list
= target
->head
; list
;
2246 list
= list
->next
, i
++) {
2247 struct target
*t
= list
->target
;
2248 if (t
->state
== TARGET_RUNNING
) {
2249 sample_memory(target
);
2257 enum riscv_poll_hart out
= riscv_poll_hart(target
,
2258 riscv_current_hartid(target
));
2259 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
) {
2260 if (target
->state
== TARGET_RUNNING
)
2261 sample_memory(target
);
2263 } else if (out
== RPH_ERROR
) {
2267 halted_hart
= riscv_current_hartid(target
);
2268 LOG_DEBUG(" hart %d halted", halted_hart
);
2270 enum riscv_halt_reason halt_reason
= riscv_halt_reason(target
, halted_hart
);
2271 if (set_debug_reason(target
, halt_reason
) != ERROR_OK
)
2273 target
->state
= TARGET_HALTED
;
2276 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
2278 switch (riscv_semihosting(target
, &retval
)) {
2281 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2284 if (riscv_resume(target
, true, 0, 0, 0, false) != ERROR_OK
)
2291 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2297 int riscv_openocd_step(struct target
*target
, int current
,
2298 target_addr_t address
, int handle_breakpoints
)
2300 LOG_DEBUG("stepping rtos hart");
2303 riscv_set_register(target
, GDB_REGNO_PC
, address
);
2305 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
2306 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
2309 int out
= riscv_step_rtos_hart(target
);
2310 if (out
!= ERROR_OK
) {
2311 LOG_ERROR("unable to step rtos hart");
2315 register_cache_invalidate(target
->reg_cache
);
2317 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
2320 target
->state
= TARGET_RUNNING
;
2321 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
2322 target
->state
= TARGET_HALTED
;
2323 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2324 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2328 /* Command Handlers */
2329 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
2331 if (CMD_ARGC
!= 1) {
2332 LOG_ERROR("Command takes exactly 1 parameter");
2333 return ERROR_COMMAND_SYNTAX_ERROR
;
2335 int timeout
= atoi(CMD_ARGV
[0]);
2337 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2341 riscv_command_timeout_sec
= timeout
;
2346 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
2348 if (CMD_ARGC
!= 1) {
2349 LOG_ERROR("Command takes exactly 1 parameter");
2350 return ERROR_COMMAND_SYNTAX_ERROR
;
2352 int timeout
= atoi(CMD_ARGV
[0]);
2354 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2358 riscv_reset_timeout_sec
= timeout
;
2362 COMMAND_HANDLER(riscv_set_prefer_sba
)
2364 struct target
*target
= get_current_target(CMD_CTX
);
2367 LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
2368 if (CMD_ARGC
!= 1) {
2369 LOG_ERROR("Command takes exactly 1 parameter");
2370 return ERROR_COMMAND_SYNTAX_ERROR
;
2372 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], prefer_sba
);
2374 /* Use system bus with highest priority */
2375 r
->mem_access_methods
[0] = RISCV_MEM_ACCESS_SYSBUS
;
2376 r
->mem_access_methods
[1] = RISCV_MEM_ACCESS_PROGBUF
;
2377 r
->mem_access_methods
[2] = RISCV_MEM_ACCESS_ABSTRACT
;
2379 /* Use progbuf with highest priority */
2380 r
->mem_access_methods
[0] = RISCV_MEM_ACCESS_PROGBUF
;
2381 r
->mem_access_methods
[1] = RISCV_MEM_ACCESS_SYSBUS
;
2382 r
->mem_access_methods
[2] = RISCV_MEM_ACCESS_ABSTRACT
;
2385 /* Reset warning flags */
2386 r
->mem_access_progbuf_warn
= true;
2387 r
->mem_access_sysbus_warn
= true;
2388 r
->mem_access_abstract_warn
= true;
2393 COMMAND_HANDLER(riscv_set_mem_access
)
2395 struct target
*target
= get_current_target(CMD_CTX
);
2397 int progbuf_cnt
= 0;
2399 int abstract_cnt
= 0;
2401 if (CMD_ARGC
< 1 || CMD_ARGC
> RISCV_NUM_MEM_ACCESS_METHODS
) {
2402 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS
);
2403 return ERROR_COMMAND_SYNTAX_ERROR
;
2406 /* Check argument validity */
2407 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2408 if (strcmp("progbuf", CMD_ARGV
[i
]) == 0) {
2410 } else if (strcmp("sysbus", CMD_ARGV
[i
]) == 0) {
2412 } else if (strcmp("abstract", CMD_ARGV
[i
]) == 0) {
2415 LOG_ERROR("Unknown argument '%s'. "
2416 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV
[i
]);
2417 return ERROR_COMMAND_SYNTAX_ERROR
;
2420 if (progbuf_cnt
> 1 || sysbus_cnt
> 1 || abstract_cnt
> 1) {
2421 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2422 return ERROR_COMMAND_SYNTAX_ERROR
;
2425 /* Args are valid, store them */
2426 for (unsigned int i
= 0; i
< RISCV_NUM_MEM_ACCESS_METHODS
; i
++)
2427 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_UNSPECIFIED
;
2428 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2429 if (strcmp("progbuf", CMD_ARGV
[i
]) == 0)
2430 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_PROGBUF
;
2431 else if (strcmp("sysbus", CMD_ARGV
[i
]) == 0)
2432 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_SYSBUS
;
2433 else if (strcmp("abstract", CMD_ARGV
[i
]) == 0)
2434 r
->mem_access_methods
[i
] = RISCV_MEM_ACCESS_ABSTRACT
;
2437 /* Reset warning flags */
2438 r
->mem_access_progbuf_warn
= true;
2439 r
->mem_access_sysbus_warn
= true;
2440 r
->mem_access_abstract_warn
= true;
2445 COMMAND_HANDLER(riscv_set_enable_virtual
)
2447 if (CMD_ARGC
!= 1) {
2448 LOG_ERROR("Command takes exactly 1 parameter");
2449 return ERROR_COMMAND_SYNTAX_ERROR
;
2451 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virtual
);
2455 int parse_ranges(struct list_head
*ranges
, const char *tcl_arg
, const char *reg_type
, unsigned int max_val
)
2457 char *args
= strdup(tcl_arg
);
2461 /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2462 char *arg
= strtok(args
, ",");
2468 char *dash
= strchr(arg
, '-');
2469 char *equals
= strchr(arg
, '=');
2472 if (!dash
&& !equals
) {
2473 /* Expecting single register number. */
2474 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2475 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2477 return ERROR_COMMAND_SYNTAX_ERROR
;
2479 } else if (dash
&& !equals
) {
2480 /* Expecting register range - two numbers separated by a dash: ##-## */
2483 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2484 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2486 return ERROR_COMMAND_SYNTAX_ERROR
;
2488 if (sscanf(dash
, "%u%n", &high
, &pos
) != 1 || pos
!= strlen(dash
)) {
2489 LOG_ERROR("Failed to parse single register number from '%s'.", dash
);
2491 return ERROR_COMMAND_SYNTAX_ERROR
;
2494 LOG_ERROR("Incorrect range encountered [%u, %u].", low
, high
);
2498 } else if (!dash
&& equals
) {
2499 /* Expecting single register number with textual name specified: ##=name */
2502 if (sscanf(arg
, "%u%n", &low
, &pos
) != 1 || pos
!= strlen(arg
)) {
2503 LOG_ERROR("Failed to parse single register number from '%s'.", arg
);
2505 return ERROR_COMMAND_SYNTAX_ERROR
;
2508 name
= calloc(1, strlen(equals
) + strlen(reg_type
) + 2);
2510 LOG_ERROR("Failed to allocate register name.");
2515 /* Register prefix: "csr_" or "custom_" */
2516 strcpy(name
, reg_type
);
2517 name
[strlen(reg_type
)] = '_';
2519 if (sscanf(equals
, "%[_a-zA-Z0-9]%n", name
+ strlen(reg_type
) + 1, &pos
) != 1 || pos
!= strlen(equals
)) {
2520 LOG_ERROR("Failed to parse register name from '%s'.", equals
);
2523 return ERROR_COMMAND_SYNTAX_ERROR
;
2526 LOG_ERROR("Invalid argument '%s'.", arg
);
2528 return ERROR_COMMAND_SYNTAX_ERROR
;
2531 high
= high
> low
? high
: low
;
2533 if (high
> max_val
) {
2534 LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type
, high
, max_val
);
2540 /* Check for overlap, name uniqueness. */
2541 range_list_t
*entry
;
2542 list_for_each_entry(entry
, ranges
, list
) {
2543 if ((entry
->low
<= high
) && (low
<= entry
->high
)) {
2545 LOG_WARNING("Duplicate %s register number - "
2546 "Register %u has already been exposed previously", reg_type
, low
);
2548 LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2549 "with already exposed register/range at %u.", low
, entry
->low
);
2552 if (entry
->name
&& name
&& (strcasecmp(entry
->name
, name
) == 0)) {
2553 LOG_ERROR("Duplicate register name \"%s\" found.", name
);
2560 range_list_t
*range
= calloc(1, sizeof(range_list_t
));
2562 LOG_ERROR("Failed to allocate range list.");
2571 list_add(&range
->list
, ranges
);
2573 arg
= strtok(NULL
, ",");
2580 COMMAND_HANDLER(riscv_set_expose_csrs
)
2582 if (CMD_ARGC
== 0) {
2583 LOG_ERROR("Command expects parameters");
2584 return ERROR_COMMAND_SYNTAX_ERROR
;
2587 struct target
*target
= get_current_target(CMD_CTX
);
2591 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2592 ret
= parse_ranges(&info
->expose_csr
, CMD_ARGV
[i
], "csr", 0xfff);
2593 if (ret
!= ERROR_OK
)
2600 COMMAND_HANDLER(riscv_set_expose_custom
)
2602 if (CMD_ARGC
== 0) {
2603 LOG_ERROR("Command expects parameters");
2604 return ERROR_COMMAND_SYNTAX_ERROR
;
2607 struct target
*target
= get_current_target(CMD_CTX
);
2611 for (unsigned int i
= 0; i
< CMD_ARGC
; i
++) {
2612 ret
= parse_ranges(&info
->expose_custom
, CMD_ARGV
[i
], "custom", 0x3fff);
2613 if (ret
!= ERROR_OK
)
2620 COMMAND_HANDLER(riscv_authdata_read
)
2622 unsigned int index
= 0;
2623 if (CMD_ARGC
== 0) {
2625 } else if (CMD_ARGC
== 1) {
2626 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], index
);
2628 LOG_ERROR("Command takes at most one parameter");
2629 return ERROR_COMMAND_SYNTAX_ERROR
;
2632 struct target
*target
= get_current_target(CMD_CTX
);
2634 LOG_ERROR("target is NULL!");
2640 LOG_ERROR("riscv_info is NULL!");
2644 if (r
->authdata_read
) {
2646 if (r
->authdata_read(target
, &value
, index
) != ERROR_OK
)
2648 command_print_sameline(CMD
, "0x%08" PRIx32
, value
);
2651 LOG_ERROR("authdata_read is not implemented for this target.");
2656 COMMAND_HANDLER(riscv_authdata_write
)
2659 unsigned int index
= 0;
2661 if (CMD_ARGC
== 0) {
2663 } else if (CMD_ARGC
== 1) {
2664 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
2665 } else if (CMD_ARGC
== 2) {
2666 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], index
);
2667 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2669 LOG_ERROR("Command takes at most 2 arguments");
2670 return ERROR_COMMAND_SYNTAX_ERROR
;
2673 struct target
*target
= get_current_target(CMD_CTX
);
2676 if (r
->authdata_write
) {
2677 return r
->authdata_write(target
, value
, index
);
2679 LOG_ERROR("authdata_write is not implemented for this target.");
2684 COMMAND_HANDLER(riscv_dmi_read
)
2686 if (CMD_ARGC
!= 1) {
2687 LOG_ERROR("Command takes 1 parameter");
2688 return ERROR_COMMAND_SYNTAX_ERROR
;
2691 struct target
*target
= get_current_target(CMD_CTX
);
2693 LOG_ERROR("target is NULL!");
2699 LOG_ERROR("riscv_info is NULL!");
2704 uint32_t address
, value
;
2705 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2706 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
2708 command_print(CMD
, "0x%" PRIx32
, value
);
2711 LOG_ERROR("dmi_read is not implemented for this target.");
2717 COMMAND_HANDLER(riscv_dmi_write
)
2719 if (CMD_ARGC
!= 2) {
2720 LOG_ERROR("Command takes exactly 2 arguments");
2721 return ERROR_COMMAND_SYNTAX_ERROR
;
2724 struct target
*target
= get_current_target(CMD_CTX
);
2727 uint32_t address
, value
;
2728 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2729 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2732 return r
->dmi_write(target
, address
, value
);
2734 LOG_ERROR("dmi_write is not implemented for this target.");
2739 COMMAND_HANDLER(riscv_test_sba_config_reg
)
2741 if (CMD_ARGC
!= 4) {
2742 LOG_ERROR("Command takes exactly 4 arguments");
2743 return ERROR_COMMAND_SYNTAX_ERROR
;
2746 struct target
*target
= get_current_target(CMD_CTX
);
2749 target_addr_t legal_address
;
2751 target_addr_t illegal_address
;
2752 bool run_sbbusyerror_test
;
2754 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[0], legal_address
);
2755 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], num_words
);
2756 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[2], illegal_address
);
2757 COMMAND_PARSE_ON_OFF(CMD_ARGV
[3], run_sbbusyerror_test
);
2759 if (r
->test_sba_config_reg
) {
2760 return r
->test_sba_config_reg(target
, legal_address
, num_words
,
2761 illegal_address
, run_sbbusyerror_test
);
2763 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2768 COMMAND_HANDLER(riscv_reset_delays
)
2773 LOG_ERROR("Command takes at most one argument");
2774 return ERROR_COMMAND_SYNTAX_ERROR
;
2778 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
2780 struct target
*target
= get_current_target(CMD_CTX
);
2782 r
->reset_delays_wait
= wait
;
2786 COMMAND_HANDLER(riscv_set_ir
)
2788 if (CMD_ARGC
!= 2) {
2789 LOG_ERROR("Command takes exactly 2 arguments");
2790 return ERROR_COMMAND_SYNTAX_ERROR
;
2794 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2796 if (!strcmp(CMD_ARGV
[0], "idcode"))
2797 buf_set_u32(ir_idcode
, 0, 32, value
);
2798 else if (!strcmp(CMD_ARGV
[0], "dtmcs"))
2799 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
2800 else if (!strcmp(CMD_ARGV
[0], "dmi"))
2801 buf_set_u32(ir_dbus
, 0, 32, value
);
2808 COMMAND_HANDLER(riscv_resume_order
)
2811 LOG_ERROR("Command takes at most one argument");
2812 return ERROR_COMMAND_SYNTAX_ERROR
;
2815 if (!strcmp(CMD_ARGV
[0], "normal")) {
2816 resume_order
= RO_NORMAL
;
2817 } else if (!strcmp(CMD_ARGV
[0], "reversed")) {
2818 resume_order
= RO_REVERSED
;
2820 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV
[0]);
2827 COMMAND_HANDLER(riscv_use_bscan_tunnel
)
2830 int tunnel_type
= BSCAN_TUNNEL_NESTED_TAP
;
2833 LOG_ERROR("Command takes at most two arguments");
2834 return ERROR_COMMAND_SYNTAX_ERROR
;
2835 } else if (CMD_ARGC
== 1) {
2836 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2837 } else if (CMD_ARGC
== 2) {
2838 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2839 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], tunnel_type
);
2841 if (tunnel_type
== BSCAN_TUNNEL_NESTED_TAP
)
2842 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2843 else if (tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
2844 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2846 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2848 bscan_tunnel_type
= tunnel_type
;
2849 bscan_tunnel_ir_width
= irwidth
;
2853 COMMAND_HANDLER(riscv_set_enable_virt2phys
)
2855 if (CMD_ARGC
!= 1) {
2856 LOG_ERROR("Command takes exactly 1 parameter");
2857 return ERROR_COMMAND_SYNTAX_ERROR
;
2859 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virt2phys
);
2863 COMMAND_HANDLER(riscv_set_ebreakm
)
2865 if (CMD_ARGC
!= 1) {
2866 LOG_ERROR("Command takes exactly 1 parameter");
2867 return ERROR_COMMAND_SYNTAX_ERROR
;
2869 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreakm
);
2873 COMMAND_HANDLER(riscv_set_ebreaks
)
2875 if (CMD_ARGC
!= 1) {
2876 LOG_ERROR("Command takes exactly 1 parameter");
2877 return ERROR_COMMAND_SYNTAX_ERROR
;
2879 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaks
);
2883 COMMAND_HANDLER(riscv_set_ebreaku
)
2885 if (CMD_ARGC
!= 1) {
2886 LOG_ERROR("Command takes exactly 1 parameter");
2887 return ERROR_COMMAND_SYNTAX_ERROR
;
2889 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaku
);
2893 COMMAND_HELPER(riscv_print_info_line
, const char *section
, const char *key
,
2897 snprintf(full_key
, sizeof(full_key
), "%s.%s", section
, key
);
2898 command_print(CMD
, "%-21s %3d", full_key
, value
);
2902 COMMAND_HANDLER(handle_info
)
2904 struct target
*target
= get_current_target(CMD_CTX
);
2907 /* This output format can be fed directly into TCL's "array set". */
2909 riscv_print_info_line(CMD
, "hart", "xlen", riscv_xlen(target
));
2910 riscv_enumerate_triggers(target
);
2911 riscv_print_info_line(CMD
, "hart", "trigger_count",
2915 return CALL_COMMAND_HANDLER(r
->print_info
, target
);
2920 static const struct command_registration riscv_exec_command_handlers
[] = {
2923 .handler
= handle_info
,
2924 .mode
= COMMAND_EXEC
,
2926 .help
= "Displays some information OpenOCD detected about the target."
2929 .name
= "set_command_timeout_sec",
2930 .handler
= riscv_set_command_timeout_sec
,
2931 .mode
= COMMAND_ANY
,
2933 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
2936 .name
= "set_reset_timeout_sec",
2937 .handler
= riscv_set_reset_timeout_sec
,
2938 .mode
= COMMAND_ANY
,
2940 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
2943 .name
= "set_prefer_sba",
2944 .handler
= riscv_set_prefer_sba
,
2945 .mode
= COMMAND_ANY
,
2947 .help
= "When on, prefer to use System Bus Access to access memory. "
2948 "When off (default), prefer to use the Program Buffer to access memory."
2951 .name
= "set_mem_access",
2952 .handler
= riscv_set_mem_access
,
2953 .mode
= COMMAND_ANY
,
2954 .usage
= "method1 [method2] [method3]",
2955 .help
= "Set which memory access methods shall be used and in which order "
2956 "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2959 .name
= "set_enable_virtual",
2960 .handler
= riscv_set_enable_virtual
,
2961 .mode
= COMMAND_ANY
,
2963 .help
= "When on, memory accesses are performed on physical or virtual "
2964 "memory depending on the current system configuration. "
2965 "When off (default), all memory accessses are performed on physical memory."
2968 .name
= "expose_csrs",
2969 .handler
= riscv_set_expose_csrs
,
2970 .mode
= COMMAND_CONFIG
,
2971 .usage
= "n0[-m0|=name0][,n1[-m1|=name1]]...",
2972 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
2973 "addition to the standard ones. This must be executed before "
2977 .name
= "expose_custom",
2978 .handler
= riscv_set_expose_custom
,
2979 .mode
= COMMAND_CONFIG
,
2980 .usage
= "n0[-m0|=name0][,n1[-m1|=name1]]...",
2981 .help
= "Configure a list of inclusive ranges for custom registers to "
2982 "expose. custom0 is accessed as abstract register number 0xc000, "
2983 "etc. This must be executed before `init`."
2986 .name
= "authdata_read",
2987 .handler
= riscv_authdata_read
,
2989 .mode
= COMMAND_ANY
,
2990 .help
= "Return the 32-bit value read from authdata or authdata0 "
2991 "(index=0), or authdata1 (index=1)."
2994 .name
= "authdata_write",
2995 .handler
= riscv_authdata_write
,
2996 .mode
= COMMAND_ANY
,
2997 .usage
= "[index] value",
2998 .help
= "Write the 32-bit value to authdata or authdata0 (index=0), "
2999 "or authdata1 (index=1)."
3003 .handler
= riscv_dmi_read
,
3004 .mode
= COMMAND_ANY
,
3006 .help
= "Perform a 32-bit DMI read at address, returning the value."
3009 .name
= "dmi_write",
3010 .handler
= riscv_dmi_write
,
3011 .mode
= COMMAND_ANY
,
3012 .usage
= "address value",
3013 .help
= "Perform a 32-bit DMI write of value at address."
3016 .name
= "test_sba_config_reg",
3017 .handler
= riscv_test_sba_config_reg
,
3018 .mode
= COMMAND_ANY
,
3019 .usage
= "legal_address num_words "
3020 "illegal_address run_sbbusyerror_test[on/off]",
3021 .help
= "Perform a series of tests on the SBCS register. "
3022 "Inputs are a legal, 128-byte aligned address and a number of words to "
3023 "read/write starting at that address (i.e., address range [legal address, "
3024 "legal_address+word_size*num_words) must be legally readable/writable), "
3025 "an illegal, 128-byte aligned address for error flag/handling cases, "
3026 "and whether sbbusyerror test should be run."
3029 .name
= "reset_delays",
3030 .handler
= riscv_reset_delays
,
3031 .mode
= COMMAND_ANY
,
3033 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
3034 "between scans to avoid encountering the target being busy. This "
3035 "command resets those learned values after `wait` scans. It's only "
3036 "useful for testing OpenOCD itself."
3039 .name
= "resume_order",
3040 .handler
= riscv_resume_order
,
3041 .mode
= COMMAND_ANY
,
3042 .usage
= "normal|reversed",
3043 .help
= "Choose the order that harts are resumed in when `hasel` is not "
3044 "supported. Normal order is from lowest hart index to highest. "
3045 "Reversed order is from highest hart index to lowest."
3049 .handler
= riscv_set_ir
,
3050 .mode
= COMMAND_ANY
,
3051 .usage
= "[idcode|dtmcs|dmi] value",
3052 .help
= "Set IR value for specified JTAG register."
3055 .name
= "use_bscan_tunnel",
3056 .handler
= riscv_use_bscan_tunnel
,
3057 .mode
= COMMAND_ANY
,
3058 .usage
= "value [type]",
3059 .help
= "Enable or disable use of a BSCAN tunnel to reach DM. Supply "
3060 "the width of the DM transport TAP's instruction register to "
3061 "enable. Supply a value of 0 to disable. Pass A second argument "
3062 "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
3066 .name
= "set_enable_virt2phys",
3067 .handler
= riscv_set_enable_virt2phys
,
3068 .mode
= COMMAND_ANY
,
3070 .help
= "When on (default), enable translation from virtual address to "
3074 .name
= "set_ebreakm",
3075 .handler
= riscv_set_ebreakm
,
3076 .mode
= COMMAND_ANY
,
3078 .help
= "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3079 "don't trap to OpenOCD. Defaults to on."
3082 .name
= "set_ebreaks",
3083 .handler
= riscv_set_ebreaks
,
3084 .mode
= COMMAND_ANY
,
3086 .help
= "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3087 "don't trap to OpenOCD. Defaults to on."
3090 .name
= "set_ebreaku",
3091 .handler
= riscv_set_ebreaku
,
3092 .mode
= COMMAND_ANY
,
3094 .help
= "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3095 "don't trap to OpenOCD. Defaults to on."
3097 COMMAND_REGISTRATION_DONE
3101 * To be noted that RISC-V targets use the same semihosting commands as
3104 * The main reason is compatibility with existing tools. For example the
3105 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3106 * configure semihosting, which generate commands like `arm semihosting
3108 * A secondary reason is the fact that the protocol used is exactly the
3109 * one specified by ARM. If RISC-V will ever define its own semihosting
3110 * protocol, then a command like `riscv semihosting enable` will make
3111 * sense, but for now all semihosting commands are prefixed with `arm`.
3113 extern const struct command_registration semihosting_common_handlers
[];
3115 const struct command_registration riscv_command_handlers
[] = {
3118 .mode
= COMMAND_ANY
,
3119 .help
= "RISC-V Command Group",
3121 .chain
= riscv_exec_command_handlers
3125 .mode
= COMMAND_ANY
,
3126 .help
= "ARM Command Group",
3128 .chain
= semihosting_common_handlers
3130 COMMAND_REGISTRATION_DONE
3133 static unsigned riscv_xlen_nonconst(struct target
*target
)
3135 return riscv_xlen(target
);
3138 static unsigned int riscv_data_bits(struct target
*target
)
3142 return r
->data_bits(target
);
3143 return riscv_xlen(target
);
3146 struct target_type riscv_target
= {
3149 .target_create
= riscv_create_target
,
3150 .init_target
= riscv_init_target
,
3151 .deinit_target
= riscv_deinit_target
,
3152 .examine
= riscv_examine
,
3154 /* poll current target status */
3155 .poll
= old_or_new_riscv_poll
,
3158 .resume
= riscv_target_resume
,
3159 .step
= old_or_new_riscv_step
,
3161 .assert_reset
= riscv_assert_reset
,
3162 .deassert_reset
= riscv_deassert_reset
,
3164 .read_memory
= riscv_read_memory
,
3165 .write_memory
= riscv_write_memory
,
3166 .read_phys_memory
= riscv_read_phys_memory
,
3167 .write_phys_memory
= riscv_write_phys_memory
,
3169 .checksum_memory
= riscv_checksum_memory
,
3172 .virt2phys
= riscv_virt2phys
,
3174 .get_gdb_arch
= riscv_get_gdb_arch
,
3175 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
3176 .get_gdb_reg_list_noread
= riscv_get_gdb_reg_list_noread
,
3178 .add_breakpoint
= riscv_add_breakpoint
,
3179 .remove_breakpoint
= riscv_remove_breakpoint
,
3181 .add_watchpoint
= riscv_add_watchpoint
,
3182 .remove_watchpoint
= riscv_remove_watchpoint
,
3183 .hit_watchpoint
= riscv_hit_watchpoint
,
3185 .arch_state
= riscv_arch_state
,
3187 .run_algorithm
= riscv_run_algorithm
,
3189 .commands
= riscv_command_handlers
,
3191 .address_bits
= riscv_xlen_nonconst
,
3192 .data_bits
= riscv_data_bits
3195 /*** RISC-V Interface ***/
3197 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
3199 memset(r
, 0, sizeof(*r
));
3201 r
->registers_initialized
= false;
3202 r
->current_hartid
= target
->coreid
;
3203 r
->version_specific
= NULL
;
3205 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
3209 r
->mem_access_methods
[0] = RISCV_MEM_ACCESS_PROGBUF
;
3210 r
->mem_access_methods
[1] = RISCV_MEM_ACCESS_SYSBUS
;
3211 r
->mem_access_methods
[2] = RISCV_MEM_ACCESS_ABSTRACT
;
3213 r
->mem_access_progbuf_warn
= true;
3214 r
->mem_access_sysbus_warn
= true;
3215 r
->mem_access_abstract_warn
= true;
3217 INIT_LIST_HEAD(&r
->expose_csr
);
3218 INIT_LIST_HEAD(&r
->expose_custom
);
3221 static int riscv_resume_go_all_harts(struct target
*target
)
3225 LOG_DEBUG("[%s] resuming hart", target_name(target
));
3226 if (riscv_select_current_hart(target
) != ERROR_OK
)
3228 if (riscv_is_halted(target
)) {
3229 if (r
->resume_go(target
) != ERROR_OK
)
3232 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3233 target_name(target
));
3236 riscv_invalidate_register_cache(target
);
3240 int riscv_step_rtos_hart(struct target
*target
)
3243 if (riscv_select_current_hart(target
) != ERROR_OK
)
3245 LOG_DEBUG("[%s] stepping", target_name(target
));
3247 if (!riscv_is_halted(target
)) {
3248 LOG_ERROR("Hart isn't halted before single step!");
3251 riscv_invalidate_register_cache(target
);
3253 if (r
->step_current_hart(target
) != ERROR_OK
)
3255 riscv_invalidate_register_cache(target
);
3257 if (!riscv_is_halted(target
)) {
3258 LOG_ERROR("Hart was not halted after single step!");
3264 bool riscv_supports_extension(struct target
*target
, char letter
)
3268 if (letter
>= 'a' && letter
<= 'z')
3270 else if (letter
>= 'A' && letter
<= 'Z')
3274 return r
->misa
& BIT(num
);
3277 unsigned riscv_xlen(const struct target
*target
)
3283 int riscv_set_current_hartid(struct target
*target
, int hartid
)
3286 if (!r
->select_current_hart
)
3289 int previous_hartid
= riscv_current_hartid(target
);
3290 r
->current_hartid
= hartid
;
3291 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
3292 if (r
->select_current_hart(target
) != ERROR_OK
)
3298 void riscv_invalidate_register_cache(struct target
*target
)
3302 LOG_DEBUG("[%d]", target
->coreid
);
3303 register_cache_invalidate(target
->reg_cache
);
3304 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
3305 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
3309 r
->registers_initialized
= true;
3312 int riscv_current_hartid(const struct target
*target
)
3315 return r
->current_hartid
;
3318 int riscv_count_harts(struct target
*target
)
3323 if (!r
|| !r
->hart_count
)
3325 return r
->hart_count(target
);
3330 * return true iff we are guaranteed that the register will contain exactly
3331 * the value we just wrote when it's read.
3332 * If write is false:
3333 * return true iff we are guaranteed that the register will read the same
3334 * value in the future as the value we just read.
3336 static bool gdb_regno_cacheable(enum gdb_regno regno
, bool write
)
3338 /* GPRs, FPRs, vector registers are just normal data stores. */
3339 if (regno
<= GDB_REGNO_XPR31
||
3340 (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
) ||
3341 (regno
>= GDB_REGNO_V0
&& regno
<= GDB_REGNO_V31
))
3344 /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3350 case GDB_REGNO_VSTART
:
3351 case GDB_REGNO_VXSAT
:
3352 case GDB_REGNO_VXRM
:
3353 case GDB_REGNO_VLENB
:
3355 case GDB_REGNO_VTYPE
:
3356 case GDB_REGNO_MISA
:
3357 case GDB_REGNO_DCSR
:
3358 case GDB_REGNO_DSCRATCH0
:
3359 case GDB_REGNO_MSTATUS
:
3360 case GDB_REGNO_MEPC
:
3361 case GDB_REGNO_MCAUSE
:
3362 case GDB_REGNO_SATP
:
3364 * WARL registers might not contain the value we just wrote, but
3365 * these ones won't spontaneously change their value either. *
3369 case GDB_REGNO_TSELECT
: /* I think this should be above, but then it doesn't work. */
3370 case GDB_REGNO_TDATA1
: /* Changes value when tselect is changed. */
3371 case GDB_REGNO_TDATA2
: /* Changse value when tselect is changed. */
3378 * This function is called when the debug user wants to change the value of a
3379 * register. The new value may be cached, and may not be written until the hart
3381 int riscv_set_register(struct target
*target
, enum gdb_regno regid
, riscv_reg_t value
)
3384 LOG_DEBUG("[%s] %s <- %" PRIx64
, target_name(target
), gdb_regno_name(regid
), value
);
3385 assert(r
->set_register
);
3389 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3390 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&& value
== 0 &&
3391 riscv_supports_extension(target
, 'E'))
3394 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3395 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3397 int result
= r
->set_register(target
, regid
, value
);
3398 if (result
== ERROR_OK
)
3399 reg
->valid
= gdb_regno_cacheable(regid
, true);
3402 LOG_DEBUG("[%s] wrote 0x%" PRIx64
" to %s valid=%d",
3403 target_name(target
), value
, reg
->name
, reg
->valid
);
3407 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
3408 enum gdb_regno regid
)
3414 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3416 LOG_DEBUG("[%s] %s does not exist.",
3417 target_name(target
), gdb_regno_name(regid
));
3421 if (reg
&& reg
->valid
) {
3422 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
3423 LOG_DEBUG("[%s] %s: %" PRIx64
" (cached)", target_name(target
),
3424 gdb_regno_name(regid
), *value
);
3428 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3429 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&&
3430 riscv_supports_extension(target
, 'E')) {
3435 int result
= r
->get_register(target
, value
, regid
);
3437 if (result
== ERROR_OK
)
3438 reg
->valid
= gdb_regno_cacheable(regid
, false);
3440 LOG_DEBUG("[%s] %s: %" PRIx64
, target_name(target
),
3441 gdb_regno_name(regid
), *value
);
3445 bool riscv_is_halted(struct target
*target
)
3448 assert(r
->is_halted
);
3449 return r
->is_halted(target
);
3452 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
3455 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
3456 return RISCV_HALT_ERROR
;
3457 if (!riscv_is_halted(target
)) {
3458 LOG_ERROR("Hart is not halted!");
3459 return RISCV_HALT_UNKNOWN
;
3461 return r
->halt_reason(target
);
3464 size_t riscv_debug_buffer_size(struct target
*target
)
3467 return r
->debug_buffer_size
;
3470 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
3473 r
->write_debug_buffer(target
, index
, insn
);
3477 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
3480 return r
->read_debug_buffer(target
, index
);
3483 int riscv_execute_debug_buffer(struct target
*target
)
3486 return r
->execute_debug_buffer(target
);
3489 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
3492 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
3495 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
3498 r
->fill_dmi_read_u64(target
, buf
, a
);
3501 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
3504 r
->fill_dmi_nop_u64(target
, buf
);
3507 int riscv_dmi_write_u64_bits(struct target
*target
)
3510 return r
->dmi_write_u64_bits(target
);
3514 * Count triggers, and initialize trigger_count for each hart.
3515 * trigger_count is initialized even if this function fails to discover
3517 * Disable any hardware triggers that have dmode set. We can't have set them
3518 * ourselves. Maybe they're left over from some killed debug session.
3520 int riscv_enumerate_triggers(struct target
*target
)
3524 if (r
->triggers_enumerated
)
3527 r
->triggers_enumerated
= true; /* At the very least we tried. */
3529 riscv_reg_t tselect
;
3530 int result
= riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
);
3531 /* If tselect is not readable, the trigger module is likely not
3532 * implemented. There are no triggers to enumerate then and no error
3533 * should be thrown. */
3534 if (result
!= ERROR_OK
) {
3535 LOG_DEBUG("[%s] Cannot access tselect register. "
3536 "Assuming that triggers are not implemented.", target_name(target
));
3537 r
->trigger_count
= 0;
3541 for (unsigned int t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
3542 r
->trigger_count
= t
;
3544 /* If we can't write tselect, then this hart does not support triggers. */
3545 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
3547 uint64_t tselect_rb
;
3548 result
= riscv_get_register(target
, &tselect_rb
, GDB_REGNO_TSELECT
);
3549 if (result
!= ERROR_OK
)
3551 /* Mask off the top bit, which is used as tdrmode in old
3552 * implementations. */
3553 tselect_rb
&= ~(1ULL << (riscv_xlen(target
) - 1));
3554 if (tselect_rb
!= t
)
3557 result
= riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
);
3558 if (result
!= ERROR_OK
)
3561 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
3566 /* On these older cores we don't support software using
3568 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3571 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
3572 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3575 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
3576 riscv_set_register(target
, GDB_REGNO_TDATA1
, 0);
3581 riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
);
3583 LOG_INFO("[%s] Found %d triggers", target_name(target
), r
->trigger_count
);
3588 const char *gdb_regno_name(enum gdb_regno regno
)
3590 static char buf
[32];
3593 case GDB_REGNO_ZERO
:
3659 case GDB_REGNO_FPR0
:
3661 case GDB_REGNO_FPR31
:
3663 case GDB_REGNO_CSR0
:
3665 case GDB_REGNO_TSELECT
:
3667 case GDB_REGNO_TDATA1
:
3669 case GDB_REGNO_TDATA2
:
3671 case GDB_REGNO_MISA
:
3675 case GDB_REGNO_DCSR
:
3677 case GDB_REGNO_DSCRATCH0
:
3679 case GDB_REGNO_MSTATUS
:
3681 case GDB_REGNO_MEPC
:
3683 case GDB_REGNO_MCAUSE
:
3685 case GDB_REGNO_PRIV
:
3687 case GDB_REGNO_SATP
:
3689 case GDB_REGNO_VTYPE
:
3758 if (regno
<= GDB_REGNO_XPR31
)
3759 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
3760 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
3761 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
3762 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
3763 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
3765 sprintf(buf
, "gdb_regno_%d", regno
);
3770 static int register_get(struct reg
*reg
)
3772 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3773 struct target
*target
= reg_info
->target
;
3776 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3777 if (!r
->get_register_buf
) {
3778 LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3779 gdb_regno_name(reg
->number
));
3783 if (r
->get_register_buf(target
, reg
->value
, reg
->number
) != ERROR_OK
)
3787 int result
= riscv_get_register(target
, &value
, reg
->number
);
3788 if (result
!= ERROR_OK
)
3790 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3792 reg
->valid
= gdb_regno_cacheable(reg
->number
, false);
3793 char *str
= buf_to_hex_str(reg
->value
, reg
->size
);
3794 LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target
),
3795 str
, reg
->name
, reg
->valid
);
3800 static int register_set(struct reg
*reg
, uint8_t *buf
)
3802 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3803 struct target
*target
= reg_info
->target
;
3806 char *str
= buf_to_hex_str(buf
, reg
->size
);
3807 LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target
),
3808 str
, reg
->name
, reg
->valid
);
3811 /* Exit early for writing x0, which on the hardware would be ignored, and we
3812 * don't want to update our cache. */
3813 if (reg
->number
== GDB_REGNO_ZERO
)
3816 memcpy(reg
->value
, buf
, DIV_ROUND_UP(reg
->size
, 8));
3817 reg
->valid
= gdb_regno_cacheable(reg
->number
, true);
3819 if (reg
->number
== GDB_REGNO_TDATA1
||
3820 reg
->number
== GDB_REGNO_TDATA2
) {
3821 r
->manual_hwbp_set
= true;
3822 /* When enumerating triggers, we clear any triggers with DMODE set,
3823 * assuming they were left over from a previous debug session. So make
3824 * sure that is done before a user might be setting their own triggers.
3826 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
3830 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3831 if (!r
->set_register_buf
) {
3832 LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3833 gdb_regno_name(reg
->number
));
3837 if (r
->set_register_buf(target
, reg
->number
, reg
->value
) != ERROR_OK
)
3840 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
3841 if (riscv_set_register(target
, reg
->number
, value
) != ERROR_OK
)
3848 static struct reg_arch_type riscv_reg_arch_type
= {
3849 .get
= register_get
,
3858 static int cmp_csr_info(const void *p1
, const void *p2
)
3860 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
3863 int riscv_init_registers(struct target
*target
)
3867 riscv_free_registers(target
);
3869 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
3870 if (!target
->reg_cache
)
3872 target
->reg_cache
->name
= "RISC-V Registers";
3873 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
3875 if (!list_empty(&info
->expose_custom
)) {
3876 range_list_t
*entry
;
3877 list_for_each_entry(entry
, &info
->expose_custom
, list
)
3878 target
->reg_cache
->num_regs
+= entry
->high
- entry
->low
+ 1;
3881 LOG_DEBUG("create register cache for %d registers",
3882 target
->reg_cache
->num_regs
);
3884 target
->reg_cache
->reg_list
=
3885 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
3886 if (!target
->reg_cache
->reg_list
)
3889 const unsigned int max_reg_name_len
= 12;
3890 free(info
->reg_names
);
3892 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
3893 if (!info
->reg_names
)
3895 char *reg_name
= info
->reg_names
;
3897 static struct reg_feature feature_cpu
= {
3898 .name
= "org.gnu.gdb.riscv.cpu"
3900 static struct reg_feature feature_fpu
= {
3901 .name
= "org.gnu.gdb.riscv.fpu"
3903 static struct reg_feature feature_csr
= {
3904 .name
= "org.gnu.gdb.riscv.csr"
3906 static struct reg_feature feature_vector
= {
3907 .name
= "org.gnu.gdb.riscv.vector"
3909 static struct reg_feature feature_virtual
= {
3910 .name
= "org.gnu.gdb.riscv.virtual"
3912 static struct reg_feature feature_custom
= {
3913 .name
= "org.gnu.gdb.riscv.custom"
3916 /* These types are built into gdb. */
3917 static struct reg_data_type type_ieee_single
= { .type
= REG_TYPE_IEEE_SINGLE
, .id
= "ieee_single" };
3918 static struct reg_data_type type_ieee_double
= { .type
= REG_TYPE_IEEE_DOUBLE
, .id
= "ieee_double" };
3919 static struct reg_data_type_union_field single_double_fields
[] = {
3920 {"float", &type_ieee_single
, single_double_fields
+ 1},
3921 {"double", &type_ieee_double
, NULL
},
3923 static struct reg_data_type_union single_double_union
= {
3924 .fields
= single_double_fields
3926 static struct reg_data_type type_ieee_single_double
= {
3927 .type
= REG_TYPE_ARCH_DEFINED
,
3929 .type_class
= REG_TYPE_CLASS_UNION
,
3930 .reg_type_union
= &single_double_union
3932 static struct reg_data_type type_uint8
= { .type
= REG_TYPE_UINT8
, .id
= "uint8" };
3933 static struct reg_data_type type_uint16
= { .type
= REG_TYPE_UINT16
, .id
= "uint16" };
3934 static struct reg_data_type type_uint32
= { .type
= REG_TYPE_UINT32
, .id
= "uint32" };
3935 static struct reg_data_type type_uint64
= { .type
= REG_TYPE_UINT64
, .id
= "uint64" };
3936 static struct reg_data_type type_uint128
= { .type
= REG_TYPE_UINT128
, .id
= "uint128" };
3938 /* This is roughly the XML we want:
3939 * <vector id="bytes" type="uint8" count="16"/>
3940 * <vector id="shorts" type="uint16" count="8"/>
3941 * <vector id="words" type="uint32" count="4"/>
3942 * <vector id="longs" type="uint64" count="2"/>
3943 * <vector id="quads" type="uint128" count="1"/>
3944 * <union id="riscv_vector_type">
3945 * <field name="b" type="bytes"/>
3946 * <field name="s" type="shorts"/>
3947 * <field name="w" type="words"/>
3948 * <field name="l" type="longs"/>
3949 * <field name="q" type="quads"/>
3953 info
->vector_uint8
.type
= &type_uint8
;
3954 info
->vector_uint8
.count
= info
->vlenb
;
3955 info
->type_uint8_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3956 info
->type_uint8_vector
.id
= "bytes";
3957 info
->type_uint8_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3958 info
->type_uint8_vector
.reg_type_vector
= &info
->vector_uint8
;
3960 info
->vector_uint16
.type
= &type_uint16
;
3961 info
->vector_uint16
.count
= info
->vlenb
/ 2;
3962 info
->type_uint16_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3963 info
->type_uint16_vector
.id
= "shorts";
3964 info
->type_uint16_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3965 info
->type_uint16_vector
.reg_type_vector
= &info
->vector_uint16
;
3967 info
->vector_uint32
.type
= &type_uint32
;
3968 info
->vector_uint32
.count
= info
->vlenb
/ 4;
3969 info
->type_uint32_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3970 info
->type_uint32_vector
.id
= "words";
3971 info
->type_uint32_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3972 info
->type_uint32_vector
.reg_type_vector
= &info
->vector_uint32
;
3974 info
->vector_uint64
.type
= &type_uint64
;
3975 info
->vector_uint64
.count
= info
->vlenb
/ 8;
3976 info
->type_uint64_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3977 info
->type_uint64_vector
.id
= "longs";
3978 info
->type_uint64_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3979 info
->type_uint64_vector
.reg_type_vector
= &info
->vector_uint64
;
3981 info
->vector_uint128
.type
= &type_uint128
;
3982 info
->vector_uint128
.count
= info
->vlenb
/ 16;
3983 info
->type_uint128_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3984 info
->type_uint128_vector
.id
= "quads";
3985 info
->type_uint128_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3986 info
->type_uint128_vector
.reg_type_vector
= &info
->vector_uint128
;
3988 info
->vector_fields
[0].name
= "b";
3989 info
->vector_fields
[0].type
= &info
->type_uint8_vector
;
3990 if (info
->vlenb
>= 2) {
3991 info
->vector_fields
[0].next
= info
->vector_fields
+ 1;
3992 info
->vector_fields
[1].name
= "s";
3993 info
->vector_fields
[1].type
= &info
->type_uint16_vector
;
3995 info
->vector_fields
[0].next
= NULL
;
3997 if (info
->vlenb
>= 4) {
3998 info
->vector_fields
[1].next
= info
->vector_fields
+ 2;
3999 info
->vector_fields
[2].name
= "w";
4000 info
->vector_fields
[2].type
= &info
->type_uint32_vector
;
4002 info
->vector_fields
[1].next
= NULL
;
4004 if (info
->vlenb
>= 8) {
4005 info
->vector_fields
[2].next
= info
->vector_fields
+ 3;
4006 info
->vector_fields
[3].name
= "l";
4007 info
->vector_fields
[3].type
= &info
->type_uint64_vector
;
4009 info
->vector_fields
[2].next
= NULL
;
4011 if (info
->vlenb
>= 16) {
4012 info
->vector_fields
[3].next
= info
->vector_fields
+ 4;
4013 info
->vector_fields
[4].name
= "q";
4014 info
->vector_fields
[4].type
= &info
->type_uint128_vector
;
4016 info
->vector_fields
[3].next
= NULL
;
4018 info
->vector_fields
[4].next
= NULL
;
4020 info
->vector_union
.fields
= info
->vector_fields
;
4022 info
->type_vector
.type
= REG_TYPE_ARCH_DEFINED
;
4023 info
->type_vector
.id
= "riscv_vector";
4024 info
->type_vector
.type_class
= REG_TYPE_CLASS_UNION
;
4025 info
->type_vector
.reg_type_union
= &info
->vector_union
;
4027 struct csr_info csr_info
[] = {
4028 #define DECLARE_CSR(name, number) { number, #name },
4029 #include "encoding.h"
4032 /* encoding.h does not contain the registers in sorted order. */
4033 qsort(csr_info
, ARRAY_SIZE(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
4034 unsigned csr_info_index
= 0;
4036 int custom_within_range
= 0;
4038 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
4039 if (!shared_reg_info
)
4041 shared_reg_info
->target
= target
;
4043 /* When gdb requests register N, gdb_get_register_packet() assumes that this
4044 * is register at index N in reg_list. So if there are certain registers
4045 * that don't exist, we need to leave holes in the list (or renumber, but
4046 * it would be nice not to have yet another set of numbers to translate
4048 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
4049 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
4053 r
->type
= &riscv_reg_arch_type
;
4054 r
->arch_info
= shared_reg_info
;
4056 r
->size
= riscv_xlen(target
);
4057 /* r->size is set in riscv_invalidate_register_cache, maybe because the
4058 * target is in theory allowed to change XLEN on us. But I expect a lot
4059 * of other things to break in that case as well. */
4060 if (number
<= GDB_REGNO_XPR31
) {
4061 r
->exist
= number
<= GDB_REGNO_XPR15
||
4062 !riscv_supports_extension(target
, 'E');
4063 /* TODO: For now we fake that all GPRs exist because otherwise gdb
4066 r
->caller_save
= true;
4068 case GDB_REGNO_ZERO
:
4165 r
->group
= "general";
4166 r
->feature
= &feature_cpu
;
4167 } else if (number
== GDB_REGNO_PC
) {
4168 r
->caller_save
= true;
4169 sprintf(reg_name
, "pc");
4170 r
->group
= "general";
4171 r
->feature
= &feature_cpu
;
4172 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
4173 r
->caller_save
= true;
4174 if (riscv_supports_extension(target
, 'D')) {
4176 if (riscv_supports_extension(target
, 'F'))
4177 r
->reg_data_type
= &type_ieee_single_double
;
4179 r
->reg_data_type
= &type_ieee_double
;
4180 } else if (riscv_supports_extension(target
, 'F')) {
4181 r
->reg_data_type
= &type_ieee_single
;
4265 case GDB_REGNO_FS10
:
4268 case GDB_REGNO_FS11
:
4277 case GDB_REGNO_FT10
:
4280 case GDB_REGNO_FT11
:
4285 r
->feature
= &feature_fpu
;
4286 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
4288 r
->feature
= &feature_csr
;
4289 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
4291 while (csr_info
[csr_info_index
].number
< csr_number
&&
4292 csr_info_index
< ARRAY_SIZE(csr_info
) - 1) {
4295 if (csr_info
[csr_info_index
].number
== csr_number
) {
4296 r
->name
= csr_info
[csr_info_index
].name
;
4298 sprintf(reg_name
, "csr%d", csr_number
);
4299 /* Assume unnamed registers don't exist, unless we have some
4300 * configuration that tells us otherwise. That's important
4301 * because eg. Eclipse crashes if a target has too many
4302 * registers, and apparently has no way of only showing a
4303 * subset of registers in any case. */
4307 switch (csr_number
) {
4311 r
->exist
= riscv_supports_extension(target
, 'F');
4313 r
->feature
= &feature_fpu
;
4319 case CSR_SCOUNTEREN
:
4325 r
->exist
= riscv_supports_extension(target
, 'S');
4329 /* "In systems with only M-mode, or with both M-mode and
4330 * U-mode but without U-mode trap support, the medeleg and
4331 * mideleg registers should not exist." */
4332 r
->exist
= riscv_supports_extension(target
, 'S') ||
4333 riscv_supports_extension(target
, 'N');
4341 case CSR_HPMCOUNTER3H
:
4342 case CSR_HPMCOUNTER4H
:
4343 case CSR_HPMCOUNTER5H
:
4344 case CSR_HPMCOUNTER6H
:
4345 case CSR_HPMCOUNTER7H
:
4346 case CSR_HPMCOUNTER8H
:
4347 case CSR_HPMCOUNTER9H
:
4348 case CSR_HPMCOUNTER10H
:
4349 case CSR_HPMCOUNTER11H
:
4350 case CSR_HPMCOUNTER12H
:
4351 case CSR_HPMCOUNTER13H
:
4352 case CSR_HPMCOUNTER14H
:
4353 case CSR_HPMCOUNTER15H
:
4354 case CSR_HPMCOUNTER16H
:
4355 case CSR_HPMCOUNTER17H
:
4356 case CSR_HPMCOUNTER18H
:
4357 case CSR_HPMCOUNTER19H
:
4358 case CSR_HPMCOUNTER20H
:
4359 case CSR_HPMCOUNTER21H
:
4360 case CSR_HPMCOUNTER22H
:
4361 case CSR_HPMCOUNTER23H
:
4362 case CSR_HPMCOUNTER24H
:
4363 case CSR_HPMCOUNTER25H
:
4364 case CSR_HPMCOUNTER26H
:
4365 case CSR_HPMCOUNTER27H
:
4366 case CSR_HPMCOUNTER28H
:
4367 case CSR_HPMCOUNTER29H
:
4368 case CSR_HPMCOUNTER30H
:
4369 case CSR_HPMCOUNTER31H
:
4372 case CSR_MHPMCOUNTER3H
:
4373 case CSR_MHPMCOUNTER4H
:
4374 case CSR_MHPMCOUNTER5H
:
4375 case CSR_MHPMCOUNTER6H
:
4376 case CSR_MHPMCOUNTER7H
:
4377 case CSR_MHPMCOUNTER8H
:
4378 case CSR_MHPMCOUNTER9H
:
4379 case CSR_MHPMCOUNTER10H
:
4380 case CSR_MHPMCOUNTER11H
:
4381 case CSR_MHPMCOUNTER12H
:
4382 case CSR_MHPMCOUNTER13H
:
4383 case CSR_MHPMCOUNTER14H
:
4384 case CSR_MHPMCOUNTER15H
:
4385 case CSR_MHPMCOUNTER16H
:
4386 case CSR_MHPMCOUNTER17H
:
4387 case CSR_MHPMCOUNTER18H
:
4388 case CSR_MHPMCOUNTER19H
:
4389 case CSR_MHPMCOUNTER20H
:
4390 case CSR_MHPMCOUNTER21H
:
4391 case CSR_MHPMCOUNTER22H
:
4392 case CSR_MHPMCOUNTER23H
:
4393 case CSR_MHPMCOUNTER24H
:
4394 case CSR_MHPMCOUNTER25H
:
4395 case CSR_MHPMCOUNTER26H
:
4396 case CSR_MHPMCOUNTER27H
:
4397 case CSR_MHPMCOUNTER28H
:
4398 case CSR_MHPMCOUNTER29H
:
4399 case CSR_MHPMCOUNTER30H
:
4400 case CSR_MHPMCOUNTER31H
:
4401 r
->exist
= riscv_xlen(target
) == 32;
4410 r
->exist
= riscv_supports_extension(target
, 'V');
4414 if (!r
->exist
&& !list_empty(&info
->expose_csr
)) {
4415 range_list_t
*entry
;
4416 list_for_each_entry(entry
, &info
->expose_csr
, list
)
4417 if ((entry
->low
<= csr_number
) && (csr_number
<= entry
->high
)) {
4420 r
->name
= entry
->name
;
4423 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4424 csr_number
, entry
->name
? entry
->name
: reg_name
);
4431 } else if (number
== GDB_REGNO_PRIV
) {
4432 sprintf(reg_name
, "priv");
4433 r
->group
= "general";
4434 r
->feature
= &feature_virtual
;
4437 } else if (number
>= GDB_REGNO_V0
&& number
<= GDB_REGNO_V31
) {
4438 r
->caller_save
= false;
4439 r
->exist
= riscv_supports_extension(target
, 'V') && info
->vlenb
;
4440 r
->size
= info
->vlenb
* 8;
4441 sprintf(reg_name
, "v%d", number
- GDB_REGNO_V0
);
4442 r
->group
= "vector";
4443 r
->feature
= &feature_vector
;
4444 r
->reg_data_type
= &info
->type_vector
;
4446 } else if (number
>= GDB_REGNO_COUNT
) {
4447 /* Custom registers. */
4448 assert(!list_empty(&info
->expose_custom
));
4450 range_list_t
*range
= list_first_entry(&info
->expose_custom
, range_list_t
, list
);
4452 unsigned custom_number
= range
->low
+ custom_within_range
;
4454 r
->group
= "custom";
4455 r
->feature
= &feature_custom
;
4456 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
4459 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
4460 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
4461 sprintf(reg_name
, "custom%d", custom_number
);
4465 r
->name
= range
->name
;
4468 LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4469 number
, range
->name
? range
->name
: reg_name
);
4471 custom_within_range
++;
4472 if (custom_within_range
> range
->high
- range
->low
) {
4473 custom_within_range
= 0;
4474 list_rotate_left(&info
->expose_custom
);
4480 reg_name
+= strlen(reg_name
) + 1;
4481 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
4484 r
->value
= calloc(1, DIV_ROUND_UP(r
->size
, 8));
4491 void riscv_add_bscan_tunneled_scan(struct target
*target
, struct scan_field
*field
,
4492 riscv_bscan_tunneled_scan_context_t
*ctxt
)
4494 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
4496 memset(ctxt
->tunneled_dr
, 0, sizeof(ctxt
->tunneled_dr
));
4497 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
4498 ctxt
->tunneled_dr
[3].num_bits
= 1;
4499 ctxt
->tunneled_dr
[3].out_value
= bscan_one
;
4500 ctxt
->tunneled_dr
[2].num_bits
= 7;
4501 ctxt
->tunneled_dr_width
= field
->num_bits
;
4502 ctxt
->tunneled_dr
[2].out_value
= &ctxt
->tunneled_dr_width
;
4503 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4504 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4506 ctxt
->tunneled_dr
[1].num_bits
= field
->num_bits
+ 1;
4507 ctxt
->tunneled_dr
[1].out_value
= field
->out_value
;
4508 ctxt
->tunneled_dr
[1].in_value
= field
->in_value
;
4510 ctxt
->tunneled_dr
[0].num_bits
= 3;
4511 ctxt
->tunneled_dr
[0].out_value
= bscan_zero
;
4513 /* BSCAN_TUNNEL_NESTED_TAP */
4514 ctxt
->tunneled_dr
[0].num_bits
= 1;
4515 ctxt
->tunneled_dr
[0].out_value
= bscan_one
;
4516 ctxt
->tunneled_dr
[1].num_bits
= 7;
4517 ctxt
->tunneled_dr_width
= field
->num_bits
;
4518 ctxt
->tunneled_dr
[1].out_value
= &ctxt
->tunneled_dr_width
;
4519 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4520 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4521 ctxt
->tunneled_dr
[2].num_bits
= field
->num_bits
+ 1;
4522 ctxt
->tunneled_dr
[2].out_value
= field
->out_value
;
4523 ctxt
->tunneled_dr
[2].in_value
= field
->in_value
;
4524 ctxt
->tunneled_dr
[3].num_bits
= 3;
4525 ctxt
->tunneled_dr
[3].out_value
= bscan_zero
;
4527 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(ctxt
->tunneled_dr
), ctxt
->tunneled_dr
, TAP_IDLE
);