s3c6410 chip
[openocd.git] / src / target / target / pxa255.cfg
1 jtag_device 5 0x1 0x1f 0x1e
2 jtag_nsrst_delay 200
3 jtag_ntrst_delay 200
4
5 target create target0 xscale -endian little -chain-position 0 -variant pxa255
6 [new_target_name] configure -event reset-init {
7 xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
8 #
9 # setup GPIO
10 #
11 mww 0x40E00018 0x00008000 #CPSR0
12 sleep 20
13 mww 0x40E0001C 0x00000002 #GPSR1
14 sleep 20
15 mww 0x40E00020 0x00000008 #GPSR2
16 sleep 20
17 mww 0x40E0000C 0x00008000 #GPDR0
18 sleep 20
19 mww 0x40E00054 0x80000000 #GAFR0_L
20 sleep 20
21 mww 0x40E00058 0x00188010 #GAFR0_H
22 sleep 20
23 mww 0x40E0005C 0x60908018 #GAFR1_L
24 sleep 20
25 mww 0x40E0000C 0x0280E000 #GPDR0
26 sleep 20
27 mww 0x40E00010 0x821C88B2 #GPDR1
28 sleep 20
29 mww 0x40E00014 0x000F03DB #GPDR2
30 sleep 20
31 mww 0x40E00000 0x000F03DB #GPLR0
32 sleep 20
33
34
35 mww 0x40F00004 0x00000020 #PSSR
36 sleep 20
37
38 #
39 # setup memory controller
40 #
41 mww 0x48000008 0x01111998 #MSC0
42 sleep 20
43 mww 0x48000010 0x00047ff0 #MSC2
44 sleep 20
45 mww 0x48000014 0x00000000 #MECR
46 sleep 20
47 mww 0x48000028 0x00010504 #MCMEM0
48 sleep 20
49 mww 0x4800002C 0x00010504 #MCMEM1
50 sleep 20
51 mww 0x48000030 0x00010504 #MCATT0
52 sleep 20
53 mww 0x48000034 0x00010504 #MCATT1
54 sleep 20
55 mww 0x48000038 0x00004715 #MCIO0
56 sleep 20
57 mww 0x4800003C 0x00004715 #MCIO1
58 sleep 20
59 #
60 mww 0x48000004 0x03CA4018 #MDREF
61 sleep 20
62 mww 0x48000004 0x004B4018 #MDREF
63 sleep 20
64 mww 0x48000004 0x000B4018 #MDREF
65 sleep 20
66 mww 0x48000004 0x000BC018 #MDREF
67 sleep 20
68 mww 0x48000000 0x00001AC8 #MDCNFG
69 sleep 20
70
71 sleep 20
72
73 mww 0x48000000 0x00001AC9 #MDCNFG
74 sleep 20
75 mww 0x48000040 0x00000000 #MDMRS
76 sleep 20
77 }
78
79 reset_config trst_and_srst
80
81
82
83 #xscale debug_handler 0 0xFFFF0800 # debug handler base address
84

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